Integrated Photonic Computing Engine for Concurrent Optical Computing

Integrated Photonic Computing Engine for Concurrent Optical Computing | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Article Integrated Photonic Computing Engine for Concurrent Optical Computing Jianping Yao, Sheng Dong, Ruiqi Zheng, Huan Rao, Junyi Zhang, and 4 more This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-6587390/v1 This work is licensed under a CC BY 4.0 License Status: Under Review Version 1 posted You are reading this latest preprint version Abstract Optical networks with parallel processing capabilities are significant in advancing high-speed data computing and large-scale data processing by providing ultra-width computational bandwidth. In this paper, we present a photonic integrated processor that can be segmented into multiple functional blocks, to enable compact and reconfigurable matrix operations for multiple parallel computational tasks. Fabricated on a silicon-on-insulator (SOI) platform, the photonic integrated processor supports fully reconfigurable optical matrix operations. By segmenting the chip into multiple functional blocks, it enables optical matrix operations of various sizes, offering great flexibility and scalability for parallel computational tasks. Specifically, we utilize this processor to perform optical convolution operations with various kernel sizes, including reconfigurable three-channel 1×1 convolution kernels and 2×2 real-valued convolution kernels, implemented within distinct segmented blocks of the chip. The multichannel optical 1×1 convolution operation is experimentally validated by using the deep residual U-Net, demonstrating precise segmentation of pneumonia lesion region in lung computed tomography (CT) images. In addition, the capability of the 2×2 optical convolution operation is also experimentally validated by constructing an optical convolution layer and integrating an electrical fully connected layer, achieving ten-class classification of handwritten digit images. The photonic integrated processor features high scalability and robust parallel computational capability, positioning it a promising candidate for applications in optical neural networks. Physical sciences/Optics and photonics/Applied optics/Microwave photonics Physical sciences/Optics and photonics/Applied optics/Integrated optics photonic integrated processor multiple parallel computational tasks reconfigurable optical matrix operation optical convolution operation Full Text Additional Declarations There is NO Competing Interest. Cite Share Download PDF Status: Under Review Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. 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Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-6587390","acceptedTermsAndConditions":true,"allowDirectSubmit":false,"archivedVersions":[],"articleType":"Article","associatedPublications":[],"authors":[{"id":463871726,"identity":"b004fb56-38af-45d1-aebc-e1d44d527b08","order_by":0,"name":"Jianping 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In this paper, we present a photonic integrated processor that can be segmented into multiple functional blocks, to enable compact and reconfigurable matrix operations for multiple parallel computational tasks. Fabricated on a silicon-on-insulator (SOI) platform, the photonic integrated processor supports fully reconfigurable optical matrix operations. By segmenting the chip into multiple functional blocks, it enables optical matrix operations of various sizes, offering great flexibility and scalability for parallel computational tasks. Specifically, we utilize this processor to perform optical convolution operations with various kernel sizes, including reconfigurable three-channel 1×1 convolution kernels and 2×2 real-valued convolution kernels, implemented within distinct segmented blocks of the chip. The multichannel optical 1×1 convolution operation is experimentally validated by using the deep residual U-Net, demonstrating precise segmentation of pneumonia lesion region in lung computed tomography (CT) images. In addition, the capability of the 2×2 optical convolution operation is also experimentally validated by constructing an optical convolution layer and integrating an electrical fully connected layer, achieving ten-class classification of handwritten digit images. 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