Explainable Machine Learning Framework for RTL Timing Prediction: Bridging the Gap Between Black-Box AI and Hardware Design

Explainable Machine Learning Framework for RTL Timing Prediction: Bridging the Gap Between Black-Box AI and Hardware Design | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Article Explainable Machine Learning Framework for RTL Timing Prediction: Bridging the Gap Between Black-Box AI and Hardware Design S. Eshwar Rao This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-8489997/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract In modern VLSI design, achieving timing closure is a critical and time-consuming bottleneck. Tradi- tional Static Timing Analysis (STA) tools are ac- curate but computationally expensive, often requir- ing hours or days for full chip analysis. This de- lay hinders rapid design exploration at the Register- Transfer Level (RTL). While Machine Learning (ML) models have shown promise, they often suffer from the “Black Box” problem. Here, we present a dual- phase framework integrating Graph Neural Networks (GNNs) with eXplainable AI (XAI) to achieve ac- celerated and transparent timing closure. By repre- senting circuit topology via the Graph Laplacian and modeling thermal dissipation as a diffusive process, our model achieves a 74.4% error reduction over base- line statistical models and enables Zero-Shot Trans- fer Learning Physical sciences/Engineering/Electrical and electronic engineering Physical sciences/Nanoscience and technology/Techniques and instrumentation/Design, synthesis and processing RTL Timing Graph Neural Networks SHAP LIME VLSI Design Thermodynamic Intelligence Full Text Additional Declarations There is NO Competing Interest. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-8489997","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Article","associatedPublications":[],"authors":[{"id":569462897,"identity":"7dce1086-9e01-4507-aabd-dd4a8d593a15","order_by":0,"name":"S. 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Tradi-\r\ntional Static Timing Analysis (STA) tools are ac-\r\ncurate but computationally expensive, often requir-\r\ning hours or days for full chip analysis. This de-\r\nlay hinders rapid design exploration at the Register-\r\nTransfer Level (RTL). While Machine Learning (ML)\r\nmodels have shown promise, they often suffer from\r\nthe “Black Box” problem. Here, we present a dual-\r\nphase framework integrating Graph Neural Networks\r\n(GNNs) with eXplainable AI (XAI) to achieve ac-\r\ncelerated and transparent timing closure. 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