A Capacitance Based Threshold Voltage analysis of raised source drain Junctionless field effect transistor

A Capacitance Based Threshold Voltage analysis of raised source drain Junctionless field effect transistor | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article A Capacitance Based Threshold Voltage analysis of raised source drain Junctionless field effect transistor Rikhit Swargiary, Kaushik Chandra Deva Sarma This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-6593959/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract The evolution of transistor technology has led to the emergence of Junctionless Field-Effect Transistors (JLFETs) as promising alternatives to conventional MOSFETs, offering simplified fabrication and superior electrostatic control. Among them, Raised Source Drain Double gate JLFETs (RSD-JLFETs) exhibit enhanced performance characteristics, making them suitable for nanoscale applications. This paper presents a capacitance-based analytical method for accurately determining the threshold voltage of RSD-JLFETs. The model defines threshold voltage as the gate voltage at which the depletion width equals the silicon body thickness, marking the onset of conduction. Unlike traditional current-based methods, this approach utilizes the gate-to-channel capacitance transition to extract threshold voltage (Vth), incorporating critical design parameters such as gate work function, oxide thickness, channel length, dielectric constant, drain voltage, and temperature. The model is validated through extensive TCAD simulations using various high-k dielectrics and gate materials, demonstrating strong agreement with conventional techniques. The validation of the model is also done by comparison with experimental results by fabricating the device on SOI wafer. This method offers a physically insightful, computationally efficient tool for Vth estimation, aiding the design and optimization of next-generation low-power JLFET devices. JLFET Raised Source Drain Threshold Voltage TCAD Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 1. Introduction With the Continuing advances in semiconductor technology new transistor architecture like JLFETs has evolved. Junctionless Field-Effect Transistors JLFETs eliminate traditional pn junctions, simplifying fabrication. The foundational insights into the properties and design considerations of Junctionless nanowire transistors, highlighting their potential for scaling and reduced fabrication complexity in [ 1 – 3 ]. Further, [ 4 ] elaborated on the physics and operating principles of these devices, cementing their role in emerging low-power and high-performance nano systems. The [ 5 ] introduced the CJM compact model for double-gate junctionless FETs, offering an accurate analytical framework for simulating device characteristics. Threshold voltage modelling in JLFETs has been extensively studied. The impact of nanowire width variations on threshold voltage sensitivity, emphasizing precise dimension control is studied in [ 6 ] and [ 7 ] provided an analytical approach to determine the threshold voltage in nanowire transistors, highlighting the role of doping concentration and device geometry. A quasi-two-dimensional threshold voltage model for short-channel junctionless double-gate MOSFETs is developed in [ 8 ], improving accuracy in predicting variations due to short-channel effects. Similarly, [ 9 ] proposed an analytical model incorporating a vertical Gaussian-like doping profile, demonstrating its influence on device electrostatics and performance. Further refinements to threshold voltage models have been proposed for different JLFET architectures. In [ 10 ] extended modelling to tri-gate JLFETs by including substrate bias effects, while [ 11 ] focused on threshold voltage variability due to process variations and doping inhomogeneities. The [ 12 ] developed a physics-based model addressing structural and doping asymmetry in double-gate JLFETs, improving insights into stability and design optimization. Recent advancements have expanded threshold voltage modelling to novel architectures. Graded-doped junctionless gate-all-around MOSFETs [ 13 ], investigated the impact of doping gradient on subthreshold characteristics and [ 14 ] modelled threshold voltage variations in ultra-thin nanotube junctionless double-gate-all-around MOSFETs, considering core-and-outer gate interactions. Similarly, [ 15 ] studied threshold voltage and flat band voltage for normally-on JLFETs, enhancing understanding of their turn-on characteristics. Raut and Panda [ 16 ] developed a threshold voltage model for N + pocket vertical junctionless TFETs, demonstrating their potential as label-free biosensors for biomedical applications and [ 17 ] analysed raised source/drain dopingless junctionless accumulation mode FETs, focusing on design optimizations to improve performance. The electrical properties of raised source/drain junctionless thin-film transistors with a dual-gate structure [ 18 ], provides valuable insights into their electronic behavior. Sarma et al. [ 19 ] conducted a simulation study on raised source/drain double-gate junctionless FETs, evaluating their performance under different conditions and offering computational insights for future research. This paper focuses on developing of an capacitance based analytical model for the Vth of a raised source drain JLFET, offering deeper physical insight. The device is simulated on TCAD 2D device simulator and fabricated on SOI wafer. The results from simulated device fabricated device are compared with the mathematical model developed. 2. METHODOLOGY The RSD- DG JLFET is a novel variant of the conventional Junctionless FET that offers improved electrostatic control and simplified fabrication. In the RSD-JLFET architecture, the source and drain regions are physically elevated above the channel, which allows for better isolation and reduced short-channel effects. This design facilitates enhanced control over the channel potential and minimizes leakage currents, making it highly suitable for ultra-scaled and low-power applications. In this work, a capacitance-based analytical approach is adopted to determine the Vth of the RSD-DG JLFET. Threshold voltage is defined as the gate voltage at which the depletion region spans the entire body thickness, beyond which the device transits to the conducting state. Rather than relying on the conventional drain current method, the proposed method focuses on the gate-to-channel capacitance response. The capacitance variation is monitored as a function of gate voltage, and the inflection point where the depletion width equals the silicon body thickness is identified as the threshold voltage. The analytical model incorporates various device parameters including gate work function, gate oxide thickness, silicon film thickness, dielectric constant, drain voltage and temperature. These parameters influence the electrostatics of the device and thus impact the capacitance profile. To validate the analytical results, simulations and experimental were performed. The structures employed different combinations of dielectric constants and gate work functions to assess the accuracy and applicability of the proposed model under varying conditions. 3. DETERMINATION OF THRESHOLD VOLTAGE In a double gate junctionless FET the threshold voltage is determined by the balanced of capacitance in the device. At the threshold voltage \(\:{V}_{th}\:\) the total capacitance of the system must be equal to the equivalent capacitance derived from electrostatics. At \(\:{V}_{th}\:\) = \(\:{V}_{g}\) the capacitance structure consists of \(\:{C}_{1}\:\) and \(\:{C}_{2}\) . Since the system is symmetric: $$\:{C}_{1}\:=\:{C}_{2}={C}_{ox}$$ The gate capacitance \(\:{C}_{ox}\:\) arises due to the oxide layer separating the gate from the channel can be expressed as $$\:{C}_{ox}=\frac{{Є}_{ox}}{{T}_{ox}}$$ 1 where \(\:{T}_{ox}\) ​ is the oxide thickness and \(\:{Є}_{ox}\) is the permittivity of the oxide material. The semiconductor region between the gates introduces an additional depletion capacitance which is given by $$\:{C}_{Semi}=\frac{{2Є}_{si}}{{T}_{si}}$$ 2 where \(\:{T}_{si}\) is the thickness of the silicon channel and \(\:{Є}_{si}\) is the permittivity of silicon. The lateral capacitance \(\:{C}_{1}\:\) and \(\:{C}_{2}\) are in series with the semiconductor capacitance: $$\:{C}_{total}={\left(\frac{2}{{C}_{ox}}+\frac{1}{{C}_{semi}}\right)}^{-1}$$ $$\:{C}_{total}={\left(\frac{2{T}_{ox}}{{Є}_{ox}}+\frac{{t}_{si}}{2{Є}_{si}}\right)}^{-1}$$ 3 At the threshold voltage, the equivalent capacitance is derived from the depletion charge in the semiconductor: $$\:{C}_{eq}=\frac{dQ}{dV}$$ 4 The depletion charge per unit area is $$\:{Q}_{eq}=\text{q}{N}_{d}{t}_{si}$$ 5 Differentiating with respect to gate voltage \(\:{V}_{g}\) : $$\:{C}_{eq}=\frac{\text{q}{N}_{d}{t}_{si}}{{V}_{th}}$$ 6 By equating the total capacitance to the equivalent capacitance: $$\:{C}_{eq}=\:{C}_{total}$$ $$\:{\left(\frac{2{T}_{ox}}{{Є}_{ox}}+\frac{{t}_{si}}{2{Є}_{si}}\right)}^{-1}=\:\frac{\text{q}{N}_{d}{t}_{si}}{{V}_{th}}$$ $$\:{V}_{th}=\:\text{q}{N}_{d}{t}_{si}\left(\frac{2{T}_{ox}}{{Є}_{ox}}+\frac{{t}_{si}}{2{Є}_{si}}\right)$$ 7 The threshold voltage in Eq. ( 7 ) is applicable for raised source drain structure also because in calculating threshold voltage the channel depletion layer is considered and source drain layer is not considered because the depletion layer at the center will start removing without the effect of source drain region. 4. RESULTS AND DISCUSSION This paper introduced a capacitance based model for threshold voltage of a Junctionless transistor which has been developed. The developed model RSD-DG JLFET has been compared with simulated results from Cogenda Visual TCAD 2D device simulator and experimental results for the purpose of validating the model. 4.1 Comparison with simulation results The threshold voltage variation with gate oxide thickness, dielectric constant of gate dielectric, channel length and temperature obtained from the mathematical model has been compared with that obtained from TCAD numerical simulation. The structural overview of the RSD-DG-JLFET is illustrated in Fig. 1 , providing a detailed representation of its design and key features. The simulation results obtained from the developed model have been systematically compared with the mathematical model. The proposed model demonstrates a high degree of accuracy, with a deviation of less than 5% when compared to numerical simulations. Furthermore, the obtained results and their comparisons with TCAD simulations are graphically represented in the subsequent figures, providing a clear visualization of the model’s performance. These comparative analyses affirm the validity and robustness of the developed analytical approach, making it a valuable tool for future research and development in Junctionless Transistor technology. In a raised source drain JLFET, the threshold voltage \(\:{V}_{th}\) is significantly influenced by the work function of the gate material. The Fig. 2 . shows the variation of threshold voltage with gate oxide thickness. From the figure it is clear that gate loses control over the channel region for thicker gate oxide. To achieve a suitable positive threshold voltage value at a short channel the gate oxide and channel region should be very thin. The model is in close agreement with TCAD simulation results. The Fig. 3 . shows the variation of threshold voltage with Dielectric constant of Gate Dielectric. It has been observed that the value of the dielectric constant of gate dielectric increase with the threshold voltage rises from 0.4 V to 0.8 V. This occurs because a higher dielectric constant enhances gate capacitance, leading to stronger electrostatic control over the channel. Using high-k dielectrics in JLFETs helps improve device performance by reducing leakage current and improving gate control making them suitable for low-power applications. However, a very high dielectric constant can lead to undesirable effects such as threshold voltage instability and increased interface trap densities. Figure. 4 illustrates the effect of channel length on the \(\:{V}_{th}\) in a raised source drain JLFET. As the channel length increases from 20 nm to 30 nm, the threshold voltage rises from 0.4 V to 0.48 V. This occurs because longer channels reduce short-channel effects, leading to better electrostatic control by the gate. A shorter channel allows more influence from the drain, which can lower \(\:{V}_{th}\) . The Figure. 5 shows the effect of temperature on the threshold voltage \(\:{V}_{th}\) in a proposed structure. As the temperature increases from 350 K to 650 K, the threshold voltage decreases from 0.4 V to 0.1 V. This trend is due to the intrinsic properties of semiconductors, where higher temperatures lead to increased carrier concentration and reduced bandgap energy. As a result, more free carriers are available in the channel, making it easier for the device to turn on at lower gate voltages, effectively reducing \(\:{V}_{th}\) .This temperature dependence is crucial for JLFET performance. 4.2 Comparison with Experimental Results: The fabrication of RSD-JLFETs is simplified due to the elimination of PN junctions, as depicted in Fig. 6 . This junctionless approach removes the need for complex ion implantation and diffusion steps typically associated with traditional MOSFET fabrication, making the process more cost-effective and scalable for future technologies. The fabrication begins with a uniformly doped silicon-on-insulator (SOI) wafer, which provides excellent electrical isolation and a well-controlled body thickness. A thin gate oxide layer is then thermally grown or deposited to form a high-quality gate dielectric, which plays a crucial role in gate control over the channel. The source and drain regions are then raised above the channel surface through selective epitaxial growth or deposition techniques, creating the distinctive raised source/drain architecture. Following this, the gate material—typically a metal or doped polysilicon—is deposited and patterned over the channel region. Advanced lithography and etching techniques are used to define the gate with nanometre-scale precision. Finally, contact holes are etched, and metal contacts are formed through deposition and planarization to complete the device structure. The electrical performance of the fabricated RSD-JLFET is analysed by evaluating the threshold voltage behavior under various conditions, as shown in Figs. 7 to 10 . These figures demonstrate the variation of threshold voltage with respect to drain voltage highlighting the impact of gate dielectric material and gate work function. Figure 7 presents the threshold voltage characteristics for a device with a gate dielectric constant of 3.9, corresponding to SiO 2 , a silicon body thickness of 10 nm, oxide thickness of 2 nm, and gate work function of 5.4 eV. In contrast, Fig. 8 explores the effect of using a high-k dielectric material, HfO 2 22, while keeping other parameters constant. The influence of gate metal work function is further examined in Figs. 9 and 10 , where work function is increased to 5.6 eV for both SiO 2 and HfO 2 dielectrics respectively. These results provide important insights into how dielectric properties and gate material selection influence threshold voltage modulation, thereby enabling optimized device performance for ultra-scaled and low-power applications. CONCLUSION In this work, a capacitance-based analytical method for determining the threshold voltage of RSD-JLFETs has been successfully developed and validated. The proposed method overcomes the limitations of conventional current-based threshold voltage extraction by focusing on the gate capacitance behavior, providing a more physically insightful and accurate estimation, particularly for ultra-scaled devices. Extensive TCAD simulations demonstrated that this approach is consistent with traditional threshold extraction techniques while offering improved simplicity and applicability, especially for devices with high-k dielectrics and short-channel effects. Further experimental validation and optimization of the method can lead to its incorporation into compact modeling frameworks, contributing to the advancement of nanoelectronic device design. Declarations Funding The authors did not receive support from any organization for the submitted work. • No funding was received to assist with the preparation of this manuscript. • No funding was received for conducting this study. • No funds, grants, or other support was received. Data Availability There are no linked data or material to this submission. Compliance with Ethical Standards Conflict of Interest • The authors have no relevant financial or non-financial interests to disclose. • The authors have no conflicts of interest to declare that are relevant to the content of this article. • All authors certify that they have no affiliations with or involvement in any organization or entity with any financial interest or non-financial interest in the subject matter or materials discussed in this manuscript. • The authors have no financial or proprietary interests in any material discussed in this article. The authors followed all accepted principles of ethical and profession- al conduct. Consent to Participate: The research involved no human participants and animals. Consent for Publication: The research involved no such materials which requires consent for publication so consent for publication is not applica- ble to this submission. Author Contribution Rikhit Swargiary performed the fabrication and drafted the manuscript. Kaushik Chandra Deva Sarma provided the research design and concept and performed the simulation. References Colinge, Jean-Pierre, et al. "Junctionless nanowire transistor (JNT): Properties and design guidelines." Solid-State Electronics 65 (2011): 33-37. Colinge JP, Lee HW, Afzalian A, Akhavan ND, Yan R, Ferain I, Razavi P, O'Neill B, Blake A, White M, Kelleher AM, McCarthy B, Murphy R (2010) Nanowire transistors without junctions. Nat Nanotechnol 5:225–229. Nowbahari, Arian, Avisek Roy, and Luca Marchetti. "Junctionless transistors: State-of-the-art." Electronics 9.7 (2020): 1174. Colinge, Jean-Pierre. "The junctionless transistor." Emerging devices for low-power and high-performance nanosystems . Jenny Stanford Publishing, 2018. 2-72. Makris, Nikolaos, et al. "CJM: a compact model for double-gate junction FETs." IEEE Journal of the Electron Devices Society 7 (2019): 1191-1199. Choi, Sung-Jin, et al. "Sensitivity of threshold voltage to nanowire width variation in junctionless transistors." IEEE Electron Device Letters 32.2 (2010): 125-127. Trevisoli, Renan Doria, et al. "Threshold voltage in junctionless nanowire transistors." Semiconductor Science and Technology 26.10 (2011): 105009. Chiang, Te-Kuang. "A quasi-two-dimensional threshold voltage model for short-channel junctionless double-gate MOSFETs." IEEE Transactions on Electron Devices 59.9 (2012): 2284-2289. Singh, Balraj, et al. "Analytical modeling of channel potential and threshold voltage of double-gate junctionless FETs with a vertical Gaussian-like doping profile." IEEE Transactions on Electron Devices 63.6 (2016): 2299-2305. D. Gola, B. Singh and P. K. Tiwari "A threshold voltage model of tri-gate junctionless field-effect transistors including substrate bias effects." IEEE transactions on Electron Devices 64.9 (2017): 3534-3540. Chen, Chun-Yu, Jyi-Tsong Lin, and Meng-Hsueh Chiang. "Threshold-voltage variability analysis and modeling for junctionless double-gate transistors." Microelectronics Reliability 74 (2017): 22-26. Kumar, A., and J. N. Roy. "A physics-based threshold voltage model for junction-less double gate FETs having vertical structural and doping asymmetry." IEEE Transactions on Electron Devices 66.8 (2019): 3640-3645. Gupta, Vidyadhar, et al. "A novel approach to model threshold voltage and subthreshold current of graded-doped Junctionless-gate-all-around (GD-JL-GAA) MOSFET’s, “Silicon (2021): 1-9. Kumar, Nitish, et al. "Modeling the threshold voltage of core-and-outer gates of ultra-thin nanotube Junctionless-double gate-all-around (NJL-DGAA) MOSFETs." Microelectronics Journal 113 (2021): 105104. Talukdar, Angshumala, and Kaushik Chandra Deva Sarma. "Threshold Voltage and Flat Band Voltage of Normally on Junction Less Field Effect Transistor." Journal of Nanoelectronics and Optoelectronics 17.1 (2022): 100-103. Raut, Pratikhya, and Deepak Kumar Panda. "Threshold voltage model development of N+ pocket vertical junctionless TFET (V-JL-TFET) as a label free biosensor." Microelectronics Journal 151 (2024): 106331. Ramaswamy, Sindhu, and Mamidala Jagadesh Kumar. "Raised source/drain dopingless junctionless accumulation mode FET: design and analysis." IEEE Transactions on Electron Devices 63.11 (2016): 4185-4190. Cheng, Ya-Chi, et al. "Characterizing the electrical properties of raised S/D junctionless thin-film transistors with a dual-gate structure." Nanoscale Research Letters 9 (2014): 1-7. K. C. D. Sarma, D. Deka and R. Swargiary, "A Simulation Study of Raised Source Drain Double Gate Junctionless Field Effect Transistor," 2023 4th International Conference on Computing and Communication Systems (I3CS), Shillong, India, 2023, pp. 1-3, doi: 10.1109/I3CS58314.2023.10127572. Additional Declarations No competing interests reported. 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Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-6593959","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":466396273,"identity":"788fb021-a5a6-49ba-b5d5-2d84f6f71d44","order_by":0,"name":"Rikhit Swargiary","email":"","orcid":"","institution":"Central Institute of Technology Kokrajhar","correspondingAuthor":false,"prefix":"","firstName":"Rikhit","middleName":"","lastName":"Swargiary","suffix":""},{"id":466396274,"identity":"dce3ab9f-8649-4ccd-a5d1-c6cb3d70b647","order_by":1,"name":"Kaushik Chandra Deva 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t\u003csub\u003eox\u003c/sub\u003e=2nm,Y\u003csub\u003eM\u003c/sub\u003e=5.4eV\u003c/p\u003e","description":"","filename":"8.png","url":"https://assets-eu.researchsquare.com/files/rs-6593959/v1/4937c683a79a49159a32da89.png"},{"id":84074415,"identity":"b0f580c4-cc92-46ae-adec-76fd6e329420","added_by":"auto","created_at":"2025-06-06 12:53:54","extension":"png","order_by":9,"title":"Figure 9","display":"","copyAsset":false,"role":"figure","size":29721,"visible":true,"origin":"","legend":"\u003cp\u003eThreshold voltage variation with drain voltage (V\u003csub\u003eds\u003c/sub\u003e) for ϵ\u003csub\u003eox\u003c/sub\u003e= 3.9(SiO\u003csub\u003e2\u003c/sub\u003e), t\u003csub\u003esi\u003c/sub\u003e=10nm, t\u003csub\u003eox\u003c/sub\u003e=2nm,Y\u003csub\u003eM\u003c/sub\u003e=5.6eV\u003c/p\u003e","description":"","filename":"9.png","url":"https://assets-eu.researchsquare.com/files/rs-6593959/v1/a1f3d33534d1714de1bef13e.png"},{"id":84074418,"identity":"b285e8f1-779b-4e58-b9c6-4c6956ea2a87","added_by":"auto","created_at":"2025-06-06 12:53:54","extension":"png","order_by":10,"title":"Figure 10","display":"","copyAsset":false,"role":"figure","size":21889,"visible":true,"origin":"","legend":"\u003cp\u003eThreshold voltage variation with drain voltage (V\u003csub\u003eds\u003c/sub\u003e) for ϵ\u003csub\u003eox\u003c/sub\u003e= 22(HfO\u003csub\u003e2\u003c/sub\u003e), t\u003csub\u003esi\u003c/sub\u003e=10nm, t\u003csub\u003eox\u003c/sub\u003e=2nm,Y\u003csub\u003eM\u003c/sub\u003e=5.6eV\u003c/p\u003e","description":"","filename":"10.png","url":"https://assets-eu.researchsquare.com/files/rs-6593959/v1/142e6711dcb2e327f6aa0acd.png"},{"id":85725417,"identity":"dceee096-c370-44ec-a38b-8a6570d9c91f","added_by":"auto","created_at":"2025-07-01 06:32:09","extension":"pdf","order_by":0,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":692795,"visible":true,"origin":"","legend":"","description":"","filename":"manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-6593959/v1/7c277985-1d4a-4808-a68d-e4097c420968.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"A Capacitance Based Threshold Voltage analysis of raised source drain Junctionless field effect transistor","fulltext":[{"header":"1. Introduction","content":"\u003cp\u003eWith the Continuing advances in semiconductor technology new transistor architecture like JLFETs has evolved. Junctionless Field-Effect Transistors JLFETs eliminate traditional pn junctions, simplifying fabrication. The foundational insights into the properties and design considerations of Junctionless nanowire transistors, highlighting their potential for scaling and reduced fabrication complexity in [\u003cspan additionalcitationids=\"CR2\" citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e\u0026ndash;\u003cspan citationid=\"CR3\" class=\"CitationRef\"\u003e3\u003c/span\u003e]. Further, [\u003cspan citationid=\"CR4\" class=\"CitationRef\"\u003e4\u003c/span\u003e] elaborated on the physics and operating principles of these devices, cementing their role in emerging low-power and high-performance nano systems. The [\u003cspan citationid=\"CR5\" class=\"CitationRef\"\u003e5\u003c/span\u003e] introduced the CJM compact model for double-gate junctionless FETs, offering an accurate analytical framework for simulating device characteristics. Threshold voltage modelling in JLFETs has been extensively studied. The impact of nanowire width variations on threshold voltage sensitivity, emphasizing precise dimension control is studied in [\u003cspan citationid=\"CR6\" class=\"CitationRef\"\u003e6\u003c/span\u003e] and [\u003cspan citationid=\"CR7\" class=\"CitationRef\"\u003e7\u003c/span\u003e] provided an analytical approach to determine the threshold voltage in nanowire transistors, highlighting the role of doping concentration and device geometry. A quasi-two-dimensional threshold voltage model for short-channel junctionless double-gate MOSFETs is developed in [\u003cspan citationid=\"CR8\" class=\"CitationRef\"\u003e8\u003c/span\u003e], improving accuracy in predicting variations due to short-channel effects. Similarly, [\u003cspan citationid=\"CR9\" class=\"CitationRef\"\u003e9\u003c/span\u003e] proposed an analytical model incorporating a vertical Gaussian-like doping profile, demonstrating its influence on device electrostatics and performance. Further refinements to threshold voltage models have been proposed for different JLFET architectures. In [\u003cspan citationid=\"CR10\" class=\"CitationRef\"\u003e10\u003c/span\u003e] extended modelling to tri-gate JLFETs by including substrate bias effects, while [\u003cspan citationid=\"CR11\" class=\"CitationRef\"\u003e11\u003c/span\u003e] focused on threshold voltage variability due to process variations and doping inhomogeneities. The [\u003cspan citationid=\"CR12\" class=\"CitationRef\"\u003e12\u003c/span\u003e] developed a physics-based model addressing structural and doping asymmetry in double-gate JLFETs, improving insights into stability and design optimization.\u003c/p\u003e \u003cp\u003eRecent advancements have expanded threshold voltage modelling to novel architectures. Graded-doped junctionless gate-all-around MOSFETs [\u003cspan citationid=\"CR13\" class=\"CitationRef\"\u003e13\u003c/span\u003e], investigated the impact of doping gradient on subthreshold characteristics and [\u003cspan citationid=\"CR14\" class=\"CitationRef\"\u003e14\u003c/span\u003e] modelled threshold voltage variations in ultra-thin nanotube junctionless double-gate-all-around MOSFETs, considering core-and-outer gate interactions. Similarly, [\u003cspan citationid=\"CR15\" class=\"CitationRef\"\u003e15\u003c/span\u003e] studied threshold voltage and flat band voltage for normally-on JLFETs, enhancing understanding of their turn-on characteristics. Raut and Panda [\u003cspan citationid=\"CR16\" class=\"CitationRef\"\u003e16\u003c/span\u003e] developed a threshold voltage model for N\u0026thinsp;+\u0026thinsp;pocket vertical junctionless TFETs, demonstrating their potential as label-free biosensors for biomedical applications and [\u003cspan citationid=\"CR17\" class=\"CitationRef\"\u003e17\u003c/span\u003e] analysed raised source/drain dopingless junctionless accumulation mode FETs, focusing on design optimizations to improve performance. The electrical properties of raised source/drain junctionless thin-film transistors with a dual-gate structure [\u003cspan citationid=\"CR18\" class=\"CitationRef\"\u003e18\u003c/span\u003e], provides valuable insights into their electronic behavior. Sarma et al. [\u003cspan citationid=\"CR19\" class=\"CitationRef\"\u003e19\u003c/span\u003e] conducted a simulation study on raised source/drain double-gate junctionless FETs, evaluating their performance under different conditions and offering computational insights for future research.\u003c/p\u003e \u003cp\u003eThis paper focuses on developing of an capacitance based analytical model for the Vth of a raised source drain JLFET, offering deeper physical insight. The device is simulated on TCAD 2D device simulator and fabricated on SOI wafer. The results from simulated device fabricated device are compared with the mathematical model developed.\u003c/p\u003e"},{"header":"2. METHODOLOGY","content":"\u003cp\u003eThe RSD- DG JLFET is a novel variant of the conventional Junctionless FET that offers improved electrostatic control and simplified fabrication. In the RSD-JLFET architecture, the source and drain regions are physically elevated above the channel, which allows for better isolation and reduced short-channel effects. This design facilitates enhanced control over the channel potential and minimizes leakage currents, making it highly suitable for ultra-scaled and low-power applications. In this work, a capacitance-based analytical approach is adopted to determine the Vth of the RSD-DG JLFET. Threshold voltage is defined as the gate voltage at which the depletion region spans the entire body thickness, beyond which the device transits to the conducting state. Rather than relying on the conventional drain current method, the proposed method focuses on the gate-to-channel capacitance response. The capacitance variation is monitored as a function of gate voltage, and the inflection point where the depletion width equals the silicon body thickness is identified as the threshold voltage. The analytical model incorporates various device parameters including gate work function, gate oxide thickness, silicon film thickness, dielectric constant, drain voltage and temperature. These parameters influence the electrostatics of the device and thus impact the capacitance profile. To validate the analytical results, simulations and experimental were performed. The structures employed different combinations of dielectric constants and gate work functions to assess the accuracy and applicability of the proposed model under varying conditions.\u003c/p\u003e"},{"header":"3. DETERMINATION OF THRESHOLD VOLTAGE","content":"\u003cp\u003eIn a double gate junctionless FET the threshold voltage is determined by the balanced of capacitance in the device. At the threshold voltage \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{V}_{th}\\:\\)\u003c/span\u003e\u003c/span\u003ethe total capacitance of the system must be equal to the equivalent capacitance derived from electrostatics.\u003c/p\u003e \u003cp\u003eAt \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{V}_{th}\\:\\)\u003c/span\u003e\u003c/span\u003e= \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{V}_{g}\\)\u003c/span\u003e\u003c/span\u003e the capacitance structure consists of \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{C}_{1}\\:\\)\u003c/span\u003e\u003c/span\u003eand \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{C}_{2}\\)\u003c/span\u003e\u003c/span\u003e. Since the system is symmetric:\u003cdiv id=\"Equa\" class=\"Equation\"\u003e\u003cdiv format=\"TEX\" class=\"mathdisplay\" id=\"FileID_Equa\" name=\"EquationSource\"\u003e\n$$\\:{C}_{1}\\:=\\:{C}_{2}={C}_{ox}$$\u003c/div\u003e\u003c/div\u003e\u003c/p\u003e \u003cp\u003eThe gate capacitance \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{C}_{ox}\\:\\)\u003c/span\u003e\u003c/span\u003earises due to the oxide layer separating the gate from the channel can be expressed as\u003cdiv id=\"Equ1\" class=\"Equation\"\u003e\u003cdiv format=\"TEX\" class=\"mathdisplay\" id=\"FileID_Equ1\" name=\"EquationSource\"\u003e\n$$\\:{C}_{ox}=\\frac{{Є}_{ox}}{{T}_{ox}}$$\u003c/div\u003e\u003cdiv class=\"EquationNumber\"\u003e1\u003c/div\u003e\u003c/div\u003e\u003c/p\u003e \u003cp\u003ewhere \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{T}_{ox}\\)\u003c/span\u003e\u003c/span\u003e​ is the oxide thickness and \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{Є}_{ox}\\)\u003c/span\u003e\u003c/span\u003e is the permittivity of the oxide material.\u003c/p\u003e \u003cp\u003eThe semiconductor region between the gates introduces an additional depletion capacitance which is given by\u003cdiv id=\"Equ2\" class=\"Equation\"\u003e\u003cdiv format=\"TEX\" class=\"mathdisplay\" id=\"FileID_Equ2\" name=\"EquationSource\"\u003e\n$$\\:{C}_{Semi}=\\frac{{2Є}_{si}}{{T}_{si}}$$\u003c/div\u003e\u003cdiv class=\"EquationNumber\"\u003e2\u003c/div\u003e\u003c/div\u003e\u003c/p\u003e \u003cp\u003ewhere \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{T}_{si}\\)\u003c/span\u003e\u003c/span\u003e is the thickness of the silicon channel and \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{Є}_{si}\\)\u003c/span\u003e\u003c/span\u003e is the permittivity of silicon.\u003c/p\u003e \u003cp\u003eThe lateral capacitance \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{C}_{1}\\:\\)\u003c/span\u003e\u003c/span\u003eand \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{C}_{2}\\)\u003c/span\u003e\u003c/span\u003e are in series with the semiconductor capacitance:\u003cdiv id=\"Equb\" class=\"Equation\"\u003e\u003cdiv format=\"TEX\" class=\"mathdisplay\" id=\"FileID_Equb\" name=\"EquationSource\"\u003e\n$$\\:{C}_{total}={\\left(\\frac{2}{{C}_{ox}}+\\frac{1}{{C}_{semi}}\\right)}^{-1}$$\u003c/div\u003e\u003c/div\u003e\u003cdiv id=\"Equ3\" class=\"Equation\"\u003e\u003cdiv format=\"TEX\" class=\"mathdisplay\" id=\"FileID_Equ3\" name=\"EquationSource\"\u003e\n$$\\:{C}_{total}={\\left(\\frac{2{T}_{ox}}{{Є}_{ox}}+\\frac{{t}_{si}}{2{Є}_{si}}\\right)}^{-1}$$\u003c/div\u003e\u003cdiv class=\"EquationNumber\"\u003e3\u003c/div\u003e\u003c/div\u003e\u003c/p\u003e \u003cp\u003eAt the threshold voltage, the equivalent capacitance is derived from the depletion charge in the semiconductor:\u003cdiv id=\"Equ4\" class=\"Equation\"\u003e\u003cdiv format=\"TEX\" class=\"mathdisplay\" id=\"FileID_Equ4\" name=\"EquationSource\"\u003e\n$$\\:{C}_{eq}=\\frac{dQ}{dV}$$\u003c/div\u003e\u003cdiv class=\"EquationNumber\"\u003e4\u003c/div\u003e\u003c/div\u003e\u003c/p\u003e \u003cp\u003eThe depletion charge per unit area is\u003cdiv id=\"Equ5\" class=\"Equation\"\u003e\u003cdiv format=\"TEX\" class=\"mathdisplay\" id=\"FileID_Equ5\" name=\"EquationSource\"\u003e\n$$\\:{Q}_{eq}=\\text{q}{N}_{d}{t}_{si}$$\u003c/div\u003e\u003cdiv class=\"EquationNumber\"\u003e5\u003c/div\u003e\u003c/div\u003e\u003c/p\u003e \u003cp\u003eDifferentiating with respect to gate voltage \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{V}_{g}\\)\u003c/span\u003e\u003c/span\u003e:\u003cdiv id=\"Equ6\" class=\"Equation\"\u003e\u003cdiv format=\"TEX\" class=\"mathdisplay\" id=\"FileID_Equ6\" name=\"EquationSource\"\u003e\n$$\\:{C}_{eq}=\\frac{\\text{q}{N}_{d}{t}_{si}}{{V}_{th}}$$\u003c/div\u003e\u003cdiv class=\"EquationNumber\"\u003e6\u003c/div\u003e\u003c/div\u003e\u003c/p\u003e \u003cp\u003eBy equating the total capacitance to the equivalent capacitance:\u003cdiv id=\"Equc\" class=\"Equation\"\u003e\u003cdiv format=\"TEX\" class=\"mathdisplay\" id=\"FileID_Equc\" name=\"EquationSource\"\u003e\n$$\\:{C}_{eq}=\\:{C}_{total}$$\u003c/div\u003e\u003c/div\u003e\u003cdiv id=\"Equd\" class=\"Equation\"\u003e\u003cdiv format=\"TEX\" class=\"mathdisplay\" id=\"FileID_Equd\" name=\"EquationSource\"\u003e\n$$\\:{\\left(\\frac{2{T}_{ox}}{{Є}_{ox}}+\\frac{{t}_{si}}{2{Є}_{si}}\\right)}^{-1}=\\:\\frac{\\text{q}{N}_{d}{t}_{si}}{{V}_{th}}$$\u003c/div\u003e\u003c/div\u003e\u003cdiv id=\"Equ7\" class=\"Equation\"\u003e\u003cdiv format=\"TEX\" class=\"mathdisplay\" id=\"FileID_Equ7\" name=\"EquationSource\"\u003e\n$$\\:{V}_{th}=\\:\\text{q}{N}_{d}{t}_{si}\\left(\\frac{2{T}_{ox}}{{Є}_{ox}}+\\frac{{t}_{si}}{2{Є}_{si}}\\right)$$\u003c/div\u003e\u003cdiv class=\"EquationNumber\"\u003e7\u003c/div\u003e\u003c/div\u003e\u003c/p\u003e \u003cp\u003eThe threshold voltage in Eq.\u0026nbsp;(\u003cspan refid=\"Equ7\" class=\"InternalRef\"\u003e7\u003c/span\u003e) is applicable for raised source drain structure also because in calculating threshold voltage the channel depletion layer is considered and source drain layer is not considered because the depletion layer at the center will start removing without the effect of source drain region.\u003c/p\u003e"},{"header":"4. RESULTS AND DISCUSSION","content":"\u003cp\u003eThis paper introduced a capacitance based model for threshold voltage of a Junctionless transistor which has been developed. The developed model RSD-DG JLFET has been compared with simulated results from Cogenda Visual TCAD 2D device simulator and experimental results for the purpose of validating the model.\u003c/p\u003e \u003cdiv id=\"Sec5\" class=\"Section2\"\u003e \u003ch2\u003e4.1 Comparison with simulation results\u003c/h2\u003e \u003cp\u003eThe threshold voltage variation with gate oxide thickness, dielectric constant of gate dielectric, channel length and temperature obtained from the mathematical model has been compared with that obtained from TCAD numerical simulation. The structural overview of the RSD-DG-JLFET is illustrated in Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003e, providing a detailed representation of its design and key features.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eThe simulation results obtained from the developed model have been systematically compared with the mathematical model. The proposed model demonstrates a high degree of accuracy, with a deviation of less than 5% when compared to numerical simulations. Furthermore, the obtained results and their comparisons with TCAD simulations are graphically represented in the subsequent figures, providing a clear visualization of the model\u0026rsquo;s performance. These comparative analyses affirm the validity and robustness of the developed analytical approach, making it a valuable tool for future research and development in Junctionless Transistor technology.\u003c/p\u003e \u003cp\u003eIn a raised source drain JLFET, the threshold voltage \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{V}_{th}\\)\u003c/span\u003e\u003c/span\u003e is significantly influenced by the work function of the gate material. The Fig.\u0026nbsp;\u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e2\u003c/span\u003e. shows the variation of threshold voltage with gate oxide thickness. From the figure it is clear that gate loses control over the channel region for thicker gate oxide. To achieve a suitable positive threshold voltage value at a short channel the gate oxide and channel region should be very thin. The model is in close agreement with TCAD simulation results. The Fig.\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003e. shows the variation of threshold voltage with Dielectric constant of Gate Dielectric. It has been observed that the value of the dielectric constant of gate dielectric increase with the threshold voltage rises from 0.4 V to 0.8 V. This occurs because a higher dielectric constant enhances gate capacitance, leading to stronger electrostatic control over the channel. Using high-k dielectrics in JLFETs helps improve device performance by reducing leakage current and improving gate control making them suitable for low-power applications. However, a very high dielectric constant can lead to undesirable effects such as threshold voltage instability and increased interface trap densities.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eFigure. 4 illustrates the effect of channel length on the \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{V}_{th}\\)\u003c/span\u003e\u003c/span\u003e in a raised source drain JLFET. As the channel length increases from 20 nm to 30 nm, the threshold voltage rises from 0.4 V to 0.48 V. This occurs because longer channels reduce short-channel effects, leading to better electrostatic control by the gate. A shorter channel allows more influence from the drain, which can lower \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{V}_{th}\\)\u003c/span\u003e\u003c/span\u003e. The Figure. 5 shows the effect of temperature on the threshold voltage \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{V}_{th}\\)\u003c/span\u003e\u003c/span\u003e in a proposed structure. As the temperature increases from 350 K to 650 K, the threshold voltage decreases from 0.4 V to 0.1 V. This trend is due to the intrinsic properties of semiconductors, where higher temperatures lead to increased carrier concentration and reduced bandgap energy. As a result, more free carriers are available in the channel, making it easier for the device to turn on at lower gate voltages, effectively reducing \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{V}_{th}\\)\u003c/span\u003e\u003c/span\u003e.This temperature dependence is crucial for JLFET performance.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003c/div\u003e \u003cdiv id=\"Sec6\" class=\"Section2\"\u003e \u003ch2\u003e4.2 Comparison with Experimental Results:\u003c/h2\u003e \u003cp\u003eThe fabrication of RSD-JLFETs is simplified due to the elimination of PN junctions, as depicted in Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e. This junctionless approach removes the need for complex ion implantation and diffusion steps typically associated with traditional MOSFET fabrication, making the process more cost-effective and scalable for future technologies. The fabrication begins with a uniformly doped silicon-on-insulator (SOI) wafer, which provides excellent electrical isolation and a well-controlled body thickness. A thin gate oxide layer is then thermally grown or deposited to form a high-quality gate dielectric, which plays a crucial role in gate control over the channel. The source and drain regions are then raised above the channel surface through selective epitaxial growth or deposition techniques, creating the distinctive raised source/drain architecture. Following this, the gate material\u0026mdash;typically a metal or doped polysilicon\u0026mdash;is deposited and patterned over the channel region. Advanced lithography and etching techniques are used to define the gate with nanometre-scale precision. Finally, contact holes are etched, and metal contacts are formed through deposition and planarization to complete the device structure.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eThe electrical performance of the fabricated RSD-JLFET is analysed by evaluating the threshold voltage behavior under various conditions, as shown in Figs.\u0026nbsp;\u003cspan refid=\"Fig7\" class=\"InternalRef\"\u003e7\u003c/span\u003e to \u003cspan refid=\"Fig10\" class=\"InternalRef\"\u003e10\u003c/span\u003e. These figures demonstrate the variation of threshold voltage with respect to drain voltage highlighting the impact of gate dielectric material and gate work function. Figure\u0026nbsp;\u003cspan refid=\"Fig7\" class=\"InternalRef\"\u003e7\u003c/span\u003e presents the threshold voltage characteristics for a device with a gate dielectric constant of 3.9, corresponding to SiO\u003csub\u003e2\u003c/sub\u003e, a silicon body thickness of 10 nm, oxide thickness of 2 nm, and gate work function of 5.4 eV. In contrast, Fig.\u0026nbsp;\u003cspan refid=\"Fig8\" class=\"InternalRef\"\u003e8\u003c/span\u003e explores the effect of using a high-k dielectric material, HfO\u003csub\u003e2\u003c/sub\u003e 22, while keeping other parameters constant. The influence of gate metal work function is further examined in Figs.\u0026nbsp;\u003cspan refid=\"Fig9\" class=\"InternalRef\"\u003e9\u003c/span\u003e and \u003cspan refid=\"Fig10\" class=\"InternalRef\"\u003e10\u003c/span\u003e, where work function is increased to 5.6 eV for both SiO\u003csub\u003e2\u003c/sub\u003e and HfO\u003csub\u003e2\u003c/sub\u003e dielectrics respectively. These results provide important insights into how dielectric properties and gate material selection influence threshold voltage modulation, thereby enabling optimized device performance for ultra-scaled and low-power applications.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003c/div\u003e"},{"header":"CONCLUSION","content":"\u003cp\u003eIn this work, a capacitance-based analytical method for determining the threshold voltage of RSD-JLFETs has been successfully developed and validated. The proposed method overcomes the limitations of conventional current-based threshold voltage extraction by focusing on the gate capacitance behavior, providing a more physically insightful and accurate estimation, particularly for ultra-scaled devices. Extensive TCAD simulations demonstrated that this approach is consistent with traditional threshold extraction techniques while offering improved simplicity and applicability, especially for devices with high-k dielectrics and short-channel effects. Further experimental validation and optimization of the method can lead to its incorporation into compact modeling frameworks, contributing to the advancement of nanoelectronic device design.\u003c/p\u003e"},{"header":"Declarations","content":"\u003ch2\u003eFunding\u003c/h2\u003e \u003cp\u003eThe authors did not receive support from any organization for the submitted work.\u003c/p\u003e \u003cp\u003e\u0026bull; No funding was received to assist with the preparation of this manuscript.\u003c/p\u003e \u003cp\u003e\u0026bull; No funding was received for conducting this study.\u003c/p\u003e \u003cp\u003e\u0026bull; No funds, grants, or other support was received.\u003c/p\u003e \u003cp\u003eData Availability There are no linked data or material to this submission.\u003c/p\u003e \u003cp\u003eCompliance with Ethical Standards\u003c/p\u003e \u003cp\u003eConflict of Interest\u003c/p\u003e \u003cp\u003e\u0026bull; The authors have no relevant financial or non-financial interests to disclose.\u003c/p\u003e \u003cp\u003e\u0026bull; The authors have no conflicts of interest to declare that are relevant to the content of this article.\u003c/p\u003e \u003cp\u003e\u0026bull; All authors certify that they have no affiliations with or involvement in any organization or entity with any financial interest or non-financial interest in the subject matter or materials discussed in this manuscript.\u003c/p\u003e \u003cp\u003e\u0026bull; The authors have no financial or proprietary interests in any material discussed in this article.\u003c/p\u003e \u003cp\u003eThe authors followed all accepted principles of ethical and profession- al conduct.\u003c/p\u003e \u003cp\u003eConsent to Participate: The research involved no human participants and animals.\u003c/p\u003e \u003cp\u003eConsent for Publication: The research involved no such materials which requires consent for publication so consent for publication is not applica- ble to this submission.\u003c/p\u003e\u003ch2\u003eAuthor Contribution\u003c/h2\u003e\u003cp\u003eRikhit Swargiary performed the fabrication and drafted the manuscript. Kaushik Chandra Deva Sarma provided the research design and concept and performed the simulation.\u003c/p\u003e"},{"header":"References","content":"\u003col\u003e\n\u003cli\u003eColinge, Jean-Pierre, et al. \u0026quot;Junctionless nanowire transistor (JNT): Properties and design guidelines.\u0026quot; \u003cem\u003eSolid-State Electronics\u003c/em\u003e 65 (2011): 33-37.\u003c/li\u003e\n\u003cli\u003eColinge JP, Lee HW, Afzalian A, Akhavan ND, Yan R, Ferain I, Razavi P, O\u0026apos;Neill B, Blake A, White M, Kelleher AM, McCarthy B, Murphy R (2010) Nanowire transistors without junctions. Nat Nanotechnol 5:225\u0026ndash;229.\u003c/li\u003e\n\u003cli\u003eNowbahari, Arian, Avisek Roy, and Luca Marchetti. \u0026quot;Junctionless transistors: State-of-the-art.\u0026quot; \u003cem\u003eElectronics\u003c/em\u003e 9.7 (2020): 1174.\u003c/li\u003e\n\u003cli\u003eColinge, Jean-Pierre. \u0026quot;The junctionless transistor.\u0026quot; \u003cem\u003eEmerging devices for low-power and high-performance nanosystems\u003c/em\u003e. Jenny Stanford Publishing, 2018. 2-72.\u003c/li\u003e\n\u003cli\u003eMakris, Nikolaos, et al. \u0026quot;CJM: a compact model for double-gate junction FETs.\u0026quot; \u003cem\u003eIEEE Journal of the Electron Devices Society\u003c/em\u003e 7 (2019): 1191-1199.\u003c/li\u003e\n\u003cli\u003eChoi, Sung-Jin, et al. \u0026quot;Sensitivity of threshold voltage to nanowire width variation in junctionless transistors.\u0026quot; \u003cem\u003eIEEE Electron Device Letters\u003c/em\u003e 32.2 (2010): 125-127.\u003c/li\u003e\n\u003cli\u003eTrevisoli, Renan Doria, et al. \u0026quot;Threshold voltage in junctionless nanowire transistors.\u0026quot; \u003cem\u003eSemiconductor Science and Technology\u003c/em\u003e 26.10 (2011): 105009.\u003c/li\u003e\n\u003cli\u003eChiang, Te-Kuang. \u0026quot;A quasi-two-dimensional threshold voltage model for short-channel junctionless double-gate MOSFETs.\u0026quot; \u003cem\u003eIEEE Transactions on Electron Devices\u003c/em\u003e 59.9 (2012): 2284-2289.\u003c/li\u003e\n\u003cli\u003eSingh, Balraj, et al. \u0026quot;Analytical modeling of channel potential and threshold voltage of double-gate junctionless FETs with a vertical Gaussian-like doping profile.\u0026quot; \u003cem\u003eIEEE Transactions on Electron Devices\u003c/em\u003e 63.6 (2016): 2299-2305.\u003c/li\u003e\n\u003cli\u003eD. Gola, B. Singh and P. K. Tiwari \u0026quot;A threshold voltage model of tri-gate junctionless field-effect transistors including substrate bias effects.\u0026quot; \u003cem\u003eIEEE transactions on Electron Devices\u003c/em\u003e 64.9 (2017): 3534-3540.\u003c/li\u003e\n\u003cli\u003eChen, Chun-Yu, Jyi-Tsong Lin, and Meng-Hsueh Chiang. \u0026quot;Threshold-voltage variability analysis and modeling for junctionless double-gate transistors.\u0026quot; \u003cem\u003eMicroelectronics Reliability\u003c/em\u003e 74 (2017): 22-26.\u003c/li\u003e\n\u003cli\u003eKumar, A., and J. N. Roy. \u0026quot;A physics-based threshold voltage model for junction-less double gate FETs having vertical structural and doping asymmetry.\u0026quot; \u003cem\u003eIEEE Transactions on Electron Devices\u003c/em\u003e 66.8 (2019): 3640-3645.\u003c/li\u003e\n\u003cli\u003eGupta, Vidyadhar, et al. \u0026quot;A novel approach to model threshold voltage and subthreshold current of graded-doped Junctionless-gate-all-around (GD-JL-GAA) MOSFET\u0026rsquo;s, \u0026ldquo;Silicon (2021): 1-9.\u003c/li\u003e\n\u003cli\u003eKumar, Nitish, et al. \u0026quot;Modeling the threshold voltage of core-and-outer gates of ultra-thin nanotube Junctionless-double gate-all-around (NJL-DGAA) MOSFETs.\u0026quot; \u003cem\u003eMicroelectronics Journal\u003c/em\u003e 113 (2021): 105104.\u003c/li\u003e\n\u003cli\u003eTalukdar, Angshumala, and Kaushik Chandra Deva Sarma. \u0026quot;Threshold Voltage and Flat Band Voltage of Normally on Junction Less Field Effect Transistor.\u0026quot; \u003cem\u003eJournal of Nanoelectronics and Optoelectronics\u003c/em\u003e 17.1 (2022): 100-103.\u003c/li\u003e\n\u003cli\u003eRaut, Pratikhya, and Deepak Kumar Panda. \u0026quot;Threshold voltage model development of N+ pocket vertical junctionless TFET (V-JL-TFET) as a label free biosensor.\u0026quot; \u003cem\u003eMicroelectronics Journal\u003c/em\u003e 151 (2024): 106331.\u003c/li\u003e\n\u003cli\u003eRamaswamy, Sindhu, and Mamidala Jagadesh Kumar. \u0026quot;Raised source/drain dopingless junctionless accumulation mode FET: design and analysis.\u0026quot; \u003cem\u003eIEEE Transactions on Electron Devices\u003c/em\u003e 63.11 (2016): 4185-4190.\u003c/li\u003e\n\u003cli\u003eCheng, Ya-Chi, et al. \u0026quot;Characterizing the electrical properties of raised S/D junctionless thin-film transistors with a dual-gate structure.\u0026quot; \u003cem\u003eNanoscale Research Letters\u003c/em\u003e 9 (2014): 1-7.\u003c/li\u003e\n\u003cli\u003eK. C. D. Sarma, D. Deka and R. Swargiary, \u0026quot;A Simulation Study of Raised Source Drain Double Gate Junctionless Field Effect Transistor,\u0026quot; 2023 4th International Conference on Computing and Communication Systems (I3CS), Shillong, India, 2023, pp. 1-3, doi: 10.1109/I3CS58314.2023.10127572.\u003c/li\u003e\n\u003c/ol\u003e"}],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":true,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":true,"highlight":"","institution":"","isAcceptedByJournal":false,"isAuthorSuppliedPdf":false,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":false,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"JLFET, Raised Source Drain, Threshold Voltage, TCAD","lastPublishedDoi":"10.21203/rs.3.rs-6593959/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-6593959/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eThe evolution of transistor technology has led to the emergence of Junctionless Field-Effect Transistors (JLFETs) as promising alternatives to conventional MOSFETs, offering simplified fabrication and superior electrostatic control. Among them, Raised Source Drain Double gate JLFETs (RSD-JLFETs) exhibit enhanced performance characteristics, making them suitable for nanoscale applications. This paper presents a capacitance-based analytical method for accurately determining the threshold voltage of RSD-JLFETs. The model defines threshold voltage as the gate voltage at which the depletion width equals the silicon body thickness, marking the onset of conduction. Unlike traditional current-based methods, this approach utilizes the gate-to-channel capacitance transition to extract threshold voltage (Vth), incorporating critical design parameters such as gate work function, oxide thickness, channel length, dielectric constant, drain voltage, and temperature. The model is validated through extensive TCAD simulations using various high-k dielectrics and gate materials, demonstrating strong agreement with conventional techniques. The validation of the model is also done by comparison with experimental results by fabricating the device on SOI wafer. This method offers a physically insightful, computationally efficient tool for Vth estimation, aiding the design and optimization of next-generation low-power JLFET devices.\u003c/p\u003e","manuscriptTitle":"A Capacitance Based Threshold Voltage analysis of raised source drain Junctionless field effect transistor","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2025-06-06 12:53:50","doi":"10.21203/rs.3.rs-6593959/v1","editorialEvents":[{"type":"communityComments","content":0}],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true}}],"origin":"","ownerIdentity":"0812475f-cd69-466f-bdf6-058a0158759d","owner":[],"postedDate":"June 6th, 2025","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"posted","subjectAreas":[],"tags":[],"updatedAt":"2025-07-01T06:23:58+00:00","versionOfRecord":[],"versionCreatedAt":"2025-06-06 12:53:50","video":"","vorDoi":"","vorDoiUrl":"","workflowStages":[]},"version":"v1","identity":"rs-6593959","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-6593959","identity":"rs-6593959","version":["v1"]},"buildId":"8U1c8b4HqxoKbykW_rLl7","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}