A Dynamic Overlap-contention-free Double-edge-triggered D-type Flip-flop with High Energy Efficiency

A Dynamic Overlap-contention-free Double-edge-triggered D-type Flip-flop with High Energy Efficiency | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article A Dynamic Overlap-contention-free Double-edge-triggered D-type Flip-flop with High Energy Efficiency Shahriar Jamasb, Mohammad Bagher Khodabakhshi, Mohammad Reza Rezaeian This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-6443253/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract Considering the general trade-off between high-speed operation and low power consumption in digital integrated circuits, simultaneous reduction of the propagation delay and power dissipation in bistable memory elements represents a challenging task. A compact, dynamic, D-type double-edge-triggered flip-flop (DETFF) designed in a nanometer CMOS technology is presented. The proposed topology employs a 2:1 multiplexer to combine a pair of dynamic single-edge-triggered flip-flops, one of which is triggered on the rising edge and the other on the falling edge of a true single-phase clock (TSPC), thereby providing immunity to clock overlap contention hazards. The dynamic implementation accounts for the high-speed performance, and the use of only eight clocked transistors accounts for the low power operation of the proposed DETFF. Notably, operating with a 1-volt power supply at a clock frequency of 10 GHz, given a switching activity of 10%, the proposed DETFF exhibits an average Clock-to-Q delay of 59 psec and consumes 211 µW in a 90nm CMOS technology. A methodology based on CMOS lateral scaling rules is advanced to enable a fair comparison of the performance of the proposed topology with those of other high-performance designs. The proposed TSPC DETFF demonstrates the potential to outperform static designs in terms of speed and energy efficiency. Specifically, the proposed dynamic TSPC DETFF exhibits a lower clock-to-Q delay, and a lower power delay product than all the static low-power designs considered for comparison. Double-edge-triggered flip-flop dynamic flip-flop high-speed low-power nanometer CMOS static flip-flop Full Text Additional Declarations No competing interests reported. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. 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Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-6443253","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":455833892,"identity":"bdf3419b-adf4-4994-b915-b7280e49a685","order_by":0,"name":"Shahriar Jamasb","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAAAu0lEQVRIiWNgGAWjYBACxgYwYZMA5UsQrSUtgYGNWC1QfYdhWogAzO2nEz/+3HE+z+B+A+OHHwwW+YQt6MndLM175naxwTEGZskeBgnLBsJuyt0gzdh2O3HDMQYGaaBfDAjb0v9288+fbedAWph/E6dlRu42Cd62AyAtbETaMuPtNmveM8mJM48ltln2GBChxbA/d/PNnzvsEvsOHz5840dFHRFaGhAWApmENTAwyBOhZhSMglEwCkY6AADkuzyWK0cmxgAAAABJRU5ErkJggg==","orcid":"","institution":"Hamedan University of Technology Hamedan","correspondingAuthor":true,"prefix":"","firstName":"Shahriar","middleName":"","lastName":"Jamasb","suffix":""},{"id":455833893,"identity":"d6615d48-9ac6-4b0b-8507-a17a514d79ab","order_by":1,"name":"Mohammad Bagher Khodabakhshi","email":"","orcid":"","institution":"Hamedan University of Technology Hamedan","correspondingAuthor":false,"prefix":"","firstName":"Mohammad","middleName":"Bagher","lastName":"Khodabakhshi","suffix":""},{"id":455833894,"identity":"6480a609-e992-4bf4-9c78-4486ab0145f4","order_by":2,"name":"Mohammad Reza Rezaeian","email":"","orcid":"","institution":"Hamedan University of Technology Hamedan","correspondingAuthor":false,"prefix":"","firstName":"Mohammad","middleName":"Reza","lastName":"Rezaeian","suffix":""}],"badges":[],"createdAt":"2025-04-14 07:08:23","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-6443253/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-6443253/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":84466563,"identity":"df173689-52a6-4ffc-b158-309fbbcb5baf","added_by":"auto","created_at":"2025-06-12 09:47:14","extension":"pdf","order_by":1,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":547397,"visible":true,"origin":"","legend":"","description":"","filename":"DETFFJamasbDiscover.pdf","url":"https://assets-eu.researchsquare.com/files/rs-6443253/v1_covered_79ae0855-f04d-4036-bbb7-a0ee4b002121.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"A Dynamic Overlap-contention-free Double-edge-triggered D-type Flip-flop with High Energy Efficiency","fulltext":[],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":false,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":true,"highlight":"","institution":"","isAcceptedByJournal":false,"isAuthorSuppliedPdf":true,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":true,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"Double-edge-triggered flip-flop, dynamic flip-flop, high-speed, low-power, nanometer CMOS, static flip-flop","lastPublishedDoi":"10.21203/rs.3.rs-6443253/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-6443253/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eConsidering the general trade-off between high-speed operation and low power consumption in digital integrated circuits, simultaneous reduction of the propagation delay and power dissipation in bistable memory elements represents a challenging task. A compact, dynamic, D-type double-edge-triggered flip-flop (DETFF) designed in a nanometer CMOS technology is presented. The proposed topology employs a 2:1 multiplexer to combine a pair of dynamic single-edge-triggered flip-flops, one of which is triggered on the rising edge and the other on the falling edge of a true single-phase clock (TSPC), thereby providing immunity to clock overlap contention hazards. The dynamic implementation accounts for the high-speed performance, and the use of only eight clocked transistors accounts for the low power operation of the proposed DETFF. Notably, operating with a 1-volt power supply at a clock frequency of 10 GHz, given a switching activity of 10%, the proposed DETFF exhibits an average Clock-to-Q delay of 59 psec and consumes 211 \u0026micro;W in a 90nm CMOS technology. A methodology based on CMOS lateral scaling rules is advanced to enable a fair comparison of the performance of the proposed topology with those of other high-performance designs. The proposed TSPC DETFF demonstrates the potential to outperform static designs in terms of speed and energy efficiency. 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