Modeling and Analysis of Phase-locked loops: a non reductionist approach

Phase-locked loop (PLL), conceived in 1932 by H. Bellescize, has been the basic electronic component in the development of communication technology from the early analog radio receptors to modern digital civil and military facilities. Traditionally, the analysis is conducted by modeling the dynamical behavior of phase and frequency errors, hence following a phase reduction approach. One of the main goals of the present work is to describe and investigate the dynamics of a PLL node by representing it in full state-space, here called non reductionist model, without the usual design simplifications i.e., considering different input and output frequencies and not neglecting the higher frequencies components generated in the phase detection process. On the one hand, this approach complicates the use of analytical tools but on the other hand it permits an efficient numerical approach that can be used for precise definition of regions in parameters space that show the boundaries between synchronization and non synchronization regimes, even when noise is considered. Results show that the PLL node can be simulated in a more realistic way using the state-space model and that a number of design-relevant aspects can now be investigated numerically.