Design and Analysis of Imaging Chip Using High-Speed AXI-Interface for MPSOC Applications on FPGA Platform

The recent innovations in real-time video and image enhancements are allowing much advancement in a wide range of diverse applications. These innovations and advancements provide a new hardware architecture which aims to improve the image visualization, processing speed, and complexity reduction in hardware. The imaging chip concept is introduced in this article to support the Multiprocessing system on chip (MPSoC) applications in real-time scenarios on a single chip. The imaging chip model is designed using high-speed interface protocol, which includes different image enhancement algorithms acts as a master model, Advanced Extensible Interface (AXI)-4 as an interface model, and dual-port memory as a slave model. The image enhancement algorithm includes mainly, Brightness control, contrast stretching, Adaptive median filtering (AMF), Edge-detection techniques, image Thresholding, and Image Histogram method. The AXI-4 provides a high-speed interface for communicating master and slave modules. The proposed model work based on the modes of the operation to process the enhanced image output in MPSoC. The design supports multiple masters and multiple slave modules with reconfigurable nature. The imaging chip is a module on the Xilinx ISE environment and implemented on Artix-7 FPGA, along with the performance metrics like chip Area, time, power, and memory utilization are analyzed with improvements. The model offers low latency and high throughput architecture for real-time Multimedia applications.