A Dual-Mode Adaptive Bandwidth PLL for Improved Lock Performance

This paper proposed an adaptive bandwidth PLL that integrates Integer-N and Fractional-N switching for energy-efficient RF synthesis in IoT and mobile applications. The architecture exploits wide-bandwidth Integer-N mode for rapid lock acquisition, then seamlessly transitions to narrow-bandwidth Fractional-N mode for high-resolution synthesis and noise optimization. The architecture features a bandwidth-reconfigurable loop filter with intelligent switching control that monitors phase error dynamics. A novel adaptive digital noise filter mitigates ΔΣ quantization noise, replacing conventional synchronous delay lines. The multi loop structure incorporates a high resolution digital phase detector to enhance frequency accuracy and minimize jitter across both operating modes. With 180 nm CMOS technology, the PLL consumes 13.2 mW while achieving −119 dBc/Hz in-band phase noise, 1 psrms integrated jitter. Lock time improvements of 70% are demonstrated compared to single-mode implementations, making it suitable for high-precision, low-power wireless communication systems requiring agile frequency synthesis.