Design of Memristor Based Modified Synapse Circuit for Low-Power Neuromorphic Computing

Design of Memristor Based Modified Synapse Circuit for Low-Power Neuromorphic Computing | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Design of Memristor Based Modified Synapse Circuit for Low-Power Neuromorphic Computing Tarif Ahammad Fuad Hazari, A.B.M. Noushad Bhuiyan, Md. Israil Hossain This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-4607889/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract It is high time that brain-inspired or neuromorphic computing must have enough concentration to grow and overcome the computational barrier, which will mimic the biological neuron cell, and its computational abilities will be applied from the neuroscience point of view. We have shown some current candidates from the material to device level for neuromorphic computing and how our proposed memristor-based bridge synapse circuit can emulate the spiking properties of neurons in biological brains with plasticity phenomena such as LTP, LTD and STDP or SRDP (spike rate-dependent plasticity), considering that low power consumption is the primary key to this kind of computing. Electrical Engineering Electronic Materials and Devices Computer Architecture and Engineering LTP STDP SRDP Memristor Synapse Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 1. Introduction Modern computers now must perform complex computations such as machine learning (ML) and deep learning (DL) algorithms, even when this large number of datasets are involved in computing; however, processors are becoming slower not only because of the computational complexity itself but also because of the movement of data shuttling from memory to the CPU or vice-versa [1]. The long-term approach for reducing the power consumption of processors requires the development of a non von Neumann architecture that computes within the memory, eliminating the need for data communication. Thus, a more ‘brain-like’ architecture called neuromorphic computing was proposed by Carver Mead from Caltech after the 1990s to efficiently overcome the limitations of von Neumann architecture [2]. 1.1 Memristor Memristor was first postulated by Leon Chua in In 1971, the fourth fundamental passive electrical circuit element was first designed by HP laboratories in 2008 with a doped and undoped region with a TiO2-based model, as demonstrated in Fig. 1 above [3–4]. HP fabricated memristors are composed of two thin films of titanium dioxide (TiO 2 ) sandwiched between two platinum (Pt) electrodes, named the top electrode (TE) and bottom electrode (BE). In our SPICE symbol, we have employed TE and BE as A and B respectively. The HP model of a memristor with the Biolek window function was reproduced only for transient analysis. Nonetheless, researchers are interested in applying memristors in the field of neuromorphic computing because memristors show some promising features that are rudimentary in emulating brain-like computing. These include but are not limited to Memory effect Nanoscale size Non-Volatility Passivity 1.2 Modeling of memristor parameters We have adapted the memristor model introduced by Biolek et al. developed a memristor model based on the Biolek window function [5]. The SPICE code for defining the subcircuit model is fine-tuned so that the memristor device characteristics are the intrinsic properties, which are the pinched hysteresis loop (V-I curve). However, the human brain consists of billions of neurons as its functional unit cell, which are connected to each other through synapses. Certainly, it is an incredible biological central processing unit (CPU) that performs operations ranging from simple arithmetic to complex real-time activities while consuming less power. While overriding the von Neumann architecture for the bottleneck, C. Mead, back in the late 1990s, coined the term neuromorphic computing in his invited paper, where mimicking biological neurons from an analogous point of view was mostly inspired. This is meant to shift toward a non von Neumann computing architecture, a new paradigm in which data movement is no longer a concern. This can be achieved by thinking of in-memory computing or computing-in-memory architecture from the material to device level and then into a whole system-level perspective of implementing the hardware [6]. 2. Neuromorphic Computing 2.1 Literature Review We have investigated the gist out of the summary shown in Table 1 of the neuromorphic chips discussed above, the key features of each of the neuromorphic chips designed most recently. Although advancements are continuing to push neuromorphic computing further with cutting-edge research and development, there is a long way to go to achieve brain-like performance, as we have seen from state-of-the-art developments [7–9]. Chip Technology/Hardware Integration Density Functionality/ Performance Metrics SpiNNaker developed by the University of Manchester ARM968, 130 nm CMOS chip Up to 1K neurons per core with 1 M cores Programmable numerical simulations with 72-bit messages, for real-time simulation of spike networks TrueNorth by IBM Digital ASIC at 28 nm CMOS 1 M neurons, 256 M synapses, 1-bit synaptic state to represent a connection, with 4 programmable 9-bit weights/neuron SNN emulation without on-chip learning; 26pJ power per synaptic operation Loihi by Intel Digital ASIC at 14 nm CMOS 130 k neurons, 130 M synapses with variable weight resolution (1–9 bits) Supports on-chip learning with plasticity rules such as Hebbian, pairwise, and triplet-STDP, 23.6 pJ per synaptic operation (at nominal operating conditions) Biological neurons in a typical mammalian brain Computational process by electrochemical spike signals from neuron to neuron via synapses Approx. 86 billion neurons with 1Quadrillion or 1000 trillion synaptic connections Overall 20 W of power for real-time activities, in a healthy mammalian brain Table I: State-of-the-art comparison of computing schemes implemented from the perspective of neuromorphic computing 3. Methodology To enhance this growing field of neuromorphic computing inspired by the mammalian brain, we should independently conduct a thorough analysis of the results obtained in our next section from both electronic and neuroscientific perspectives. We designed two types of novel modified memristor-based synaptic bridge circuits that are efficacious in mimicking biological neural behavior, such as STDP characteristics and low-power consumption of components. In this work, we have reconfigured the synaptic circuits as our new findings for a better artificial neuron perceptron, the 2 memristor bridge synapse circuit (type 1, type 2) proposed by N. Wang et al., where they showed better symmetry of the synaptic weight with a wider range of weight updates [10]. We named two synaptic circuits two-resistor one capacitor (2R1C) and two-transistor one capacitor (2T1C) based on the number of components designed and/or employed to mimic the synapses involved in biological neuron activities. However, the modification of those circuits from [10] is to improve the rate of firing at a certain threshold bias voltage with a wide range of characteristic gains. 4. Results and Findings Here, these synaptic circuits exhibit STDP characteristics through the capacitance formed between the connections, possibly defined as the axon terminal of the other neuron, which may receive this signal if connected accordingly, and biological ion-exchange phenomena occur properly. We simulated this circuit in the SPICE environment, and the results are discussed in detail. Our findings of the modification of these synaptic circuits and designs come with distinct advantages after simulation. These are shown and explained for circuits 2R1C and 2T1C, respectively. Case I Modified synaptic bridge circuit simulation results for each of the components and the intricacies of the 2R1C model. For each of the circuit components used (e.g., Op-Amp, potential divider biasing resistor, voltage sources of parameterized PWM, etc.) are analogously realized from the neuroscience point of view. This is the rudimentary part of this research work, which may haul the progress of neuromorphic computing research from the original perspective. To confirm the results achieved by this 2R1C-modified synaptic circuitry, we achieved synapse-like properties in which a Biolek window function-based HP memristor two-terminal model was employed effectively. Case II Modified synaptic bridge circuit simulation results for each of the components and the intricacies of the 2T1C model. Figure 17: This shows that the M1 current activated the firing properties very well. Surprisingly, this circuit operates as a threshold dendrite circuit with a better spike transient property, as shown in [13]. This is a better realization than the CMOS dendrite circuit emulated there. Therefore, the standalone M1 memristor underwent spike modulation of the dendrite circuit. Hence, our designed 2R1C and 2T1C synaptic circuit models both show that to employ more improved synaptic circuits, as there are two CMOS transistors working in the subthreshold region where the M1 and M2 memristors connect back-to-back, as elaborated in an earlier section. Clearly, the equivalent channel resistance of the MOS device between the drain and source can be adjusted by changing the gate voltage, which can make this circuit more flexible than the memristor bridge synapse circuit (2R1C). This approach is suitable for a higher-integration environment and a stronger intensity of the input signal [14]. Finally, if we consider the power consumption of both the synaptic circuits mimicked, then the output spike amplitudes of the current and voltage pairs can be analyzed under these circumstances. Considering the first case for 2R1C-type synaptic circuitry – V SPIKE = 4.026 V, I SYNAPSE = I C1 ~ 189.00 µA. Therefore, the power consumption of the 2R1C circuit is P 2R1C = V SPIKE x I SYNAPSE = 76 mW .…. (1) Similarly, considering the second case for 2T1C-type synapse circuitry, V SPIKE ~ 1.00 V, I SYNAPSE = I C1 = 1.9 mA. Therefore, the power consumption of the 2T1C circuit is P 2T1C = V SPIKE x I SYNAPSE = 1.9 mW ...…(2) Therefore, this unerring fact cannot be avoided because although these two modifications performed in [56] revealed that the 2R1C circuitry, which may have the characteristics of a high retention of voltage spikes, will be useful for some applications. Thus, P 2R1C = 40 x P 2T1C ……………………………………………… ...(i) In addition, the major objective of this research is to lower the power consumption of the computation itself, which is 40 times greater than that of the 2R1C model. Hence, a step forward in achieving low-power neuromorphic computing computing-in-memory (CIM) is to mitigate the ‘von Neuman Bottleneck’ problem. Thus, in brief, we achieved a 40 time orders of magnitude power reduction per synaptic spike event from equation (i). In fact, we are enthusiastic about improving state-of-the-art neuromorphic computing hardware realization through further improvements, which may shed some light on this topic. 5. Conclusion and Outlook The findings of this thesis might be suitable for realizing the core of a spiking neural network architecture using two different types of memristor-based synapse circuitry improved by concentrating on state-of-the-art [10] and configuring a memristor to function as a synapse, enabling the STDP learning process aiming to achieve a low-power neuromorphic computing structure. We achieved a low-power neuron-activated synaptic bridge circuit, which was modified from previous state-of-the-art research. However, recent progress in neuromorphic computing has aimed to achieve a low-power architecture that employs an in-memory computing architecture, successfully implementing non-Von Neumann computing, where first, the separation of memory and processing units is no longer needed; then, the emulation of biological computing processes is performed appropriately. As current VLSI technology is at its very limits, the end of Moore's law is taking us somewhere else that will eventually lead us to the uncertainty of the quantum arena from electronics materials. However, some characteristics of Memristor and ReRAM, such as their neuron-like behavior and logical synthesis, have been shown to be more efficient than ever before. Currently, research progress in neuromorphic computing is booming due to the lack of the desired speed of current computing architectures and the large number of datasets available in parallel. The fact that large datasets are fed into processors that may not be designed to perform such power-hungry computations is becoming a major concern. Hence, biological computing architecture is always available to learn from it and mimic it with advanced neuroscience knowledge. Eventually, digital signal processors have also become power-hungry and have slowed down due to the enormous amount of data fed to them. Hence, an efficient architecture from device- to system-level perspectives needs to be implemented that mimics neural computing in the brain with an ~ 20 W power consumption level and performs real-time computing within the memory, eliminating the need for separate memory and processing units, unlike the von Neumann architecture. Declarations Acknowledgments We would like to express our earnest thanks to our academic supervisor A.B.M. Noushad Bhuiyan and Md. Israil Hossain for their constant guidance for this research submitted as a thesis for the degree of B.Sc. in Electrical Engineering. Data availability The data that support the findings of this study are available from the corresponding author upon reasonable request. Conflict of Interest The authors have no conflicts to disclose. References Neumann JV (1981) The principles of large-scale computing machines, IEEE Annals of the History of Computing, vol. 3, no. 3, pp. 263–273, Jul Mead C (1990) Neuromorphic electronic systems. Proc IEEE 78:1629–1636 Chua L (1971) Memristor-the missing circuit element. IEEE Trans Circuit Theory 18(5):507–519 Burr GW et al (2014) Access devices for 3D crosspoint memory. J Vac Sci Technol B Nanotechnol Microelectron 32:040802 Biolek Z, Biolek D, Biolkova V (2009) SPICE Model of Memristor with Nonlinear Dopant Drift. Radioengineering. 18 Poon C-S, Zhou K (2011) Neuromorphic silicon neurons and large-scale neural networks. Front Neurosci 5 Merolla PA, Arthur JV, Alvarez-Icaza R, Cassidy AS, Sawada J, Akopyan F, Jackson BL, Imam N, Guo C, Nakamura Y, Brezzo B, Vo I, Esser SK, Appuswamy R, Taba B, Amir A, Flickner MD, Risk WP, Manohar R, Modha DS (2014) A million spiking-neuron integrated circuit with a scalable communication network and interface. Science 345(6197):668–673 Davies M, Srinivasa N, Lin T, Chinya G, Cao Y, Choday SH, Dimou G, Joshi P, Imam N, Jain S, Liao Y, Lin C, Lines A, Liu R, Mathaikutty D, McCoy S, Paul A, Tse J, Venkataramanan G, Weng Y, Wild A, Yang Y, Wang H (2018) Loihi: A neuromorphic manycore processor with on-chip learning, IEEE Micro, vol. 38, no. 1, pp. 82–99, January Orchard G, Frady EP, Rubin DBD, Sanborn S, Shrestha S, Friedrich T (2021) Sommer and Mike Davies. Efficient Neuromorphic Signal Processing with Loihi 2. 2021 IEEE Workshop Signal Process Syst (SiPS) : 254–259 Wang N, Li L, Chen Y, Wang, Hongyu, Yang, Zheming, Long, Dingyu (2023) Memristor bridge synapse for better artificial neuron perceptron. AIP Adv 13. 10.1063/5.0138920 Xu W, Wang J, Yan X (2021) Advances in Memristor-Based Neural Networks. Front Nanotechnol 3:645995. 10.3389/fnano.2021.645995 Huang M, Schwacke M, Onen M, Alamo, Jesús, Li, Ju, Yildiz, Bilge (2023) Electrochemical Ionic Synapses: Progress and Perspectives. Adv Mater 35. 10.1002/adma.202205169 James A, Zhanbossinov A, Smagulova (2016) Kamilya. CMOS-Memristor Dendrite Threshold Circuits. 10.6084/M9.FIGSHARE.3793086 Ma L, Tong Y, He L (2021) J Phys : Conf Ser 2108(1):012029 Additional Declarations The authors declare no competing interests. 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The pinched hysteresis loop curve is generated in the SPICE platform.\u003c/p\u003e","description":"","filename":"2.png","url":"https://assets-eu.researchsquare.com/files/rs-4607889/v1/fee6c171893f3f23502c9648.png"},{"id":58794717,"identity":"e102567c-0800-4df7-a702-d392cd2eb55d","added_by":"auto","created_at":"2024-06-21 08:06:45","extension":"png","order_by":3,"title":"Figure 3","display":"","copyAsset":false,"role":"figure","size":194084,"visible":true,"origin":"","legend":"\u003cp\u003eAdapted memristor model with a Biolek window showing the STDP spikes (green) with associated memristance in accordance with the applied sinusoid (red).\u003c/p\u003e","description":"","filename":"3.png","url":"https://assets-eu.researchsquare.com/files/rs-4607889/v1/07e845adbf2e6e878963a231.png"},{"id":58794189,"identity":"e369543e-e5a1-4108-82eb-2142e913dc40","added_by":"auto","created_at":"2024-06-21 07:58:45","extension":"png","order_by":4,"title":"Figure 4","display":"","copyAsset":false,"role":"figure","size":89341,"visible":true,"origin":"","legend":"\u003cp\u003eOur modified, designed and proposed two resistor one capacitor (2R1C) versions of the synaptic bridge circuit. This circuit shows promising characteristics that can facilitate neuromorphic chip design and development for further realization of neuromorphic processing units (NPUs).\u003c/p\u003e","description":"","filename":"image4.png","url":"https://assets-eu.researchsquare.com/files/rs-4607889/v1/44ba32210f3635cf796058cb.png"},{"id":58793388,"identity":"7cb330c1-3c3f-4045-baec-5e3b76db7342","added_by":"auto","created_at":"2024-06-21 07:50:44","extension":"png","order_by":5,"title":"Figure 5","display":"","copyAsset":false,"role":"figure","size":48761,"visible":true,"origin":"","legend":"\u003cp\u003eThe modified, designed and proposed version of the synaptic bridge circuit named the two transistor (CMOS) one capacitor (2T1C) circuit model that is also simulated in the SPICE environment shows low-power consumption per synaptic event compared to its predecessor model from 2R1C shown in Fig. 4 above.\u003c/p\u003e","description":"","filename":"image5.png","url":"https://assets-eu.researchsquare.com/files/rs-4607889/v1/1b722d9a23d557b829040b2f.png"},{"id":58794188,"identity":"2421157e-33c9-421b-aa36-3d374d6e4d8d","added_by":"auto","created_at":"2024-06-21 07:58:44","extension":"png","order_by":6,"title":"Figure 6","display":"","copyAsset":false,"role":"figure","size":79224,"visible":true,"origin":"","legend":"\u003cp\u003eInput pulse (PWM) applied to the modified two memristor bridge synapse circuit in [fig. 5.1]. The simulation parameters included a pulse width of 10 ms delay, rise and fall time = 1 ns, on time = 20 ms with a period of 30 ms applied for infinite cycles within an 800 ms simulation runtime.\u003c/p\u003e","description":"","filename":"image6.png","url":"https://assets-eu.researchsquare.com/files/rs-4607889/v1/2c553409305739e310c87b7f.png"},{"id":58793384,"identity":"a663e4fd-c056-437e-bf4c-54712acc07ee","added_by":"auto","created_at":"2024-06-21 07:50:44","extension":"png","order_by":7,"title":"Figure 7","display":"","copyAsset":false,"role":"figure","size":169552,"visible":true,"origin":"","legend":"\u003cp\u003eV-I characteristics curve of memristor\u003cdel\u003e \u003c/del\u003e-based synapses (Memristor 1)\u003cdel\u003e \u003c/del\u003e; self-holding or latching of the pinched hysteresis loop. This is the literal realization of a memristor as memory + resistor = memristor for improved synaptic spike retention [12].\u003c/p\u003e","description":"","filename":"image7.png","url":"https://assets-eu.researchsquare.com/files/rs-4607889/v1/c8dc1ffc42e66aaf652f6532.png"},{"id":58793382,"identity":"b6bd526a-6583-4ef3-b3ac-47ef8ed359aa","added_by":"auto","created_at":"2024-06-21 07:50:44","extension":"png","order_by":8,"title":"Figure 8","display":"","copyAsset":false,"role":"figure","size":192047,"visible":true,"origin":"","legend":"\u003cp\u003eVolt-Ampere characteristics of adjacent synapse M2 (memristor 2) showing the resistance-based memory curve (hysteresis loop), which is almost identical to that of memristor 1 (M1).\u003c/p\u003e","description":"","filename":"image8.png","url":"https://assets-eu.researchsquare.com/files/rs-4607889/v1/d605240513f9f56f9c59cb01.png"},{"id":58793389,"identity":"944cd1db-66ac-467d-b881-416604e4c702","added_by":"auto","created_at":"2024-06-21 07:50:45","extension":"png","order_by":9,"title":"Figure 9","display":"","copyAsset":false,"role":"figure","size":87093,"visible":true,"origin":"","legend":"\u003cp\u003eOutput ion-channel current spiking analogous to that of a biological neuron spiked toward the next adjacent axon\u003cdel\u003e-\u003c/del\u003e terminal of the associated synapse (neuron). This is the current that a particular synapse carries out because of electrochemical ion exchange phenomena between the axon of a neuron and the dendrite of the adjacent neuron (basically forming synapse-like behavior).\u003c/p\u003e","description":"","filename":"image9.png","url":"https://assets-eu.researchsquare.com/files/rs-4607889/v1/5fb8a84a9b6d8c2da1bb54a6.png"},{"id":58793393,"identity":"025faf58-9924-47c2-a0e0-410ab0d0e683","added_by":"auto","created_at":"2024-06-21 07:50:45","extension":"png","order_by":10,"title":"Figure 10","display":"","copyAsset":false,"role":"figure","size":111603,"visible":true,"origin":"","legend":"\u003cp\u003eSpike-Timing-Dependent\u003cdel\u003e-\u003c/del\u003e Plasticity (STDP) exhibiting properties of the output capacitance. The neuron that is connected to the concerned neuron-synapse spike timing\u003cdel\u003e,\u003c/del\u003e will be excited by this spike and undergo long-term potentiation (LTP), as one can infer from this figure. The spiking voltage level then stabilized at a very subtle difference from the value stored after transmitting losses between neuron firings.\u003c/p\u003e","description":"","filename":"image10.png","url":"https://assets-eu.researchsquare.com/files/rs-4607889/v1/4ff192f7bb19e09f8230f905.png"},{"id":58793387,"identity":"27201162-6670-4ea5-bcc4-318490c0cf08","added_by":"auto","created_at":"2024-06-21 07:50:44","extension":"png","order_by":11,"title":"Figure 11","display":"","copyAsset":false,"role":"figure","size":89709,"visible":true,"origin":"","legend":"\u003cp\u003eSelf-hold or latching current spiking of the capacitance itself; the current is highly likely to decrease in the absence of a biased spiking voltage. It may seem like the STDP, but it is the spiking that acts as a remainder after transmission through adjacent synapses.\u003c/p\u003e","description":"","filename":"image11.png","url":"https://assets-eu.researchsquare.com/files/rs-4607889/v1/c434f6d85fb8cb7d2652db6a.png"},{"id":58794194,"identity":"af831a25-df29-446d-bea9-91a4d4533d26","added_by":"auto","created_at":"2024-06-21 07:58:45","extension":"png","order_by":12,"title":"Figure 12","display":"","copyAsset":false,"role":"figure","size":88731,"visible":true,"origin":"","legend":"\u003cp\u003eCapacitance charge‒discharge pinched loop after a certain V‒I spike pair for ion/spike exchange between neuron synapses.\u003c/p\u003e","description":"","filename":"image12.png","url":"https://assets-eu.researchsquare.com/files/rs-4607889/v1/318051478ecdceb87a8d0f59.png"},{"id":58793390,"identity":"1b3d3920-f8f2-4bdc-80a4-fb8867eae054","added_by":"auto","created_at":"2024-06-21 07:50:45","extension":"png","order_by":13,"title":"Figure 13","display":"","copyAsset":false,"role":"figure","size":81958,"visible":true,"origin":"","legend":"\u003cp\u003eV-I characteristics of the modified 2T1C synaptic bridge circuit, showing a positive pinched hysteresis loop, plausibly indicating a better memory range because of its intrinsic ability to mimic biological synapse behavior.\u003c/p\u003e","description":"","filename":"image13.png","url":"https://assets-eu.researchsquare.com/files/rs-4607889/v1/836d771a76c7c043febe3648.png"},{"id":58794192,"identity":"3b1a230f-292d-4cde-a27d-b67ade52f417","added_by":"auto","created_at":"2024-06-21 07:58:45","extension":"png","order_by":14,"title":"Figure 14","display":"","copyAsset":false,"role":"figure","size":84130,"visible":true,"origin":"","legend":"\u003cp\u003eThe output voltage spike generated, which is transmitted onto the synchronized axon/dendrite circuitry of an adjacent neuron as the STDP during retention.\u003c/p\u003e","description":"","filename":"image14.png","url":"https://assets-eu.researchsquare.com/files/rs-4607889/v1/3c5d8968bb9813f143ff04b1.png"},{"id":58794190,"identity":"52e9c458-3e22-41a2-851b-cde0a7a0eb08","added_by":"auto","created_at":"2024-06-21 07:58:45","extension":"png","order_by":15,"title":"Figure 15","display":"","copyAsset":false,"role":"figure","size":56391,"visible":true,"origin":"","legend":"\u003cp\u003eThe current of the spiking signal summed at the synapsed edge of the neuron which is the output current of the Op-Amp 741IC, performing the summing amplification of the spiking inputs.\u003c/p\u003e","description":"","filename":"image15.png","url":"https://assets-eu.researchsquare.com/files/rs-4607889/v1/e5ea2a5112f3d5dcfbdc08f7.png"},{"id":58793392,"identity":"17dd1c8f-9287-4f13-8765-f54b0bc178ac","added_by":"auto","created_at":"2024-06-21 07:50:45","extension":"png","order_by":16,"title":"Figure 16","display":"","copyAsset":false,"role":"figure","size":101816,"visible":true,"origin":"","legend":"\u003cp\u003eThe capacitor charge‒discharge cycle (pinched hysteresis loop) exhibited as the STDP along with LTP and LTD as the retention action, i.e., memory passed onto the subjected neuron’s axon/dendrite circuit. Our modification is technically based upon the capacitance formed between the axon-dendrite junctions, which is, interestingly, the action of the synapse of any mammalian neuron.\u003c/p\u003e","description":"","filename":"image16.png","url":"https://assets-eu.researchsquare.com/files/rs-4607889/v1/a38b9c5e51a3f2a8f052d5de.png"},{"id":58793399,"identity":"e498566c-8f0e-42d8-82c7-ae9f95cbff3f","added_by":"auto","created_at":"2024-06-21 07:50:45","extension":"png","order_by":17,"title":"Figure 17","display":"","copyAsset":false,"role":"figure","size":88547,"visible":true,"origin":"","legend":"\u003cp\u003eThis shows that the M1 current activated the firing properties very well. Surprisingly, this circuit operates as a threshold dendrite circuit with a better spike transient property, as shown in [13]. This is a better realization than the CMOS dendrite circuit emulated there. Therefore, the standalone M1 memristor underwent spike modulation of the dendrite circuit.\u003c/p\u003e","description":"","filename":"image17.png","url":"https://assets-eu.researchsquare.com/files/rs-4607889/v1/aa33befbfeb0c7e9c58f9ff5.png"},{"id":58794187,"identity":"033c8bee-f714-415f-ae03-485526cde5ab","added_by":"auto","created_at":"2024-06-21 07:58:44","extension":"png","order_by":18,"title":"Figure 18","display":"","copyAsset":false,"role":"figure","size":47790,"visible":true,"origin":"","legend":"\u003cp\u003eThreshold dendrite circuitry conducive to memristor M2 in the corresponding circuit. This is the activation function curve with the threshold activation function employed for \u003csub\u003e14\u003c/sub\u003eSilicon at approximately 0.72 V.\u003c/p\u003e","description":"","filename":"image18.png","url":"https://assets-eu.researchsquare.com/files/rs-4607889/v1/007c0dfb78578765d786caa5.png"},{"id":58795071,"identity":"dc81d632-742c-4f40-9057-6a8e5ee51c57","added_by":"auto","created_at":"2024-06-21 08:14:46","extension":"pdf","order_by":0,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":2213082,"visible":true,"origin":"","legend":"","description":"","filename":"manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-4607889/v1/16aec3b4-6581-4a35-877c-dc28a7062e8f.pdf"}],"financialInterests":"The authors declare no competing interests.","formattedTitle":"\u003cp\u003eDesign of Memristor Based Modified Synapse Circuit for Low-Power Neuromorphic Computing\u003c/p\u003e","fulltext":[{"header":"1. Introduction","content":"\u003cp\u003eModern computers now must perform complex computations such as machine learning (ML) and deep learning (DL) algorithms, even when this large number of datasets are involved in computing; however, processors are becoming slower not only because of the computational complexity itself but also because of the movement of data shuttling from memory to the CPU or vice-versa [1].\u003c/p\u003e \u003cp\u003eThe long-term approach for reducing the power consumption of processors requires the development of a non von Neumann architecture that computes within the memory, eliminating the need for data communication. Thus, a more \u0026lsquo;brain-like\u0026rsquo; architecture called\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eneuromorphic computing was proposed by Carver Mead from Caltech after the 1990s to efficiently overcome the limitations of von Neumann architecture [2].\u003c/p\u003e \u003cdiv id=\"Sec2\" class=\"Section2\"\u003e \u003ch2\u003e1.1 Memristor\u003c/h2\u003e \u003cp\u003eMemristor was first postulated by Leon Chua in\u003c/p\u003e \u003cp\u003eIn 1971, the fourth fundamental passive electrical circuit element was first designed by HP laboratories in 2008 with a doped and undoped region with a TiO2-based model, as demonstrated in Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003e above [3\u0026ndash;4].\u003c/p\u003e \u003cp\u003eHP fabricated memristors are composed of two thin films of titanium dioxide (TiO\u003csub\u003e2\u003c/sub\u003e) sandwiched between two platinum (Pt) electrodes, named the top electrode (TE) and bottom electrode (BE). In our SPICE symbol, we have employed TE and BE as A and B respectively. The HP model of a memristor with the Biolek window function was reproduced only for transient analysis.\u003c/p\u003e \u003cp\u003eNonetheless, researchers are interested in applying memristors in the field of neuromorphic computing because memristors show some promising features that are rudimentary in emulating brain-like computing. These include but are not limited to\u003c/p\u003e \u003cp\u003e \u003cul\u003e \u003cli\u003e \u003cp\u003eMemory effect\u003c/p\u003e \u003c/li\u003e \u003cli\u003e \u003cp\u003eNanoscale size\u003c/p\u003e \u003c/li\u003e \u003cli\u003e \u003cp\u003eNon-Volatility\u003c/p\u003e \u003c/li\u003e \u003cli\u003e \u003cp\u003ePassivity\u003c/p\u003e \u003c/li\u003e \u003c/ul\u003e \u003c/p\u003e \u003c/div\u003e \u003cdiv id=\"Sec3\" class=\"Section2\"\u003e \u003ch2\u003e1.2 Modeling of memristor parameters\u003c/h2\u003e \u003cp\u003eWe have adapted the memristor model introduced by\u003c/p\u003e \u003cp\u003eBiolek et al. developed a memristor model based on the Biolek window function [5].\u003c/p\u003e \u003cp\u003eThe SPICE code for defining the subcircuit model is fine-tuned so that the memristor device characteristics are the intrinsic properties, which are the pinched hysteresis loop (V-I curve).\u003c/p\u003e \u003cp\u003eHowever, the human brain consists of billions of neurons as its functional unit cell, which are connected to each other through synapses. Certainly, it is an incredible biological central processing unit (CPU) that performs operations ranging from simple arithmetic to complex real-time activities while consuming less power.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eWhile overriding the von Neumann architecture for the bottleneck, C. Mead, back in the late 1990s, coined the term neuromorphic computing in his invited paper, where mimicking biological neurons from an analogous point of view was mostly inspired. This is meant to shift toward a non von Neumann computing architecture, a new paradigm in which data movement is no longer a concern. This can be achieved by thinking of in-memory computing or computing-in-memory architecture from the material to device level and then into a whole system-level perspective of implementing the hardware [6].\u003c/p\u003e \u003c/div\u003e"},{"header":"2. Neuromorphic Computing","content":"\u003cdiv id=\"Sec5\" class=\"Section2\"\u003e \u003ch2\u003e2.1 \u003cem\u003eLiterature Review\u003c/em\u003e\u003c/h2\u003e \u003cp\u003eWe have investigated the gist out of the summary shown in Table\u0026nbsp;1 of the neuromorphic chips discussed above, the key features of each of the neuromorphic chips designed most recently.\u003c/p\u003e \u003cp\u003eAlthough advancements are continuing to push neuromorphic computing further with cutting-edge research and development, there is a long way to go to achieve brain-like performance, as we have seen from state-of-the-art developments [7\u0026ndash;9].\u003c/p\u003e \u003cp\u003e \u003cdiv class=\"gridtable\"\u003e\u003ctable float=\"No\" id=\"Taba\" border=\"1\"\u003e \u003ccolgroup cols=\"4\"\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c1\" colnum=\"1\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c2\" colnum=\"2\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c3\" colnum=\"3\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c4\" colnum=\"4\"\u003e\u003c/div\u003e \u003cthead\u003e \u003ctr\u003e \u003cth align=\"left\" colname=\"c1\"\u003e \u003cp\u003eChip\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c2\"\u003e \u003cp\u003eTechnology/Hardware\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c3\"\u003e \u003cp\u003eIntegration Density\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c4\"\u003e \u003cp\u003eFunctionality/\u003c/p\u003e \u003cp\u003ePerformance Metrics\u003c/p\u003e \u003c/th\u003e \u003c/tr\u003e \u003c/thead\u003e \u003ctbody\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003e\u003cb\u003eSpiNNaker developed by the University of Manchester\u003c/b\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003eARM968, 130 nm CMOS chip\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003eUp to 1K neurons per core with 1 M cores\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c4\"\u003e \u003cp\u003eProgrammable numerical simulations with 72-bit messages, for real-time simulation of spike networks\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003e\u003cb\u003eTrueNorth by IBM\u003c/b\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003eDigital ASIC at 28 nm CMOS\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e1 M neurons, 256 M synapses, 1-bit synaptic state to represent a connection, with 4 programmable 9-bit weights/neuron\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c4\"\u003e \u003cp\u003eSNN emulation without on-chip learning; 26pJ power per synaptic operation\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003e\u003cb\u003eLoihi by Intel\u003c/b\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003eDigital ASIC at 14 nm CMOS\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e130 k neurons, 130 M synapses with variable weight resolution (1\u0026ndash;9 bits)\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c4\"\u003e \u003cp\u003eSupports on-chip learning with plasticity rules such as Hebbian, pairwise, and triplet-STDP, 23.6 pJ per synaptic operation (at nominal operating conditions)\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003e\u003cb\u003eBiological neurons in a typical mammalian brain\u003c/b\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003eComputational process by electrochemical spike signals from neuron to neuron via synapses\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003eApprox. 86\u0026nbsp;billion neurons with 1Quadrillion or 1000 trillion synaptic connections\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c4\"\u003e \u003cp\u003eOverall 20 W of power for real-time activities, in a healthy mammalian brain\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003c/tbody\u003e \u003c/colgroup\u003e \u003c/table\u003e\u003c/div\u003e \u003c/p\u003e \u003cp\u003e \u003cb\u003eTable I: State-of-the-art comparison of computing schemes implemented from the perspective of neuromorphic computing\u003c/b\u003e \u003c/p\u003e \u003c/div\u003e"},{"header":"3. Methodology","content":"\u003cp\u003eTo enhance this growing field of neuromorphic computing inspired by the mammalian brain, we should independently conduct a thorough analysis of the results obtained in our next section from both electronic and neuroscientific perspectives.\u003c/p\u003e \u003cp\u003eWe designed two types of novel modified memristor-based synaptic bridge circuits that are efficacious in mimicking biological neural behavior, such as STDP characteristics and low-power consumption of components.\u003c/p\u003e \u003cp\u003eIn this work, we have reconfigured the synaptic circuits as our new findings for a better artificial neuron perceptron, the 2 memristor bridge synapse circuit (type 1, type 2) proposed by N. Wang et al., where they showed better symmetry of the synaptic weight with a wider range of weight updates [10]. We named two synaptic circuits two-resistor one capacitor (2R1C) and two-transistor one capacitor (2T1C) based on the number of components designed and/or employed to mimic the synapses involved in biological neuron activities.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eHowever, the modification of those circuits from [10] is to improve the rate of firing at a certain threshold bias voltage with a wide range of characteristic gains.\u003c/p\u003e"},{"header":"4. Results and Findings","content":"\u003cp\u003eHere, these synaptic circuits exhibit STDP characteristics through the capacitance formed between the connections, possibly defined as the axon terminal of the other neuron, which may receive this signal if connected accordingly, and biological ion-exchange phenomena occur properly. We simulated this circuit in the SPICE environment, and the results are discussed in detail.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eOur findings of the modification of these synaptic circuits and designs come with distinct advantages after simulation. These are shown and explained for circuits 2R1C and 2T1C, respectively.\u003c/p\u003e \u003cp\u003e \u003cstrong\u003eCase I\u003c/strong\u003e \u003cp\u003eModified synaptic bridge circuit simulation results for each of the components and the intricacies of the 2R1C model.\u003c/p\u003e \u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eFor each of the circuit components used (e.g., Op-Amp, potential divider biasing resistor, voltage sources of parameterized PWM, etc.) are analogously realized from the neuroscience point of view. This is the rudimentary part of this research work, which may haul the progress of neuromorphic computing research from the original perspective.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eTo confirm the results achieved by this 2R1C-modified synaptic circuitry, we achieved synapse-like properties in which a Biolek window function-based HP memristor two-terminal model was employed effectively.\u003c/p\u003e \u003cp\u003e \u003cstrong\u003eCase II\u003c/strong\u003e \u003cp\u003eModified synaptic bridge circuit simulation results for each of the components and the intricacies of the 2T1C model.\u003c/p\u003e \u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eFigure 17: This shows that the M1 current activated the firing properties very well. Surprisingly, this circuit operates as a threshold dendrite circuit with a better spike transient property, as shown in [13]. This is a better realization than the CMOS dendrite circuit emulated there. Therefore, the standalone M1 memristor underwent spike modulation of the dendrite circuit.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eHence, our designed 2R1C and 2T1C synaptic circuit models both show that to employ more improved synaptic circuits, as there are two CMOS transistors working in the subthreshold region where the M1 and M2 memristors connect back-to-back, as elaborated in an earlier section. Clearly, the equivalent channel resistance of the MOS device between the drain and source can be adjusted by changing the gate voltage, which can make this circuit more flexible than the memristor bridge synapse circuit (2R1C). This approach is suitable for a higher-integration environment and a stronger intensity of the input signal [14].\u003c/p\u003e \u003cp\u003eFinally, if we consider the power consumption of both the synaptic circuits mimicked, then the output spike amplitudes of the current and voltage pairs can be analyzed under these circumstances. Considering the first case for 2R1C-type synaptic circuitry \u0026ndash;\u003c/p\u003e \u003cp\u003eV\u003csub\u003eSPIKE\u003c/sub\u003e = 4.026 V,\u003c/p\u003e \u003cp\u003eI\u003csub\u003eSYNAPSE\u003c/sub\u003e = I\u003csub\u003eC1\u003c/sub\u003e ~ 189.00 \u0026micro;A.\u003c/p\u003e \u003cp\u003eTherefore, the power consumption of the 2R1C circuit is\u003c/p\u003e \u003cp\u003eP\u003csub\u003e2R1C\u003c/sub\u003e\u0026thinsp;=\u0026thinsp;V\u003csub\u003eSPIKE\u003c/sub\u003e x I\u003csub\u003eSYNAPSE\u003c/sub\u003e = 76 mW .\u0026hellip;. (1)\u003c/p\u003e \u003cp\u003eSimilarly, considering the second case for 2T1C-type synapse circuitry,\u003c/p\u003e \u003cp\u003eV\u003csub\u003eSPIKE\u003c/sub\u003e ~ 1.00 V,\u003c/p\u003e \u003cp\u003eI\u003csub\u003eSYNAPSE\u003c/sub\u003e = I\u003csub\u003eC1\u003c/sub\u003e = 1.9 mA.\u003c/p\u003e \u003cp\u003eTherefore, the power consumption of the 2T1C circuit is\u003c/p\u003e \u003cp\u003eP\u003csub\u003e2T1C\u003c/sub\u003e\u0026thinsp;=\u0026thinsp;V\u003csub\u003eSPIKE\u003c/sub\u003e x I\u003csub\u003eSYNAPSE\u003c/sub\u003e = 1.9 mW ...\u0026hellip;(2)\u003c/p\u003e \u003cp\u003eTherefore, this unerring fact cannot be avoided because although these two modifications performed in [56] revealed that the 2R1C circuitry, which may have the characteristics of a high retention of voltage spikes, will be useful for some applications.\u003c/p\u003e \u003cp\u003eThus, P\u003csub\u003e2R1C\u003c/sub\u003e\u0026thinsp;=\u0026thinsp;40 x P\u003csub\u003e2T1C \u0026hellip;\u0026hellip;\u0026hellip;\u0026hellip;\u0026hellip;\u0026hellip;\u0026hellip;\u0026hellip;\u0026hellip;\u0026hellip;\u0026hellip;\u0026hellip;\u0026hellip;\u0026hellip;\u0026hellip;\u0026hellip;\u0026hellip;\u0026hellip;\u003c/sub\u003e...(i)\u003c/p\u003e \u003cp\u003eIn addition, the major objective of this research is to lower the power consumption of the computation itself, which is 40 times greater than that of the 2R1C model.\u003c/p\u003e \u003cp\u003eHence, a step forward in achieving low-power neuromorphic computing computing-in-memory (CIM) is to mitigate the \u0026lsquo;von Neuman Bottleneck\u0026rsquo; problem. Thus, in brief, we achieved a 40 time orders of magnitude power reduction per synaptic spike event from equation (i).\u003c/p\u003e \u003cp\u003eIn fact, we are enthusiastic about improving state-of-the-art neuromorphic computing hardware realization through further improvements, which may shed some light on this topic.\u003c/p\u003e"},{"header":"5. Conclusion and Outlook","content":"\u003cp\u003eThe findings of this thesis might be suitable for realizing the core of a spiking neural network architecture using two different types of memristor-based synapse circuitry improved by concentrating on state-of-the-art [10] and configuring a memristor to function as a synapse, enabling the STDP learning process aiming to achieve a low-power neuromorphic computing structure.\u003c/p\u003e \u003cp\u003eWe achieved a low-power neuron-activated synaptic bridge circuit, which was modified from previous state-of-the-art research. However, recent progress in neuromorphic computing has aimed to achieve a low-power architecture that employs an in-memory computing architecture, successfully implementing non-Von Neumann computing, where first, the separation of memory and processing units is no longer needed; then, the emulation of biological computing processes is performed appropriately.\u003c/p\u003e \u003cp\u003eAs current VLSI technology is at its very limits, the end of Moore's law is taking us somewhere else that will eventually lead us to the uncertainty of the quantum arena from electronics materials. However, some characteristics of Memristor and ReRAM, such as their neuron-like behavior and logical synthesis, have been shown to be more efficient than ever before.\u003c/p\u003e \u003cp\u003eCurrently, research progress in neuromorphic computing is booming due to the lack of the desired speed of current computing architectures and the large number of datasets available in parallel. The fact that large datasets are fed into processors that may not be designed to perform such power-hungry computations is becoming a major concern. Hence, biological computing architecture is always available to learn from it and mimic it with advanced neuroscience knowledge. Eventually, digital signal processors have also become power-hungry and have slowed down due to the enormous amount of data fed to them.\u003c/p\u003e \u003cp\u003eHence, an efficient architecture from device- to system-level perspectives needs to be implemented that mimics neural computing in the brain with an ~\u0026thinsp;20 W power consumption level and performs real-time computing within the memory, eliminating the need for separate memory and processing units, unlike the von Neumann architecture.\u003c/p\u003e"},{"header":"Declarations","content":"\u003cp\u003e\u003cstrong\u003eAcknowledgments\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eWe would like to express our earnest thanks to our academic supervisor A.B.M. Noushad Bhuiyan and Md. Israil Hossain for their constant guidance for this research submitted as a thesis for the degree of B.Sc. in Electrical Engineering.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eData availability\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eThe data that support the findings of this study are available from the corresponding author upon reasonable request.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eConflict of Interest\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eThe authors have no conflicts to disclose.\u003c/p\u003e"},{"header":"References","content":"\u003col\u003e\u003cli\u003e\u003cspan\u003eNeumann JV (1981) The principles of large-scale computing machines, IEEE Annals of the History of Computing, vol. 3, no. 3, pp. 263\u0026ndash;273, Jul\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eMead C (1990) Neuromorphic electronic systems. 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We have shown some current candidates from the material to device level for neuromorphic computing and how our proposed memristor-based bridge synapse circuit can emulate the spiking properties of neurons in biological brains with plasticity phenomena such as LTP, LTD and STDP or SRDP (spike rate-dependent plasticity), considering that low power consumption is the primary key to this kind of computing.\u003c/p\u003e","manuscriptTitle":"Design of Memristor Based Modified Synapse Circuit for Low-Power Neuromorphic Computing","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2024-06-21 07:50:39","doi":"10.21203/rs.3.rs-4607889/v1","editorialEvents":[{"type":"communityComments","content":0}],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true}}],"origin":"","ownerIdentity":"6f974b83-52bc-40b2-bf58-bc6355f6af6e","owner":[],"postedDate":"June 21st, 2024","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"posted","subjectAreas":[{"id":33477733,"name":"Electrical Engineering"},{"id":33477734,"name":"Electronic Materials and Devices"},{"id":33477735,"name":"Computer Architecture and Engineering"}],"tags":[],"updatedAt":"2024-06-21T07:50:40+00:00","versionOfRecord":[],"versionCreatedAt":"2024-06-21 07:50:39","video":"","vorDoi":"","vorDoiUrl":"","workflowStages":[]},"version":"v1","identity":"rs-4607889","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-4607889","identity":"rs-4607889","version":["v1"]},"buildId":"8U1c8b4HqxoKbykW_rLl7","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}