FPGA Based Quantum Circuit Simulator: Processing 30 Qubit Systems | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article FPGA Based Quantum Circuit Simulator: Processing 30 Qubit Systems Nasir Ali Nasir Ali, Abhishek Tiwari Abhishek Tiwari, Nadeem khan Nadeem khan, and 5 more This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-8581344/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract This paper presents a field-programmable gate array (FPGA) implementation of a quantum circuit simulator capable of processing 30-qubit systems, representing over 1.07 billion quantum states stored in 8 GB of memory. Built on the Xilinx Alveo U55C platform with High Bandwidth Memory (HBM) technology, our system demonstrates deterministic performance through a 16-bank parallel memory distribution architecture integrated with the Qiskit quantum computing framework. We achieved complete verification across all qubit configurations from 1 to 30 qubits, with execution times ranging from 5 milliseconds to approximately 49 minutes. The simulator supports a comprehensive quantum gate library including single-qubit operations (Hadamard, Pauli gates, rotation gates) and multi-qubit gates (CNOT, controlled-Z, Toffoli. Our performance analysis reveals distinct operational regimes where FPGA excels for small-scale circuits (1-12 qubits) but faces scalability challenges beyond 15 qubits when compared to GPU architectures. This work establishes FPGA as a practical platform for quantum algorithm development and circuit verification, particularly valuable for applications requiring deterministic timing and energy-efficient computation. The architecture provides clear pathways for expansion to 31+ qubits through memory configuration enhancements. FPGA Quantum Computing Quantum Simulation High Bandwidth Memory HBM Xilinx Alveo Quantum Circuit Qiskit Hardware Acceleration Quantum Gates Full Text Additional Declarations No competing interests reported. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. 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Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-8581344","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":576880689,"identity":"6bb7869b-b19f-433a-ae52-3b34ad6c064a","order_by":0,"name":"Nasir Ali Nasir Ali","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAAA/ElEQVRIiWNgGAWjYJCCAwwMFjz87I3tPz4AeWzsxGmR4JHsOXxAcgZICzNxFkkwGNxwS5DmAbEJaTFnP/7wcEWNhAzDDR4DY5tf2+T5mBkYP3zMwa3FsifH4OCZYxI8jLN7DJJz+24btjEzMEvO3IZbi8GBHIaDDWwSPMwyZwwO5/bcZgRqYWPmxafl/PMHBxv+SfCwSeQYNlv23LYnrOVGgsHBxjYJHh6JtGRmhh+3E4nQ8gaopU+CR4Ln8DHG3obbyW3MjM34/XI+/fHHhm829vbHG9sYfvy5bTu/vfngh494tKACxjYw2UCsehD4Q4riUTAKRsEoGCkAAEGNUhTkZgTSAAAAAElFTkSuQmCC","orcid":"","institution":"Centre for Development of Advanced Computing","correspondingAuthor":true,"prefix":"","firstName":"Nasir","middleName":"Ali Nasir","lastName":"Ali","suffix":""},{"id":576880690,"identity":"487d6397-a31d-4e6e-90c1-e72a6b5261b7","order_by":1,"name":"Abhishek Tiwari Abhishek Tiwari","email":"","orcid":"","institution":"Centre for Development of Advanced Computing","correspondingAuthor":false,"prefix":"","firstName":"Abhishek","middleName":"Tiwari Abhishek","lastName":"Tiwari","suffix":""},{"id":576880691,"identity":"2abcc32c-2275-4415-ab05-9b601b512aee","order_by":2,"name":"Nadeem khan Nadeem khan","email":"","orcid":"","institution":"Centre for Development of Advanced Computing","correspondingAuthor":false,"prefix":"","firstName":"Nadeem","middleName":"khan Nadeem","lastName":"khan","suffix":""},{"id":576880692,"identity":"aaa05dc5-5b70-42f3-8b58-1b50bc2ff8b2","order_by":3,"name":"Imam Mazhar Imam Mazhar","email":"","orcid":"","institution":"Centre for Development of Advanced Computing","correspondingAuthor":false,"prefix":"","firstName":"Imam","middleName":"Mazhar Imam","lastName":"Mazhar","suffix":""},{"id":576880693,"identity":"2faa3390-9ad0-4315-ac1c-3d7a966bbd88","order_by":4,"name":"Karan Islur Karan Islur","email":"","orcid":"","institution":"Centre for Development of Advanced Computing","correspondingAuthor":false,"prefix":"","firstName":"Karan","middleName":"Islur Karan","lastName":"Islur","suffix":""},{"id":576880694,"identity":"30312f1d-dc5c-4e29-914a-757fdd2c0e33","order_by":5,"name":"Himanshu Gupta Himanshu Gupta","email":"","orcid":"","institution":"Centre for Development of Advanced Computing","correspondingAuthor":false,"prefix":"","firstName":"Himanshu","middleName":"Gupta Himanshu","lastName":"Gupta","suffix":""},{"id":576880695,"identity":"43d3351f-5357-40c3-a459-516fd142b635","order_by":6,"name":"Sachin kumar Sachin kumar","email":"","orcid":"","institution":"University of Delhi","correspondingAuthor":false,"prefix":"","firstName":"Sachin","middleName":"kumar Sachin","lastName":"kumar","suffix":""},{"id":576880696,"identity":"84a602da-9c36-42c7-9cab-e95cc3ae155f","order_by":7,"name":"Pankaj Tyagi Pankaj Tyagi","email":"","orcid":"","institution":"University of Delhi","correspondingAuthor":false,"prefix":"","firstName":"Pankaj","middleName":"Tyagi Pankaj","lastName":"Tyagi","suffix":""}],"badges":[],"createdAt":"2026-01-12 11:53:12","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-8581344/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-8581344/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":100665602,"identity":"fd793014-2224-44a1-9a6e-726216a50700","added_by":"auto","created_at":"2026-01-20 09:28:56","extension":"json","order_by":0,"title":"","display":"","copyAsset":false,"role":"acdc-reference","size":8335,"visible":true,"origin":"","legend":"","description":"","filename":"81033317476e4239a7213d4f4c6de45e.json","url":"https://assets-eu.researchsquare.com/files/rs-8581344/v1/4630b41d6cd3bee807a65fcc.json"},{"id":104193969,"identity":"20bb1378-0f59-409c-8bd4-7f4a40348d6c","added_by":"auto","created_at":"2026-03-09 02:39:52","extension":"pdf","order_by":1,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":1332115,"visible":true,"origin":"","legend":"","description":"","filename":"FPGABasedQuantumCircuitSimulation.pdf","url":"https://assets-eu.researchsquare.com/files/rs-8581344/v1_covered_84f3bd27-209d-4f94-8668-29722bf612e1.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"FPGA Based Quantum Circuit Simulator: Processing 30 Qubit Systems","fulltext":[],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":false,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":true,"highlight":"","institution":"","isAcceptedByJournal":false,"isAuthorSuppliedPdf":true,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":true,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"
[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"FPGA, Quantum Computing, Quantum Simulation, High Bandwidth Memory, HBM, Xilinx Alveo, Quantum Circuit, Qiskit, Hardware Acceleration, Quantum Gates","lastPublishedDoi":"10.21203/rs.3.rs-8581344/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-8581344/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"This paper presents a field-programmable gate array (FPGA) implementation of a quantum circuit simulator capable of processing 30-qubit systems, representing over 1.07 billion quantum states stored in 8 GB of memory. Built on the Xilinx Alveo U55C platform with High Bandwidth Memory (HBM) technology, our system demonstrates deterministic performance through a 16-bank parallel memory distribution architecture integrated with the Qiskit quantum computing framework. \nWe achieved complete verification across all qubit configurations from 1 to 30 qubits, with execution times ranging from 5 milliseconds to approximately 49 minutes. The simulator supports a comprehensive quantum gate library including single-qubit operations (Hadamard, Pauli gates, rotation gates) and multi-qubit gates (CNOT, controlled-Z, Toffoli. Our performance analysis reveals distinct operational regimes where FPGA excels for small-scale circuits (1-12 qubits) but faces scalability challenges beyond 15 qubits when compared to GPU architectures.\nThis work establishes FPGA as a practical platform for quantum algorithm development and circuit verification, particularly valuable for applications requiring deterministic timing and energy-efficient computation. The architecture provides clear pathways for expansion to 31+ qubits through memory configuration enhancements.","manuscriptTitle":"FPGA Based Quantum Circuit Simulator: Processing 30 Qubit Systems","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2026-01-20 08:31:28","doi":"10.21203/rs.3.rs-8581344/v1","editorialEvents":[{"type":"communityComments","content":0}],"status":"published","journal":{"display":true,"email":"
[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true}}],"origin":"","ownerIdentity":"5e8808a8-6d94-4d59-8f22-c8b99bda3a03","owner":[],"postedDate":"January 20th, 2026","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"posted","subjectAreas":[],"tags":[],"updatedAt":"2026-05-19T03:38:11+00:00","versionOfRecord":[],"versionCreatedAt":"2026-01-20 08:31:28","video":"","vorDoi":"","vorDoiUrl":"","workflowStages":[]},"version":"v1","identity":"rs-8581344","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-8581344","identity":"rs-8581344","version":["v1"]},"buildId":"XKTyCvWXoU3ODBz1xrDgd","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}
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