Performance Analysis of 4x4 Modified Wallace Tree Multiplier Using Different Full Adders

Performance Analysis of 4x4 Modified Wallace Tree Multiplier Using Different Full Adders | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Performance Analysis of 4x4 Modified Wallace Tree Multiplier Using Different Full Adders Hema Chitra S -, Deepakraj R -, Boffi Rajalin R P -, Krupa Shankar S - This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-2929806/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract In Embedded and DSP system architectures. Multipliers play a huge role for the mathematical computations. A system’s performance is generally determined by the performance of the multiplier because the multiplier is generally the slowest element in the whole system and also it is occupying more area. Adders play an important role in doing the Multiplication operation for VLSI and digital signal processing applications. In this paper, a modified full adder using multiplexer is proposed to improve the speed of multiplier. In WALLACE tree multiplier the partial sum adders can also be rearranged in a tree like structure. The partial sum adders are implemented with the proposed full adder. The optimization of adder has led to the improvement in performance of multiplier The challenge involved in this kind of multipliers is to realize the complete structure with a minimum number of AND Gates and adder elements. The designs are developed using Verilog HDL and the functional verification was done using Xilinx Vivado18.3. Simulation results are obtained for a 4x4 modified Wallace tree multiplier using various partial sum adders like RCA, CSA and CKA. The results show that the delay is reduced in multiplier using the proposed adder. Modified WALLACE tree Multiplier Multiplexer Based Full adder Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Introduction Digital circuits multiplier play a major role in the efficient implementation of arithmetic circuits. Arithmetic logics can be done by multipliers [1] [1], [2] [2],[4], [1–5] [5], [6] [6] implemented in suitable logic. A multiplier is a circuit which performs multiplication of two numbers and gives the multiplied output. In Modified WAL- LACE Tree multiplier, simple adder circuits are used to perform operations. The power consumption, delay and area [3] [3], [4] [4],[6], [7] [7] [8–11] have always been an important design consideration for any circuit designer. Many DSP structures incorporate multipliers in their design. Delay of the circuit inevitably changes with the delay of the multiplier. Many research works are involved in reducing the delay of the multiplier so that the delay of the whole circuit can be reduced. Modified WALLACE Tree multiplier [5] has been evolved as high speed and area efficient multiplier. The Modified WALLACE Tree multiplier involves ANDing of multiplier and multiplicand bits for the generation of partial products. To reduce the complexity of design, many re- searches are carried out by using multiplexer based full adder structures which shows that the area is reduced drastically. This paper presents three different forms of Modified WALLACE Tree multiplier using three different adder circuits namely ripple carry adder, carry skip adder and carry select adder. After developing these three different forms of Modified WALLACE Tree multiplier a comparative study is being carried out on the basis of delay and power consumption by the three designs. This work mainly deals with the replacement of full adders with modified full adder in the reduction phase of the Modified WALLACE Tree multiplier. In the proposed method, a modified full adder (FA-3) using multiplexer is applied to achieve delay improvement compared to the existing techniques with reduced power consumption. Related Works Implementation of 4x4 modified WALLACE tree multiplier using the following 6-bit adders: Ripple carry adder Carry Select adder Carry bypass adder Methods A. WALLACE Tree Multiplier using RCA: The basic architecture for WALLACE Tree Multi- plier using ripple carry adder is shown in Fig 2. In this architecture both the multiplier and multiplicand are ANDed together and partial products are generated. Thus, WALLACE Tree is implemented. In this arrangement the partial products with same weight are grouped together and written in a column. Here there are totally six columns in the arrangement in accordance to the maximum weight carried by partial product term i.e., a3b3 has highest weight 6. Now the addition is applied in each column using half and full adders according to the need, if there are two numbers to be added then half adder is employed and if there are three numbers for addition then full adder has to be used partial product a0b0 doesn’t need any computation, it is directly taken as the LSB of the product. Therefore, R0 is equals to P0. Now the task to be done is to extract two final bits from each remaining column after excluding the first column from right as it contains P0. Now carefully examining the columns, the second column from right has two partial products P4 and P1, which means it has only two bits in all so they can be taken directly and termed as A0 and B0. Moving further to the next column having three terms, P8, P5 and P2, so here we need to apply adders to get final two bits for RCA. A half adder is applied with P8 and P5 as inputs which gives two outputs sum and carry, now from this column the sum obtained is taken as B1, the partial product term P2 as A1 and the carry so obtained as A2. Going ahead in this manner, we will get final six pairs of bits as A0B0, A1B1, A2B2, A3B3, A4B4, and A5B5. These numbers so obtained can be treated as two input numbers for the adder. The WALLACE tree implementation with the RCA is shown in Fig.2. The main objective is to implement the three types of adders in WALLACE multiplier. As known, the first Similarly, the Ripple Carry Adder is replaced with Carry Select Adder and Carry Skip Adder and the architecture and the tree formation is shown below in Fig.3. B. Conventional Full Adder (FA): The traditional full adder circuit is obtained using 2 XOR gates, 3AND gates and an OR gate. The Boolean expressions used are shown in the below Fig 7 sum = a ^ b ^ cin carry=(a · b)+(b · cin)+(cin · a) C. Modified full adder- 1 (FA-1): In this paper [6] have proposed this model. In this work, the detailed study about WALLACE tree multi- plier and truncated multipliers is done with both nor- mal full adder and modified full adder-1 and it is shown that modified full adder-1 implementation occupies less area are shown in the below Fig 8 D. Modified full adder- 2(FA-2): In this paper [9] have proposed this Model. It is also shown that the use of modified full adder-2 is better in terms of delay and area are shown in the below fig 9 E. Proposed Full Adder(FA-3): The proposed multiplexer based full adder shown in fig 10, consists of five 2:1 Multiplexer. In this proposed full adder, propagation delay of SUM is lesser compared to CARRY, Since SUM generation needs only two 2:1 Multiplexer whereas CARRY generation requires three 2:1 Multiplexer which has the critical path. In SUM part, the inputs B and ~B is fed as the input to the first multiplexer A is given as select line input and the generated output of first multiplexer is that modified full adder-1 implementation occupies less area are shown in the below Fig 8 Modified full adder- 2(FA-2): In this paper [9] have proposed this Model. It is also shown that the use of modified full adder-2 is better in terms of delay and area are shown in the below fig 9 Proposed Full Adder(FA-3): The proposed multiplexer based full adder shown in fig 10, consists of five 2:1 Multiplexer. In this proposed full adder, propagation delay of SUM is lesser compared to CARRY, Since SUM generation needs only two 2:1 Multiplexer whereas CARRY generation requires three 2:1 Multiplexer which has the critical path. In SUM part, the inputs B and ~B is fed as the input to the first multiplexer A is given as select line input and the generated output of first multiplexer is fed to the input of second multiplexer cin is selected as the select line and the out is generated as SUM. In carry part, three multiplexers are used. Fig.10 shows the proposed diagram of multiplexer based full adder. In the first stage of the multiplexer, cin, 1, 0 are given as input B is the select line. The output generated by the two multiplexers are fed to the input of the second stage multiplexer. A is taken as the select line which gives CARRY as outputs are shown in the below fig 10 and fig 11. Results Performance Analysis: F. 1 Modified WALLACE Tree Multiplier F.1.1 Delay & Power Table I show the setup time delay of modified Wal- lace tree multiplier using 6-bit ripple carry adder, carry select adder and carry select adder. Here 6-bit is used because the partial products generated by the adder is 6-bit is used because the partial products generated by the adder is 6-bit Table II shows the Hold time delay of modified Wallace tree multiplier using 6-bit ripple carry adder, carry select adder and carry select adder Table III shows the power of modified Wallace tree multiplier using 6-bit ripple carry adder, carry select adder and carry select adder. Table IV shows the Area of modified Wallace tree multiplier using 6-bit ripple carry adder, carry select adder and carry select adder Comparing with conventional full adder, proposed FA-3 gives 25.98% of reduction, 23.61% of reduction compared with FA-1, 17.85% reduction compared with FA-2 for setup delay. In all comparisons ripple carry adder gives better results than carry select adder and carry skip adder. Conclusion In this paper, an 4x4 Modified WALLACE tree multiplier with 6-bit ripple carry adder, carry select adder carry skip adder was implemented and tabulations were done for maximum delay and power. The results proved that the proposed work optimizes the delay compared to other structures. It would be really interesting, to implement the design with 32 bit and 64-bit architecture. This design will be the major help for designing a MAC unit . Declarations Ethical Approval Not applicable Competing interests Not applicable Authors' contributions Not applicable Funding Not applicable Availability of data and materials Not applicable References C Wallace. A suggestion for a fast multiplier. IEEE Transaction on Electronic Computers, (13):14–17. R S Waters and E E Swartzlander. A reduced complexity WALLACE multiplier reduction. IEEE Transactions on Computers, 59(8):1134–1137 (2010). B Ramkumar, M Harish, and Kittur. Low power and area efficient carry select adder. IEEE Trans- actions on Very Large Scale Integration (VLSI) Sys- tems, 20:371–375 (2012). Shahzad Asif and Yinan Kong. Low Area WAL- LACE Multiplier. VLSI Design (2014). M Damarlaparadhasaradhi, N Prashanthi, and Vivek. Modified WALLACE Tree Multiplier using Efficient Square Root Carry Select Adder. Inter- national Journal of Computer Science and Mobile Computing, 2(9):128–138 (2014). S Murugeswari and S K Mohideen. Design of area efficient and low power multipliers using multiplexer based full adder. In 2nd International Conference on Current Trends in Engineering and technology (ICCTET), pages 388–392 (2014). Bharti kokila, Nithish Jaiswal, V Kumar, Pavithra Seshadri, G Lakshminarayanan, Low Power WALLACE Tree Multiplier Using Modified Full Adder, 2015 3rd International Conference on Signal Processing, Communication and Networking (ICSCN). K. Anirudh Kumar Maurya, K Balasindhuri, Y Ramalakshmanna, and N Udaya Kumar. Design and Implementation of 32-Bit Adders Using Various Full Adders. International Conference on Inno- vations in Power and Advanced Computing Tech- nologies. SreehariVeeramachaneni et al., “Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors ” International Conference on VLSI Design, VLSID, IEEEComputer Society, 2007, ISSN 0-7695-2762-0 . J M Rabaey. Digital Integrated Circuits-A Design Perspective. Prentice-Hall, Upper Saddle River, NJ (2001). N Weste, D Harris, and Cmos Vlsi Design. A Circuit and System Perspective. Addison-Wesley, USA,20 V. Additional Declarations No competing interests reported. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. 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-","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAAA60lEQVRIie2RsQrCMBCGLzi4RLp2al/hioOL+CwWwS4WdO8Q6eDiA0R8CTdxqwTSpeBoB4e4OBdcXEQjOjilugnmg+RykA/+4wAsll/EfRbv1WZvd43S1oewr5SQvStG/GWqoEq60drJ96pKDuDMMiLGBgUPEgmXw3jDR5Mplydwiz4IblLcETRaTMSrkoapfgCUAIKagnGtXNktwl0Rplet+HUKlFohLOtjFm1TohWsU7Ac4nYuB4GehSzmUtCgCFlNsMFRXZKe33FyVV0S4Xm5EGdjMHjtAoHio9Lnfj4Boak++2mxWCx/xx2zA1UGOCmx+QAAAABJRU5ErkJggg==","orcid":"","institution":"PSG College of Technology","correspondingAuthor":true,"submittingAuthor":false,"prefix":"","firstName":"Hema","middleName":"Chitra S","lastName":"-","suffix":""},{"id":200575554,"identity":"2a7dee74-5514-4eea-b570-287d6dcd9711","order_by":1,"name":"Deepakraj R -","email":"","orcid":"","institution":"PSG College of Technology","correspondingAuthor":false,"submittingAuthor":false,"prefix":"","firstName":"Deepakraj","middleName":"R","lastName":"-","suffix":""},{"id":200575556,"identity":"f1d67fc9-b6f9-4805-9764-97e09f46fd6f","order_by":2,"name":"Boffi Rajalin R P -","email":"","orcid":"","institution":"PSG College of Technology","correspondingAuthor":false,"submittingAuthor":false,"prefix":"","firstName":"Boffi","middleName":"Rajalin R P","lastName":"-","suffix":""},{"id":200575558,"identity":"44ae8aad-4bc2-47d7-921c-5bf28db6bf97","order_by":3,"name":"Krupa Shankar S -","email":"","orcid":"","institution":"PSG College of Technology","correspondingAuthor":false,"submittingAuthor":false,"prefix":"","firstName":"Krupa","middleName":"Shankar S","lastName":"-","suffix":""}],"badges":[],"createdAt":"2023-05-13 05:14:16","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-2929806/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-2929806/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":37188728,"identity":"c8fab13d-7836-4a41-a568-653428021803","added_by":"auto","created_at":"2023-05-18 12:47:14","extension":"png","order_by":1,"title":"Figure 1","display":"","copyAsset":false,"role":"figure","size":109123,"visible":true,"origin":"","legend":"\u003cp\u003eModified WALLACE Multiplier Architecture using RCA\u003c/p\u003e","description":"","filename":"1.png","url":"https://assets-eu.researchsquare.com/files/rs-2929806/v1/5409c1ec4beba7510ecee369.png"},{"id":37190093,"identity":"6dfd5079-3d3f-4f3f-a864-5bc15a1b02d3","added_by":"auto","created_at":"2023-05-18 12:55:14","extension":"png","order_by":2,"title":"Figure 2","display":"","copyAsset":false,"role":"figure","size":56773,"visible":true,"origin":"","legend":"\u003cp\u003e4x4 WALLACE Tree Multiplier using RCA\u003c/p\u003e","description":"","filename":"2.png","url":"https://assets-eu.researchsquare.com/files/rs-2929806/v1/99d253586b1747fe9c9c440d.png"},{"id":37188734,"identity":"7bb039a7-6d17-4894-b0fb-68986f0f4087","added_by":"auto","created_at":"2023-05-18 12:47:14","extension":"png","order_by":3,"title":"Figure 3","display":"","copyAsset":false,"role":"figure","size":142799,"visible":true,"origin":"","legend":"\u003cp\u003eModified WALLACE Multiplier Architecture using CSA\u003c/p\u003e","description":"","filename":"3.png","url":"https://assets-eu.researchsquare.com/files/rs-2929806/v1/56d025c261c8fd48bf923279.png"},{"id":37188732,"identity":"71889725-16fb-4e4b-ba5d-0d914cc37187","added_by":"auto","created_at":"2023-05-18 12:47:14","extension":"png","order_by":4,"title":"Figure 4","display":"","copyAsset":false,"role":"figure","size":51723,"visible":true,"origin":"","legend":"\u003cp\u003e4x4 WALLACE Tree Multiplier using CSA\u003c/p\u003e","description":"","filename":"4.png","url":"https://assets-eu.researchsquare.com/files/rs-2929806/v1/c769429b45a16c25f61ade51.png"},{"id":37190922,"identity":"284ffed4-c5ae-4411-8981-e002c95007d7","added_by":"auto","created_at":"2023-05-18 13:03:14","extension":"png","order_by":5,"title":"Figure 5","display":"","copyAsset":false,"role":"figure","size":102823,"visible":true,"origin":"","legend":"\u003cp\u003eModified WALLACE Tree Multiplier Architecture using CSK\u003c/p\u003e","description":"","filename":"5.png","url":"https://assets-eu.researchsquare.com/files/rs-2929806/v1/98846c67bb59b1ae56f15ff2.png"},{"id":37188733,"identity":"29342245-a3ef-4bf9-8016-f4140e107081","added_by":"auto","created_at":"2023-05-18 12:47:14","extension":"png","order_by":6,"title":"Figure 6","display":"","copyAsset":false,"role":"figure","size":61229,"visible":true,"origin":"","legend":"\u003cp\u003e4x4 WALLACE Tree Multiplier using CSK\u003c/p\u003e","description":"","filename":"6.png","url":"https://assets-eu.researchsquare.com/files/rs-2929806/v1/45a444617d073812ceeb616e.png"},{"id":37188729,"identity":"5ab42256-f796-491d-abcb-627dd44d805d","added_by":"auto","created_at":"2023-05-18 12:47:14","extension":"png","order_by":7,"title":"Figure 7","display":"","copyAsset":false,"role":"figure","size":54024,"visible":true,"origin":"","legend":"\u003cp\u003eConventional full adder cell (FA)\u003c/p\u003e","description":"","filename":"7.png","url":"https://assets-eu.researchsquare.com/files/rs-2929806/v1/4e41dd5871572d00726d6124.png"},{"id":37190095,"identity":"936593f3-a278-4d44-96c2-1c73124fd031","added_by":"auto","created_at":"2023-05-18 12:55:14","extension":"png","order_by":8,"title":"Figure 8","display":"","copyAsset":false,"role":"figure","size":68565,"visible":true,"origin":"","legend":"\u003cp\u003eModified full adder-1 (FA1)\u003c/p\u003e","description":"","filename":"8.png","url":"https://assets-eu.researchsquare.com/files/rs-2929806/v1/9c62fae95b505c7606b65615.png"},{"id":37188738,"identity":"55785448-502c-4fda-9d6c-c1dfcff7d998","added_by":"auto","created_at":"2023-05-18 12:47:14","extension":"png","order_by":9,"title":"Figure 9","display":"","copyAsset":false,"role":"figure","size":67743,"visible":true,"origin":"","legend":"\u003cp\u003eModified full adder-2(FA2)\u003c/p\u003e","description":"","filename":"9.png","url":"https://assets-eu.researchsquare.com/files/rs-2929806/v1/bdcbbdf4949725cb05abe184.png"},{"id":37188737,"identity":"badacae3-7f7f-44c6-8275-45e8ca30e74c","added_by":"auto","created_at":"2023-05-18 12:47:14","extension":"png","order_by":10,"title":"Figure 10","display":"","copyAsset":false,"role":"figure","size":24715,"visible":true,"origin":"","legend":"\u003cp\u003eProposed Full Adder (FA-3)\u003c/p\u003e","description":"","filename":"10.png","url":"https://assets-eu.researchsquare.com/files/rs-2929806/v1/e2a5101b7c40fdb468bd56c5.png"},{"id":37188736,"identity":"742768d2-5622-4c86-b166-da35e9cfb811","added_by":"auto","created_at":"2023-05-18 12:47:14","extension":"png","order_by":11,"title":"Figure 11","display":"","copyAsset":false,"role":"figure","size":28168,"visible":true,"origin":"","legend":"\u003cp\u003eProposed Full Adder (FA-3)\u003c/p\u003e","description":"","filename":"11.png","url":"https://assets-eu.researchsquare.com/files/rs-2929806/v1/ed335eeba5e652c00d212320.png"},{"id":37549691,"identity":"9063d351-d622-44ab-8e0a-0bc86fe42168","added_by":"auto","created_at":"2023-05-26 17:14:29","extension":"pdf","order_by":0,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":894815,"visible":true,"origin":"","legend":"","description":"","filename":"manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-2929806/v1/071c0272-b7d1-448d-833c-f2b6a735108a.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"Performance Analysis of 4x4 Modified Wallace Tree Multiplier Using Different Full Adders","fulltext":[{"header":"Introduction","content":"\u003cp\u003eDigital circuits multiplier play a major role in the efficient implementation of arithmetic circuits. Arithmetic logics can be done by multipliers [1] [1], [2] [2],[4], [1\u0026ndash;5]\u0026nbsp;\u003c/p\u003e\n\u003cp\u003e[5], [6] [6] implemented in suitable logic. A multiplier is a circuit which performs multiplication of two numbers and gives the multiplied output. In Modified WAL- LACE Tree multiplier, simple adder circuits are used to perform operations. The power consumption, delay and area [3] [3], [4] [4],[6], [7] [7] [8\u0026ndash;11] have always been an important design consideration for any circuit designer. Many DSP structures incorporate multipliers in their design. Delay of the circuit inevitably changes with the delay of the multiplier. Many research works are involved in reducing the delay of the multiplier so that the delay of the whole circuit can be reduced. Modified WALLACE Tree multiplier [5] has been evolved as high speed and area efficient multiplier. The Modified WALLACE \u0026nbsp;Tree \u0026nbsp;multiplier involves \u0026nbsp; ANDing of multiplier and multiplicand bits for the generation of partial products. To reduce the complexity of design, many re- searches are carried out by using multiplexer based full adder structures which shows that the area is reduced drastically.\u003c/p\u003e\n\u003cp\u003eThis paper presents three different forms of Modified WALLACE Tree multiplier using three different adder circuits namely ripple carry adder, carry skip adder and carry select adder. After developing these three different forms of Modified WALLACE Tree \u0026nbsp;multiplier a comparative study is being carried out on the basis of delay and power consumption by the three designs. This work mainly deals with the replacement \u0026nbsp;of full adders with modified full adder in the reduction phase of the Modified WALLACE Tree multiplier. In the proposed method, a modified full adder (FA-3) using multiplexer is applied to achieve delay improvement compared to the existing techniques with reduced power consumption.\u003c/p\u003e\n\u003col\u003e\n \u003cli\u003eRelated\u0026nbsp;Works\u003c/li\u003e\n\u003c/ol\u003e\n\u003cp\u003eImplementation of 4x4 modified WALLACE tree multiplier using the following 6-bit adders:\u003c/p\u003e\n\u003col\u003e\n \u003cli\u003eRipple carry adder\u003c/li\u003e\n \u003cli\u003eCarry Select\u0026nbsp;adder\u003c/li\u003e\n \u003cli\u003eCarry bypass adder\u003c/li\u003e\n\u003c/ol\u003e"},{"header":"Methods","content":"\u003cp\u003eA. WALLACE Tree Multiplier using RCA:\u003c/p\u003e\n\u003cp\u003eThe basic architecture for WALLACE Tree Multi- plier using ripple carry adder is shown in Fig 2. In this architecture both the multiplier and multiplicand are ANDed together and partial products are generated. Thus, WALLACE Tree is implemented. In this arrangement the partial products with same weight are grouped together and written in a column. Here there are totally six columns in the arrangement in accordance to the maximum weight carried by partial product term i.e., a3b3 has highest weight 6. Now the addition is applied in each column using half and full adders according to the need, if there are two numbers to be added then half adder is employed and if there are three numbers for addition then full adder has to be used partial product a0b0 doesn\u0026rsquo;t need any computation, it is directly taken as the LSB of the product. Therefore, R0 is equals to P0. Now the task to be done is to extract two final bits from each remaining column after excluding the first column from right as it contains P0. Now carefully examining the columns, the second column from right has two partial products P4 and P1, which means it has only two bits in all so they can be taken directly and termed as A0 and B0. Moving further to the next column having three terms, P8, P5 and P2, so here we need to apply adders to get final two bits for RCA. A half adder is applied with P8 and P5 as inputs which gives two outputs sum and carry, now from this column the sum obtained is taken as B1, the partial product term P2 as A1 and the carry so obtained as A2. Going ahead in this manner, we will get final six pairs of bits as A0B0, A1B1, A2B2, A3B3, A4B4, and A5B5. These numbers so obtained can be treated as two input numbers for the adder. The WALLACE tree implementation with the RCA is shown in Fig.2.\u003c/p\u003e\n\u003cp\u003eThe main objective is to implement the three types of adders in WALLACE multiplier. As known, the first\u0026nbsp;\u003c/p\u003e\n\u003cp\u003eSimilarly, the Ripple Carry Adder is replaced with Carry Select Adder and Carry Skip Adder and the architecture and the tree formation is shown below in Fig.3.\u003c/p\u003e\n\u003cp\u003eB. Conventional Full Adder (FA):\u003c/p\u003e\n\u003cp\u003eThe\u0026nbsp;traditional\u0026nbsp;full\u0026nbsp;adder\u0026nbsp;circuit\u0026nbsp;is\u0026nbsp;obtained\u0026nbsp;using\u0026nbsp;2 XOR\u0026nbsp;gates, 3AND gates and an OR gate. The Boolean expressions\u0026nbsp;used\u0026nbsp;are\u0026nbsp;shown\u0026nbsp;in\u0026nbsp;the\u0026nbsp;below\u0026nbsp;Fig\u0026nbsp;7\u003c/p\u003e\n\u003col\u003e\n \u003cli\u003esum = a ^ b ^ cin\u003c/li\u003e\n \u003cli\u003ecarry=(a\u0026nbsp;\u003cem\u003e\u0026middot;\u0026nbsp;\u003c/em\u003eb)+(b\u0026nbsp;\u003cem\u003e\u0026middot;\u003c/em\u003ecin)+(cin\u003cem\u003e\u0026middot;\u003c/em\u003ea)\u003c/li\u003e\n\u003c/ol\u003e\n\u003cp\u003eC. Modified full adder- 1 (FA-1):\u003c/p\u003e\n\u003cp\u003eIn this paper [6] have proposed this model. In this work, the detailed study about WALLACE tree multi- plier and truncated multipliers is done with both nor- mal full adder and modified full adder-1 and it is shown that modified full adder-1 implementation occupies less area are shown in the below Fig 8\u003c/p\u003e\n\u003cp\u003eD. Modified full adder- 2(FA-2):\u003c/p\u003e\n\u003cp\u003eIn\u0026nbsp;this\u0026nbsp;paper\u0026nbsp;[9]\u0026nbsp;have\u0026nbsp;proposed\u0026nbsp;this\u0026nbsp;Model.\u0026nbsp;It\u0026nbsp;is\u0026nbsp;also shown\u0026nbsp;that\u0026nbsp;the\u0026nbsp;use\u0026nbsp;of\u0026nbsp;modified\u0026nbsp;full\u0026nbsp;adder-2\u0026nbsp;is\u0026nbsp;better\u0026nbsp;in terms of delay and area are shown in the below fig\u0026nbsp;9\u003c/p\u003e\n\u003cp\u003eE. Proposed Full Adder(FA-3):\u003c/p\u003e\n\u003cp\u003eThe\u0026nbsp;proposed\u0026nbsp;multiplexer\u0026nbsp;based\u0026nbsp;full\u0026nbsp;adder\u0026nbsp;shown\u0026nbsp;in fig\u0026nbsp;10,\u0026nbsp;consists\u0026nbsp;of\u0026nbsp;five\u0026nbsp;2:1\u0026nbsp;Multiplexer.\u0026nbsp;In\u0026nbsp;this\u0026nbsp;proposed full\u0026nbsp;adder,\u0026nbsp;propagation\u0026nbsp;delay\u0026nbsp;of\u0026nbsp;SUM\u0026nbsp;is\u0026nbsp;lesser\u0026nbsp;compared to CARRY,\u0026nbsp;Since SUM generation needs only two\u0026nbsp;2:1 Multiplexer whereas CARRY\u0026nbsp;generation requires\u0026nbsp;three 2:1\u0026nbsp;Multiplexer\u0026nbsp;which\u0026nbsp;has\u0026nbsp;the\u0026nbsp;critical\u0026nbsp;path.\u003c/p\u003e\n\u003cp\u003eIn SUM part, the inputs B and ~B is fed as the input to the first multiplexer A is given as select line input and the generated output of first multiplexer is\u0026nbsp;\u003c/p\u003e\n\u003cp\u003ethat\u0026nbsp;modified\u0026nbsp;full\u0026nbsp;adder-1\u0026nbsp;implementation\u0026nbsp;occupies\u0026nbsp;less area\u0026nbsp;are\u0026nbsp;shown\u0026nbsp;in\u0026nbsp;the\u0026nbsp;below\u0026nbsp;Fig\u0026nbsp;8\u003c/p\u003e\n\u003col start=\"1\"\u003e\n \u003cli\u003eModified full adder-\u0026nbsp;2(FA-2):\u003c/li\u003e\n\u003c/ol\u003e\n\u003cp\u003eIn\u0026nbsp;this\u0026nbsp;paper\u0026nbsp;[9]\u0026nbsp;have\u0026nbsp;proposed\u0026nbsp;this\u0026nbsp;Model.\u0026nbsp;It\u0026nbsp;is\u0026nbsp;also shown\u0026nbsp;that\u0026nbsp;the\u0026nbsp;use\u0026nbsp;of\u0026nbsp;modified\u0026nbsp;full\u0026nbsp;adder-2\u0026nbsp;is\u0026nbsp;better\u0026nbsp;in terms of delay and area are shown in the below fig\u0026nbsp;9\u003c/p\u003e\n\u003col start=\"2\"\u003e\n \u003cli\u003eProposed Full\u0026nbsp;Adder(FA-3):\u003c/li\u003e\n\u003c/ol\u003e\n\u003cp\u003eThe\u0026nbsp;proposed\u0026nbsp;multiplexer\u0026nbsp;based\u0026nbsp;full\u0026nbsp;adder\u0026nbsp;shown\u0026nbsp;in fig\u0026nbsp;10,\u0026nbsp;consists\u0026nbsp;of\u0026nbsp;five\u0026nbsp;2:1\u0026nbsp;Multiplexer.\u0026nbsp;In\u0026nbsp;this\u0026nbsp;proposed full\u0026nbsp;adder,\u0026nbsp;propagation\u0026nbsp;delay\u0026nbsp;of\u0026nbsp;SUM\u0026nbsp;is\u0026nbsp;lesser\u0026nbsp;compared to CARRY,\u0026nbsp;Since SUM generation needs only two\u0026nbsp;2:1 Multiplexer whereas CARRY\u0026nbsp;generation requires\u0026nbsp;three 2:1\u0026nbsp;Multiplexer\u0026nbsp;which\u0026nbsp;has\u0026nbsp;the\u0026nbsp;critical\u0026nbsp;path.\u003c/p\u003e\n\u003cp\u003eIn SUM part, the inputs B and ~B is fed as the input to the first multiplexer A is given as select line input and the generated output of first multiplexer is fed to the input of second multiplexer cin is selected as the select line and the out is generated as SUM. In carry part, three multiplexers are used. Fig.10 shows the proposed diagram of multiplexer based full adder. In the first stage of the multiplexer, cin, 1, 0 are given as input B is the select line. The output generated by the two multiplexers are fed to the input of the second stage multiplexer. A is taken as the select line which gives CARRY as outputs are shown in the below fig 10 and fig 11.\u003c/p\u003e"},{"header":"Results","content":"\u003col start=\"1\"\u003e\n \u003cli\u003ePerformance Analysis:\u003c/li\u003e\n\u003c/ol\u003e\n\u003cp\u003eF. 1 Modified WALLACE Tree Multiplier\u003c/p\u003e\n\u003cp\u003eF.1.1 Delay \u0026amp; Power\u003c/p\u003e\n\u003cp\u003eTable I show the setup time delay of modified Wal- lace tree multiplier using 6-bit ripple carry adder, carry select adder and carry select adder. Here 6-bit is used because the partial products generated by the adder is 6-bit is used because the partial products generated by the adder is 6-bit\u003c/p\u003e\n\u003cp\u003e\u003cimg src=\"https://myfiles.space/user_files/122228_c8a1650c59388082/122228_custom_files/img1684357144.png\"\u003e\u003c/p\u003e\n\u003cp\u003eTable II shows the Hold time delay of modified Wallace tree multiplier using 6-bit ripple carry adder, carry select adder and carry select adder\u003c/p\u003e\n\u003cp\u003eTable\u0026nbsp;III\u0026nbsp;shows the power of modified Wallace\u0026nbsp;tree multiplier using 6-bit ripple carry adder, carry select adder and carry select adder.\u003c/p\u003e\n\u003cp\u003eTable IV shows the Area of modified Wallace tree multiplier using 6-bit ripple carry adder, carry select adder and carry select adder\u003c/p\u003e\n\u003cp\u003eComparing with conventional full adder, proposed FA-3 gives 25.98% of reduction, 23.61% of reduction compared with FA-1, 17.85% reduction compared with\u003c/p\u003e\n\u003cp\u003e\u003cimg src=\"https://myfiles.space/user_files/122228_c8a1650c59388082/122228_custom_files/img1684357218.png\"\u003e\u003c/p\u003e\n\u003cp\u003e\u003cimg src=\"https://myfiles.space/user_files/122228_c8a1650c59388082/122228_custom_files/img1684357237.png\"\u003e\u003c/p\u003e\n\u003cp\u003eFA-2 for setup delay. In all comparisons ripple carry adder gives better results than carry select adder and carry skip adder.\u003c/p\u003e"},{"header":"Conclusion","content":"\u003cp\u003eIn this paper, an 4x4 Modified WALLACE tree multiplier with 6-bit ripple carry adder, carry select adder carry skip adder was implemented and tabulations were done for maximum delay and power. The results proved that the proposed work optimizes the delay compared to other structures. It would be really interesting, to implement the design with 32 bit and 64-bit architecture. This design will be the major help for designing a MAC unit .\u003c/p\u003e"},{"header":"Declarations ","content":"\u003cp\u003e\u003cstrong\u003eEthical Approval\u003c/strong\u003e\u0026nbsp;\u003c/p\u003e\n\u003cp\u003eNot\u0026nbsp;applicable\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003e\u0026nbsp;\u003c/strong\u003e\u003cstrong\u003eCompeting interests\u003c/strong\u003e\u0026nbsp;\u003c/p\u003e\n\u003cp\u003eNot applicable\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eAuthors\u0026apos; contributions\u003c/strong\u003e\u0026nbsp;\u003c/p\u003e\n\u003cp\u003eNot applicable\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003e\u0026nbsp;\u003c/strong\u003e\u003cstrong\u003eFunding\u0026nbsp;\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eNot applicable\u003c/p\u003e\n\u003cp\u003e\u0026nbsp;\u003cstrong\u003eAvailability of data and materials\u003c/strong\u003e\u0026nbsp;\u003c/p\u003e\n\u003cp\u003eNot applicable\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003e\u0026nbsp;\u003c/strong\u003e\u003c/p\u003e"},{"header":"References","content":"\u003col\u003e\n\u003cli\u003eC Wallace. A suggestion for a fast multiplier. IEEE Transaction on Electronic Computers, (13):14\u0026ndash;17.\u003c/li\u003e\n\u003cli\u003eR S Waters and E E Swartzlander. A reduced complexity WALLACE multiplier reduction. IEEE Transactions on Computers, 59(8):1134\u0026ndash;1137 (2010).\u003c/li\u003e\n\u003cli\u003eB Ramkumar, M Harish, and Kittur. Low power and area efficient carry select adder. IEEE Trans- actions on Very Large Scale Integration (VLSI) Sys- tems, 20:371\u0026ndash;375 (2012).\u003c/li\u003e\n\u003cli\u003eShahzad Asif and Yinan Kong. Low Area WAL- LACE Multiplier. VLSI Design (2014).\u003c/li\u003e\n\u003cli\u003eM Damarlaparadhasaradhi, N Prashanthi, and Vivek. Modified WALLACE Tree Multiplier using Efficient Square Root Carry Select Adder. Inter- national Journal of Computer Science and Mobile Computing, 2(9):128\u0026ndash;138 (2014).\u003c/li\u003e\n\u003cli\u003eS Murugeswari and S K Mohideen. Design of area efficient and low power multipliers using multiplexer based full adder. In 2nd International Conference on Current Trends in Engineering and technology (ICCTET), pages 388\u0026ndash;392 (2014). \u003c/li\u003e\n\u003cli\u003eBharti kokila, Nithish Jaiswal, V Kumar, Pavithra Seshadri, G Lakshminarayanan, Low Power WALLACE Tree Multiplier Using Modified Full Adder, 2015 3rd International Conference on Signal Processing, Communication and Networking (ICSCN).\u003c/li\u003e\n\u003cli\u003eK. Anirudh Kumar Maurya, K Balasindhuri, Y Ramalakshmanna, and N Udaya Kumar. Design and Implementation of 32-Bit Adders Using Various Full Adders. International Conference on Inno- vations in Power and Advanced Computing Tech- nologies.\u003c/li\u003e\n\u003cli\u003eSreehariVeeramachaneni et al., \u0026ldquo;Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors \u0026rdquo; International Conference on VLSI Design, VLSID, IEEEComputer Society, 2007, ISSN 0-7695-2762-0 .\u003c/li\u003e\n\u003cli\u003eJ M Rabaey. Digital Integrated Circuits-A Design Perspective. Prentice-Hall, Upper Saddle River, NJ (2001).\u003c/li\u003e\n\u003cli\u003eN Weste, D Harris, and Cmos Vlsi Design. A Circuit and System Perspective. Addison-Wesley, USA,20 V.\u003c/li\u003e\n\u003c/ol\u003e"}],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":true,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":true,"highlight":"","institution":"","isAcceptedByJournal":false,"isAuthorSuppliedPdf":false,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":false,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"Modified WALLACE tree Multiplier, Multiplexer Based Full adder","lastPublishedDoi":"10.21203/rs.3.rs-2929806/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-2929806/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"In Embedded and DSP system architectures. Multipliers play a huge role for the mathematical computations. A system’s performance is generally determined by the performance of the multiplier because the multiplier is generally the slowest element in the whole system and also it is occupying more area. Adders play an important role in doing the Multiplication operation for VLSI and digital signal processing applications. In this paper, a modified full adder using multiplexer is proposed to improve the speed of multiplier. In WALLACE tree multiplier the partial sum adders can also be rearranged in a tree like structure. The partial sum adders are implemented with the proposed full adder. The optimization of adder has led to the improvement in performance of multiplier The challenge involved in this kind of multipliers is to realize the complete structure with a minimum number of AND Gates and adder elements. The designs are developed using Verilog HDL and the functional verification was done using Xilinx Vivado18.3. Simulation results are obtained for a 4x4 modified Wallace tree multiplier using various partial sum adders like RCA, CSA and CKA. The results show that the delay is reduced in multiplier using the proposed adder.","manuscriptTitle":"Performance Analysis of 4x4 Modified Wallace Tree Multiplier Using Different Full Adders","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2023-05-18 12:47:09","doi":"10.21203/rs.3.rs-2929806/v1","editorialEvents":[{"type":"communityComments","content":0}],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true}}],"origin":"","ownerIdentity":"3af8338a-9d2e-4d0f-a5a6-120fbe3dc47d","owner":[],"postedDate":"May 18th, 2023","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"posted","subjectAreas":[],"tags":[],"updatedAt":"2023-05-26T17:14:17+00:00","versionOfRecord":[],"versionCreatedAt":"2023-05-18 12:47:09","video":"","vorDoi":"","vorDoiUrl":"","workflowStages":[]},"version":"v1","identity":"rs-2929806","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-2929806","identity":"rs-2929806","version":["v1"]},"buildId":"rHA-KDH7Qsr4HCuvH75dn","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}