A Framework for Compressive On-chip Action Potential Recording

A Framework for Compressive On-chip Action Potential Recording | bioRxiv /* */ /* */ <!-- <!-- /*! * yepnope1.5.4 * (c) WTFPL, GPLv2 */ (function(a,b,c){function d(a){return"[object Function]"==o.call(a)}function e(a){return"string"==typeof a}function f(){}function g(a){return!a||"loaded"==a||"complete"==a||"uninitialized"==a}function h(){var a=p.shift();q=1,a?a.t?m(function(){("c"==a.t?B.injectCss:B.injectJs)(a.s,0,a.a,a.x,a.e,1)},0):(a(),h()):q=0}function i(a,c,d,e,f,i,j){function k(b){if(!o&&g(l.readyState)&&(u.r=o=1,!q&&h(),l.onload=l.onreadystatechange=null,b)){"img"!=a&&m(function(){t.removeChild(l)},50);for(var d in y[c])y[c].hasOwnProperty(d)&&y[c][d].onload()}}var j=j||B.errorTimeout,l=b.createElement(a),o=0,r=0,u={t:d,s:c,e:f,a:i,x:j};1===y[c]&&(r=1,y[c]=[]),"object"==a?l.data=c:(l.src=c,l.type=a),l.width=l.height="0",l.onerror=l.onload=l.onreadystatechange=function(){k.call(this,r)},p.splice(e,0,u),"img"!=a&&(r||2===y[c]?(t.insertBefore(l,s?null:n),m(k,j)):y[c].push(l))}function j(a,b,c,d,f){return q=0,b=b||"j",e(a)?i("c"==b?v:u,a,b,this.i++,c,d,f):(p.splice(this.i++,0,a),1==p.length&&h()),this}function k(){var a=B;return a.loader={load:j,i:0},a}var l=b.documentElement,m=a.setTimeout,n=b.getElementsByTagName("script")[0],o={}.toString,p=[],q=0,r="MozAppearance"in l.style,s=r&&!!b.createRange().compareNode,t=s?l:n.parentNode,l=a.opera&&"[object Opera]"==o.call(a.opera),l=!!b.attachEvent&&!l,u=r?"object":l?"script":"img",v=l?"script":u,w=Array.isArray||function(a){return"[object Array]"==o.call(a)},x=[],y={},z={timeout:function(a,b){return b.length&&(a.timeout=b[0]),a}},A,B;B=function(a){function b(a){var a=a.split("!"),b=x.length,c=a.pop(),d=a.length,c={url:c,origUrl:c,prefixes:a},e,f,g;for(f=0;f<d;f++)g=a[f].split("="),(e=z[g.shift()])&&(c=e(c,g));for(f=0;f<b;f++)c=x[f](c);return c}function g(a,e,f,g,h){var i=b(a),j=i.autoCallback;i.url.split(".").pop().split("?").shift(),i.bypass||(e&&(e=d(e)?e:e[a]||e[g]||e[a.split("/").pop().split("?")[0]]),i.instead?i.instead(a,e,f,g,h):(y[i.url]?i.noexec=!0:y[i.url]=1,f.load(i.url,i.forceCSS||!i.forceJS&&"css"==i.url.split(".").pop().split("?").shift()?"c":c,i.noexec,i.attrs,i.timeout),(d(e)||d(j))&&f.load(function(){k(),e&&e(i.origUrl,h,g),j&&j(i.origUrl,h,g),y[i.url]=2})))}function h(a,b){function c(a,c){if(a){if(e(a))c||(j=function(){var a=[].slice.call(arguments);k.apply(this,a),l()}),g(a,j,b,0,h);else if(Object(a)===a)for(n in m=function(){var b=0,c;for(c in a)a.hasOwnProperty(c)&&b++;return b}(),a)a.hasOwnProperty(n)&&(!c&&!--m&&(d(j)?j=function(){var a=[].slice.call(arguments);k.apply(this,a),l()}:j[n]=function(a){return function(){var b=[].slice.call(arguments);a&&a.apply(this,b),l()}}(k[n])),g(a[n],j,b,n,h))}else!c&&l()}var h=!!a.test,i=a.load||a.both,j=a.callback||f,k=j,l=a.complete||f,m,n;c(h?a.yep:a.nope,!!i),i&&c(i)}var i,j,l=this.yepnope.loader;if(e(a))g(a,0,l,0);else if(w(a))for(i=0;i (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0];var j=d.createElement(s);var dl=l!='dataLayer'?'&l='+l:'';j.src='//www.googletagmanager.com/gtm.js?id='+i+dl;j.type='text/javascript';j.async=true;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-M677548'); Skip to main content Home About Submit ALERTS / RSS Search for this keyword Advanced Search New Results A Framework for Compressive On-chip Action Potential Recording View ORCID Profile Pumiao Yan , View ORCID Profile Dante G. Muratore , View ORCID Profile E.J. Chichilnisky , View ORCID Profile Boris Murmann , View ORCID Profile Tsachy Weissman doi: https://doi.org/10.1101/2025.09.26.678698 Pumiao Yan 1 Department of Electrical Engineering, Stanford University , CA, USA Roles: Student Member, IEEE Find this author on Google Scholar Find this author on PubMed Search for this author on this site ORCID record for Pumiao Yan Dante G. Muratore 2 Microelectronics Department, Delft University of Technology , The Netherlands Roles: Senior Member, IEEE Find this author on Google Scholar Find this author on PubMed Search for this author on this site ORCID record for Dante G. Muratore E.J. Chichilnisky 4 Department of Neurosurgery and Ophthalmology and the Hansen Experimental Physics Laboratory, Stanford University , CA, USA Find this author on Google Scholar Find this author on PubMed Search for this author on this site ORCID record for E.J. Chichilnisky Boris Murmann 3 Department of Electrical and Computer Engineering, University of Hawaii , Honolulu, HI, USA Roles: Fellow, IEEE Find this author on Google Scholar Find this author on PubMed Search for this author on this site ORCID record for Boris Murmann Tsachy Weissman 1 Department of Electrical Engineering, Stanford University , CA, USA Roles: Fellow, IEEE Find this author on Google Scholar Find this author on PubMed Search for this author on this site ORCID record for Tsachy Weissman For correspondence: tsachy{at}stanford.edu Abstract Full Text Info/History Metrics Preview PDF Abstract Scaling neural recording systems to thousands of channels creates extreme bandwidth demands, posing a challenge for resource-constrained, implantable devices. This work introduces an adaptive, multi-stage compression framework for high-bandwidth neural interfaces. The system combines a Wired-OR analog-to-digital compressive readout with a digital core that adaptively requantizes, selectively samples, and encodes the neural signals. Although prior work suggests that action potential recordings can be re-quantized to approximately the signal-to-noise (SNR) number of bits without significantly degrading decoding performance, our results show that the required resolution can often be reduced even further. By matching the number of quantization levels to the electrode’s maximum SNR (⌈log 2 SNR⌉ number of bits), we retain waveform fidelity while eliminating unnecessary precision that primarily captures noise. Recorded spike samples are selected using a mutual information-based criterion to preserve both spatial and temporal discriminative waveform features. A static entropy coder completes the pipeline with low computation overhead compression optimized for neural signal statistics. Evaluated on 512-channel macaque retina ex vivo data, the system preserves 90% of spikes while achieving a 1098× total compression over baseline. I. I ntroduction H IGH-DENSITY neural interfaces capable of recording from thousands of neurons at single-cell resolution are transforming both neuroscience and clinical neurotechnology [ 1 ]. These interfaces provide access to fine-grained activity across large neural populations, which offer unprecedented insight into complex interactions between neurons and their cooperative behaviors [ 2 ]–[ 7 ]. Applications of neural interfaces range from basic studies of sensory processing to brainmachine interfaces for motor rehabilitation, vision restoration, and sensory augmentation [ 8 ], [ 9 ]. Meeting the demands of long-term, high-resolution in vivo recording requires systems that have many simultaneous recording channels and high temporal resolution, and must operate fully wirelessly for stable chronic use. To support these applications, wired high-density microelectrode arrays (MEAs) with thousands of electrodes have been developed in research, enabling large-scale neural recordings with fine spatial and temporal resolution [ 10 ], [ 11 ]. However, existing fully implantable systems remain limited to roughly a thousand simultaneous channels [ 12 ] and are unable to preserve spike waveform information. As channel counts scale up, power consumption, silicon area, and data transmission requirements grow proportionally. Processing and transmitting this volume of data within the power and area constraints of a wireless implant becomes increasingly difficult. This motivates the need for hardware-friendly and power-efficient compression that reduces data through the data acquisition pipeline, without discarding critical spike-level information needed for downstream analysis. In neural recordings, most of the information relevant to downstream processing is contained in the shape and timing of action potentials [ 13 ], [ 14 ]. These features enable essential tasks such as spike detection, spike sorting, and cell-type classification (the spike processing pipeline of such tasks is shown in Fig. 1 ). Spike detection identifies the timing and location of events, sorting clusters them by neuronal source, and cell-type classification associates units with specific cell types based on waveform and firing statistics. While the information required for each task varies (e.g., shape, amplitude, or timing), waveform shape remains a key feature, especially for more advanced analyses such as cell-type classification [ 15 ]– [ 17 ]. As a result, the structure of the spike waveform directly influences which features are retained for downstream interpretation and which can be disregarded as noise or redundancy. Download figure Open in new tab Fig. 1: Action potential signal processing pipeline. Conventional compression techniques typically rely on thresholding or temporal sub-sampling to reduce data volume [ 18 ]–[ 23 ]. While thresholding can be effective for simple decoding tasks, it discards waveform details needed for sorting and classification. Setting optimal thresholds also requires channel-specific tuning, which increases system complexity and power usage. Other approaches propose on-chip spike sorting [ 24 ]–[ 26 ] or compression following digitization [ 27 ]– [ 29 ], but digitizing full-resolution signals from thousands of channels remains a major bottleneck. To avoid overwhelming bandwidth at any stage, compression must begin as close as possible to the analog front-end [ 30 ]. Ideally, this compression would be adaptive—preserving the relevant spike information for a given task while discarding non-informative baseline activity. As shown in Fig. 2 , this requires rethinking the signal processing pipeline to integrate lossy compression at the analog-to-digital (A/D) interface. Download figure Open in new tab Fig. 2: (a) Conventional and (b) proposed on-chip compressive readout framework. In the conventional system architecture ( Fig. 2(a) ), signals from a multiplexed electrode array are first digitized in full by an ADC before undergoing any compression. This design imposes a heavy bandwidth and power burden at the front-end and requires ADCs that are capable of handling continuous high-rate data, including non-informative baseline samples. Compression occurs only after digitization, requiring more processing power and bandwidth. Recent efforts have explored embedding spike sorting in hardware to enable low-latency, on-chip processing. For example, our prior work [ 31 ] presented a 1024-channel spike-sorting chip using event-driven detection and self-organizing map clustering, while Chen et al. [ 32 ] proposed an unsupervised geometry-aware sorting architecture. These approaches show promise, but typically focus on either spatial or temporal features, not both, and remain limited by power constraints. In this work, we present a compressive readout framework that builds on previous analog-to-digital compression architectures [ 33 ], [ 34 ] and incorporates adaptive digital processing tailored to neural signals. As shown in Fig. 2(b) , the system features a multi-stage pipeline that combines a Wired-OR analog-to-digital readout with an on-chip digital core that adaptively re-quantizes, selectively samples, and encodes spike waveforms. These operations are configured by an external module using signal statistics and waveform templates. Using this calibration-driven approach, the hardware applies compression strategies optimized for both data rate and signal fidelity. We evaluate this framework through emulation on 512-channel ex vivo primate retina recordings. Results show that our system can preserve 90% of spike events – an improvement of 8 – 10% over state-of-the-art methods [ 31 ] – while achieving a 1098× total compression ratio over baseline recordings. These findings demonstrate that signal-aware, multi-stage compression can achieve substantial data reduction without sacrificing downstream performance. This paper extends our prior work on Wired-OR compression by introducing and analyzing the full adaptive pipeline. Specifically: We develop a re-quantization strategy based on electrode SNR, eliminating excess quantization levels. We propose a mutual information–based selective sampling method that preserves both spatial and temporal waveform features. We implement a lightweight entropy coding scheme for efficient final-stage compression. We evaluate the pipeline on real 512-channel recordings and analyze performance across spike detection and sorting tasks. The rest of this paper is organized as follows. Section II introduces the multi-stage compression framework, including the Wired-OR analog-to-digital readout and the adaptive digital post compression core. Section III presents simulation and experimental results using 512-channel neural recordings. Section IV discusses hardware implications and comparisons with existing methods. Section V concludes the paper. II. M ulti-stage C ompression F ramework We now present the implementation details of the proposed compressive readout framework, focusing on how compression is distributed across analog and digital domains to minimize bandwidth and power. The proposed system operates in two main phases: calibration and compression. During the Calibration Phase ( Fig. 3a ), a representative subset of recorded neural signals is analyzed offline to extract key statistical and structural features. Characteristic spike waveforms are identified, and relevant metrics such as SNR, firing rates, and salient waveform features are estimated. These metrics guide the selection of optimal compression parameters, which are loaded into the on-chip digital compression core. Tailoring the system parameters to the underlying neural activity in this way ensures that compression decisions, such as quantization levels or sampling intervals, are application-aware and reflective of the unique signal properties observed during calibration. Download figure Open in new tab Fig. 3: On-chip compressive readout framework Once the calibration parameters have been established, the system transitions into the Compression Phase ( Fig. 3b ). Neural signals are continuously acquired, and the first level of compression occurs immediately at the analog front-end through the Wired-OR A/D compressive readout. This mixed-signal architecture exploits the sparsity of neural activity: spike-related voltages, which deviate sharply from baseline and are less frequent, are more likely to be uniquely encoded, while baseline-level voltages, being more frequent, are prone to collision in the row and column readout and naturally suppressed. As a result, the data volume is substantially reduced while preserving nearly all spike-relevant samples, alleviating pressure on downstream processing. Following this mixed-signal compression, a digital post-compression core refines the data further through re-quantization, selective sampling of spike waveforms, and low-overhead on-chip encoding. This multi-stage strategy ensures that each subsequent compression step operates on a smaller data stream, thereby reducing both power consumption and bandwidth requirements without sacrificing essential spike information. A. Wired-OR analog-to-digital compressive readout The Wired-OR analog-to-digital (A/D) compressive readout [ 33 ]–[ 35 ] (as shown in Fig. 2(b) ) serves as the first stage of the proposed multi-stage compression framework, directly reducing data at the A/D interface. This hardware-efficient and event-driven approach acquires neural data while simultaneously performing data compression and channel multiplexing. Each pixel samples the input voltage and encodes it into a pulse position based on a globally distributed ramp. Pulses from multiple pixels are merged on shared wires using Wired-OR circuitry. If only one pixel fires at a given time step, both its location and voltage level can be uniquely decoded (as shown in Fig. 4(b) ). If multiple pulses coincide—i.e., a collision occurs—the data is discarded, achieving compression by exploiting signal sparsity (see Fig. 4(c-d) . This technique exploits the sparsity and diversity of neural signals to minimize redundant sampling and digitization while maintaining the key features required for downstream analysis. Download figure Open in new tab Fig. 4: Wired-OR readout concept [ 34 ]. (a) A snippet of action potential waveform seen on different electrodes. (b) Conversion of voltage to pulse position and collision-free readout of one pixel. (c) A collision between two pixels. (d) Massive collision across the array at the baseline level. (e) Diagonal wiring conceptual drawing. (f) Interleaving wiring. Unlike conventional A/D architectures that sample continuously across all channels, the Wired-OR readout refrains mostly spike-related events, significantly reducing data rates and computational overhead. This spike-driven encoding process ensures that only the most relevant neural activity is retained, making the system highly scalable and power-efficient for brain-machine interface applications. Due to their temporal and spatial sparsity, spike-related samples are more likely to be unique, they are retained, while baseline-level voltages—which are more frequent and thus prone to collision—are naturally filtered out. Wiring strategies such as diagonal [ 34 ] and interleaved [ 33 ] layouts can help resolve small collisions and recover more spike information, also shown in Fig. 4(e-f) . By pre-compressing neural data at the analog interface, the Wired-OR readout reduces the data bandwidth burden on subsequent processing stages by 15 ∼ 50 ×, depending on the wiring strategy and neural firing rate. This efficiency was validated in ex vivo experiments using a taped-out chip, where compression rates ranged from 111.2× (single-wire) to 38.8× (four-wire) configurations [ 35 ]. The digital compression core, detailed in Section II-B, further refines the signal through re-quantization, selective sampling, and on-chip encoding, ensuring optimal balance between compression efficiency and neural signal fidelity. B. Digital compression core The output of the Wired-OR readout stage is a sparse set of events, each represented by its row and column address along with the amplitude (encoded in ADC counts). These elements - spatial address and amplitude - form the input to the post compression core, which aims to further reduce data size by keeping critical information available for downstream analyses. The digital core first treats address and amplitude data as separate streams, optimizing compression strategies tailored to each. For the amplitude, we explore re-quantization to a lower resolution, leveraging the insight that many spikes can be accurately reconstructed at a coarser bit depth. In addition, selective sampling is applied to discard redundant or low-information spike samples. The remaining critical samples are then passed through a lightweight entropy coding stage inspired by Huffman coding. Instead of performing full encoding in hardware, we use a precomputed lookup table that approximates optimal codes based on amplitude and spatial statistics gathered during the calibration phase. This hybrid scheme achieves high compression ratios while maintaining hardware simplicity and preserving spike timing and shape characteristics essential for downstream decoding and sorting. 1) Re-quantization State-of-the-art neural interface systems are equipped with ADCs of 10-16 bit resolution [ 10 ], [ 12 ], [ 36 ]–[ 39 ] driven by multiple considerations such as signal drift, motion artifacts, and dynamic range. Although prior work [ 19 ] suggests that action potential data can be requantized to about the SNR number of bits without significantly degrading decoding performance, our results indicate that the required re-quantization resolution can often be reduced even further. In an electrode of a MEA, the measured voltage V ( z, t ) can be modeled as [ 40 ]: Here, z denotes the electrode location, t is the continuous time, and k indexes distinct neurons or clusters. Each cluster σ ( k ) has an associated waveform template A σ ( k ) , shifted by the spike time t k and scaled by the spike amplitude x ( k ). The term N ( t ) captures additive noise present in the recording. For a spike event, the SNR is approximated by [ 36 ]: The amplitude of the spike peak-to-peak ( V peak-peak amplitude ) is determined by identifying the electrode with the most significant peak-to-peak difference for each spike. The noise level ( V σ,channel ) is calculated as the median absolute deviation when no action potential is detected on the electrode. Intuitively speaking, if we look at the recording of spikes on a certain electrode, the observed voltage level is the summation of the underlying noise-free signal and noise that can be modeled as a Gaussian distribution (see Fig. 5 ). When the electrode records spikes only up to a certain SNR max,electrode (following the definition of Eq. 2 ), the quantizer only needs to differentiate N steps quantization levels, where: Download figure Open in new tab Fig. 5: Empirical demonstration of additive Gaussian noise in extracellular action potential recording. (a) Average spike waveform of a given cell-electrode pair. (b) Real, measured voltage distribution at a specific sample point across multiple spike occurrences because finer resolution would merely differentiate noise. Hence, the minimum bit depth required is: From a theoretical perspective, this interplay between universal filtering and lossy compression aligns with established results in information theory and signal processing. The foundational works of [ 41 ]–[ 43 ] have characterized noise filtering via data compression and indirect rate-distortion problems, respectively, underscoring the effectiveness of compression-based denoising. Additionally, the principles articulated in [ 44 ], [ 45 ] reveal that compressing noisy data can inherently facilitate noise reduction when the compression is optimized for a distortion tuned to the level and characteristics of the noise. Practical manifestations of this approach are extensively discussed in prior research [ 44 ], [ 46 ], reinforcing the viability of compression-driven filtering methods in real-world scenarios. Further justification for our use of uniform scalar quantization followed by universal filtering arises from both theory and practice. It is well-established that, under squared-error distortion and in the presence of additive Gaussian noise, uniform scalar quantization achieves near-optimal performance [ 47 ]. This setting applies directly to neural signals, which are commonly modeled as clean spike waveforms corrupted by zero-mean Gaussian noise (see Fig. 6 ). Prior work [ 47 ] has shown that quantizing the noisy signal using a quantizer designed for the clean source yields distortion nearly matching that of the optimal scheme. Thus, uniform scalar quantization not only simplifies implementation by obviating the need for optimized quantizer thresholds but also incurs minimal performance loss 1 . Download figure Open in new tab Fig. 6: Normalized mean square error (NMSE) versus requantization resolution, where the x-axis is expressed as the ratio of each electrode’s chosen bit depth to B min . An experiment of requantizing the action potential recording from an originally 12-bit quantized dataset is conducted. The requantization resolution for each electrode in three 512-channel primate ex vivo retina recording datasets is normalized to the proposed B min defined by Eq. 4 . As shown in Fig. 6 , the green curve shows how NMSE 2 decreases sharply as the bit depth approaches or exceeds B min , indicating that the requantization error can be substantially mitigated by allocating just enough bits to match the electrode’s maximum SNR-based bits. The shaded region depicts the variability across different channels, illustrating the NMSE is consistently small across electrodes with a requantization resolution of B min . We also studied the average spike waveform distortion introduced by re-quantizing with B min bits resolution across different cell-electrode pairs where spikes have a wide range of SNR. Fig. 7 shows that for SNR ≥ 5, less than 1% of NMSE is introduced by re-quantization. Download figure Open in new tab Fig. 7: Normalized Mean Square Error (NMSE) versus spike SNR for re-quantization at B min bits. During the calibration phase ( Fig. 3a ), a single sweep across all channels is performed to extract signal statistics used to estimate the SNR and determine B min for each channel. In this mode, full waveforms from each electrode are sampled and digitized without thresholding or compression, enabling accurate baseline noise characterization. Because SNR can vary over time due to factors such as electrode impedance changes, tissue response, or other nonstationary effects, the system includes a recalibration mechanism. It periodically re-enters calibration mode to update noise estimates and recompute B min . The re-calibration interval is empirically determined based on the application, as different recording modalities (e.g., retinal vs. intracortical) exhibit different SNR dynamics. This adaptive calibration ensures that the quantizer remains well-tuned to current signal conditions, preserving both compression efficiency and signal fidelity. 2) Selective sampling Following the compressive Wired-OR readout and digital re-quantization, further compression gains can be realized by reducing the number of time samples retained for each spiking event. Rather than transmitting all of the Wired-OR outputs, we identify a small set of time points that carry the most discriminative information across neural units. This selective sampling process eliminates redundant or less-informative samples, preserving only those samples essential for downstream tasks such as spike sorting or neural decoding. Selective sampling is configured during the Calibration Phase, where informative samples are identified off-chip based on statistical differences across spike waveforms. The selected sample indices are then programmed into the on-chip digital core to enable compact spike representation during realtime data streaming. Our approach is motivated by information-theoretic principles, yet implemented using lightweight operations suited to streaming. The procedure unfolds in three stages: an initial unsupervised clustering, mutual information-based sample ranking, and optional online refinement. a) Unsupervised Clustering Initialization We first start with performing an initial unsupervised clustering on the full Wired-OR spike waveforms. Here we use k-means clustering (with k set to a conservative number of 5, empirically chosen). This provides provisional cluster assignments without any feature selection bias. Given spike waveforms of length 61 3 (each approximated as a true spike shape plus Gaussian noise), we need to find which time sample indices are most informative for distinguishing unknown clusters (typically 3–5 clusters). In an unsupervised scenario (no prior labels), we seek statistically sound, efficient feature-ranking methods that highlight time points contributing most to cluster separation. We focus on global importance across all clusters seen on the electrode (not per-cluster specific) and avoid heavy machine-learning models. Below, we outline the principle of our method. We also discuss their computational efficiency and how they can fit into a real-time feature selection pipeline. b) Information-Theoretic Sample Selection While mutual information between each sample requantized value X t and the unit identity C is an ideal theoretical measure of importance, its computation is costly and ill-suited to real-time or low-power implementations. We therefore approximate this metric under the Gaussian noise model (see Eq. 1 ), where mutual information simplifies to a ratio of variances: with as the mean waveform value at time t for cluster c , and as the within-cluster variance. This discriminability score captures the same intuition: samples with high inter-unit variability and low intra-unit noise are more informative for separating spikes from different sources. We compute this score for each time index and retain only the top 3–5 samples with the highest discriminability, forming a compact, information-rich representation of each spike. While we do not claim this number to be theoretically optimal, it was found to be empirically sufficient across multiple datasets. This choice reflects a practical tradeoff between reducing input dimensionality and preserving clustering performance. c) Refined Clustering and Online Update After feature selection, clustering is rerun using the reduced feature vectors. This not only accelerates computation but can improve accuracy by suppressing noisy and less-informative samples. To support long-term use in dynamic recording environments, the discriminability scores can be updated incrementally as a subset of new spikes, with all Wired-OR spike samples, are periodically transmitted. We maintain running estimates of per-cluster means and variances at each time point, enabling online updates to feature rankings with minimal overhead. These statistics converge quickly and require only O ( k ) computation per spike, allowing the system to adapt to changing neural conditions while maintaining compression efficiency. 3. On-chip encoding To efficiently encode remaining samples, we implement a Huffman-inspired entropy coder using a precomputed lookup table. During the system’s calibration phase, histograms of address and amplitude values are collected and used to build codebooks optimized for the neural signal distribution. The codebook is refreshed at each recalibration, keeping the coding efficiency near the true entropy of the evolving signal distribution. Instead of constructing Huffman trees at runtime, which is expensive in both time and silicon area, we generate static Huffman tables offline and store them on-chip. These tables translate each sample’s spatial and amplitude value into a fixed-length or variable-length code via a simple lookup. This method eliminates the need for real-time histogramming or adaptive coding logic, enabling ultra-low-power, high-speed compression. The channel coordinates and spike amplitude exhibit skewed distributions due to structured neural activity, allowing Huffman coding to achieve substantial gains. Coupled with selective sampling and re-quantization, this final stage completes the multi-step pipeline from raw events to fully compressed and hardware-ready output. III. S imulation and R esults To evaluate the performance of our multi-stage compression framework, we conduct experiments on 512-channel ex vivo primate retina datasets recorded at 20kHz. These datasets are processed in software to emulate the full pipeline, including Wired-OR analog-to-digital compressive readout, requantization, selective sampling, and entropy coding. Each stage is designed to reduce the total data volume while preserving critical information for downstream spike processing. Parameter recalibration was performed every 10 minutes, which was sufficient to maintain stable compression performance over time. We further benchmark our framework against state-of-the-art on-chip spike sorters [ 25 ], [ 31 ] using a publicly available multi-channel Neuropixels dataset [ 48 ]. Fig. 8 provides a detailed example of the full pipeline applied to one channel and its neighboring electrodes. The top row (see Fig. 8 (a–c) ) shows the extracted electrical images (EIs 4 ) of units recorded on electrode 501 in the array, initial spike templates obtained through unsupervised k-means clustering, and the panel (c) shows the refined templates obtained after re-clustering using only the discriminative samples selected during the selective sampling phase, as described in the refined clustering and online update stage. This step enhances both accuracy and efficiency by removing noisy or redundant dimensions from the feature space. The bottom row highlights the discriminability scores computed for two adjacent electrodes: Fig. 8 (d) for electrode 501 and Fig. 8 (e) for electrode 502. Notably, in this example, electrode 502—despite not being the primary site of the spike—exhibits more peaked and informative samples for class separation. This underscores the value of spatially informed selective sampling, where nearby electrodes can provide higher-discriminability features than the electrode with the largest spike amplitude. Download figure Open in new tab Fig. 8: An example of processing through electrode 501 in simulation. (a) Ground truth electrical image (EI) of the cells on electrode 501. (b) Initialized templates by clustering the detected and aligned events. (c) Refined and updated templates after iterating through the dataset. (d) Discriminability score of electrode 501 given the collected statistics after the calibration phase. (e) Discriminability score of electrode 502, which is near 501. (f) The matching matrix of the final clustering results and ground truth labels (different cells with the largest spike on electrode 501 and “garbage”). Fig. 8 (f) shows a spike matching matrix between the clustering output from compressed data and ground truth unit labels. Clusters are aligned based on their dominant electrode. To address duplicate clusters across nearby electrodes, we apply a merging procedure based on the Hierarchical Adaptive Means (HAM) clustering strategy [ 49 ], which compares intercluster distances against a noise-informed threshold and consolidates redundant units in a hardware-efficient manner. The resulting average matching rate in this example is 92.35%. To assess generalization beyond a single electrode, we evaluated the percentage of spikes preserved across the entire dataset. Fig. 9 summarizes spike recall as a function of signal-to-noise ratio (SNR) for different cell-electrode pair in the dataset. We compare two representative schemes: (1) only compress with Wired-OR a 1-wire 6-bit ramp configuration, achieving a compression ratio (CR) of 274.35, and (2) the full compression pipeline with a 10-bit ramp, eight interleaved wiring Wired-OR configuration, and the addition of digital post-compression, resulting in a total CR of 1098.23. Download figure Open in new tab Fig. 9: Spike recall for ExVivo-1, across varying SNRs. The full pipeline achieves higher recall at higher compression. As shown in Fig. 9 , both configurations achieve high spike recall across a broad SNR range, with the full compression pipeline consistently outperforming the baseline Wired-OR-only setup. Notably, even under aggressive compression, spike recall exceeds 95% for moderate SNR values (SNR ≥ 8) and approaches 100% for higher-quality signals. The shaded region represents variability across electrodes for different SNR ranges, reflecting electrode-specific SNRs. These results demonstrate that combining Wired-OR read-out with post-compression stages—including re-quantization, selective sampling, and Huffman-inspired encoding—can significantly increase compression efficiency without compromising spike detection fidelity. We next evaluate how our proposed compression framework compares against other spike compression and sorting approaches [ 31 ] on the same 512-channel ex vivo primate retina datasets (referred to hereafter as ExVivo-1 and ExVivo-2) and Neuropixel dataset [ 48 ]. These datasets are chosen as representative cases of neural recordings with varying SNR distributions, which significantly affect compression performance—particularly in the re-quantization and entropy coding stages. Specifically, ExVivo-1 has a mean SNR of 16.16 with a standard deviation of 6.99, while ExVivo-2 exhibits a mean SNR of 12.64 with a narrower spread (standard deviation of 6.06). Fig. 10 shows the spike clustering accuracy across three datasets using our method (with information-theoretic selective sampling), the spatial spike sorting method reported from [ 31 ], and a temporal spike sorting baseline. Download figure Open in new tab Fig. 10: Spike clustering accuracy across two retina datasets and one public Neuropixel dataset comparing three methods: our work using discriminability-driven selective sampling, the spatial spike sorting method proposed in [ 31 ], and a temporal single-electrode baseline. Our method achieves the highest average accuracy and more consistent performance across units. The temporal method performs spike sorting independently on each electrode by using all Wired-OR spike samples and linearly interpolating missing ones before classification, following the methods that we previously proposed in [ 50 ]. The spatial method, as proposed in [ 31 ], combines spikes across electrodes and leverages spatial correlation for clustering using a self-organizing map approach. While the spatial method shows strong performance, it does not report the variability of sorting accuracy across units. Our method not only achieves the highest mean clustering accuracy in both datasets (90.0% for ExVivo-1, 92.6% for ExVivo-2 and 99.4% for Neuropixel data), but also shows lower variability compared to using only temporal features, indicating robust performance across all neural units. To understand how each stage of the compression pipeline contributes to overall compression, we analyze the normalized data size after each component. As shown in Fig. 11 , the Wired-OR stage alone achieves 35× and 19× compression on ExVivo-1 and ExVivo-2, respectively. With selective sampling and re-quantization, an additional 11× reduction is observed, followed by a further 3× from Huffman-inspired entropy coding. The overall compression rate exceeds 1000×, with acceptable loss in spike fidelity. In the Neuropixels dataset [ 48 ], the lower SNR (∼ 7) and long-shank electrode architecture result in significantly greater compression gains—achieving 358 ×from re-quantization and selective sampling, and an additional 4.8× from Huffman-inspired coding. Notably, the compressibility in the selective sampling stage depends on the number of retained samples; in this analysis, we select the top 5 most discriminative time points per spiking event on an electrode and its neighboring electrodes. Download figure Open in new tab Fig. 11: Compression rate comparison across pipeline stages for three datasets. Starting from raw data, the Wired-OR stage provides the first major reduction. Re-quantization and selective sampling yield another 11 ×, followed by Huffman coding with 2.5× further reduction. Each dataset retains 5 informative samples per spike. IV D iscussion A. Implementation and benchmarking of digital compression core Fig. 12 shows the proposed hardware architecture of the digital compression core that follows the Wired-OR analog-to-digital compressive readout. The system is divided into three main stages: (1) re-quantization, (2) discriminability-driven feature selection, and (3) approximate entropy coding via a lightweight Huffman encoder. Download figure Open in new tab Fig. 12: Hardware architecture of the proposed digital compression core. The system receives sparse spike samples from the Wired-OR stage and performs re-quantization, sample selection, and Huffman-style encoding. Incoming spike events from the Wired-OR stage are represented as sparse triplets: row address, column address, and ADC count. These are first fed into the “Re-quantization and Feature Selection Unit”, which handles both amplitude compression and sample reduction. In the re-quantization block, a programmable lookup table (LUT) determines the quantization resolution ( B o → B rq , where B o is the length of the Wired-OR amplitude output, B r q is the reduced bit width after re-quantization) based on the maximum SNR per channel. A simple shift-and-truncate operation compresses the amplitude values. This enables amplitude-specific precision tuning across electrodes with negligible computation overhead. For sample selection, incoming spike waveforms are buffered in a FIFO and processed using a sliding window. A lightweight argmax engine computes the spike peak timing, and the most informative N samples are selected. The selection is driven by a second LUT that is trained offline during a calibration phase. Selected samples are forwarded via an asynchronous FIFO to the encoder. Finally, the data passes through an on-chip Huffman encoder that uses a fixed codebook precomputed during the calibration phase. The encoder maps frequent sample patterns to shorter binary representations using a lookup table, and a bit packer serializes the output. This design enables approximate entropy-coded compression with low hardware complexity and avoids the need for runtime codebook updates. To assess implementation feasibility, we provide an estimated breakdown of complexity and energy consumption for the digital compression core. Table I summarizes gate count 5 and energy cost per spike processed for each major module, based on standard logic primitives and published energy models for 28nm CMOS [ 51 ], [ 52 ]. Gate counts are estimated by decomposing each module into standard digital building blocks such as flip-flops, adders, comparators, and control logic, using representative gate-equivalent costs derived from synthesis reports and textbook implementations [ 53 ], [ 54 ]. View this table: View inline View popup Download powerpoint Table I. Estimated Memory, Gate Count, and Energy per Re-quantization and Feature Selection Unit (28nm LP) The entire post-compression system is designed for shared processing across channels. A single Requantization & Feature Selection Unit is time-multiplexed across multiple channels. Based on spike event rates modeled empirically, only 32 such units are required to support a 1024-channel array. This architecture reduces the power and area overhead compared to per-channel buffering, while preserving the low-memory footprint that is a key advantage of the original Wired-OR design. Including a conservative memory estimation of the Huffman lookup table of 4KB 6 , the total on-chip memory required for the post-compression stage across 1024 channels is approximately 4.92 KB. The entire logic complexity is well within feasible bounds for modern implantable SoCs. a) Power Savings Assuming a baseline wireless transmission energy of 72.9 pJ/bit [ 55 ], the energy cost per bit after compression is broken down as follows 7 : 0.066 pJ/b from re-quantization and selection, from Huffman encoding [ 56 ], from transmission. Total energy per transmitted bit: 2.296 pJ/ compared to transmitting all of the original Wired-OR outputs, this corresponds to an additional 31.75× power reduction. This analysis confirms that the post-compression stage delivers significant energy and bandwidth benefits with low hardware overhead, making it highly suitable for implantable or portable neural interface systems. B. Comparison with Prior Work Table II compares the proposed compression framework to previous neural signal compression and spike sorting approaches. Compared to conventional thresholding-based spike detection [ 21 ], which incurs low overhead but discards wave-form detail, we maintain full waveform shape and achieve 3–10× higher compression compared to this reported thresholding approach. While ML-based autoencoders [ 27 ], [ 29 ] can offer similar compression ratios, they require training, inference, and high memory resources—making them less suitable for ultra-low-power edge systems. On-chip spike sorting techniques [ 25 ], [ 31 ] extract spike times and unit labels in hardware, often discarding waveform information, and typically rely on fixed temporal or spatial features. In contrast, our system supports tunable feature selection via an information-theoretic approach and retains waveform fidelity. Among all methods surveyed, Wired-OR is the only one to support high compression, waveform preservation, and scalable implementation without requiring large memory, floating-point operations, or machine learning. This makes it particularly well suited for large-scale neural recording systems targeting real-time closed-loop applications. View this table: View inline View popup Download powerpoint Table II. Comparison With Prior Work V. C onclusion We have presented an end-to-end framework for adaptive compressive neural signal acquisition and digital compression. Building on our prior work on Wired-OR analog-to-digital compressive readout [ 33 ], [ 34 ], this paper introduces a post-compression architecture that combines re-quantization, selective sampling based on spike discriminability, and hardware-friendly entropy encoding. Together, these components form a scalable system that dramatically reduces data rates while preserving spike information critical for more fine-tuned spike sorting algorithms. Evaluated on 512-channel ex vivo primate retina recordings, the system achieves over 1000× compression while preserving 90% spike sorting accuracy. The design balances spatial and temporal feature retention with hardware efficiency, and supports runtime adaptation to varying signal conditions. VI. B iography S ection Download figure Open in new tab Pumiao Yan received the B.Sc. degree in Electrical and Computer Engineering from Cornell University in 2018, and the M.S. and Ph.D. degrees in Electrical Engineering from Stanford University in 2020 and 2025, respectively. She was a Seth A. Ritch Bio-X Graduate Student Fellow during her Ph.D. studies. Her research focuses on algorithm-hardware co-design and signal processing for analog-to-digital compression hardware architectures for neural interfaces. Download figure Open in new tab Dante G. Muratore is an assistant professor in the Microelectronics department at the Delft University of Technology. He received the B.Sc. degree and the M.Sc. degree in Electrical Engineering from Politecnico of Turin in 2012 and 2013, respectively. He received the Ph.D. degree in Microelectronics from the University of Pavia in 2017 in the Integrated Microsystems Lab. From 2015 to 2016, he was a Visiting Scholar at Microsystems Technology labs at the Massachusetts Institute of Technology. From 2016 to 2020, he was a Postdoctoral Fellow at Stanford University. He is the recipient of the Wu Tsai Neurosciences Institute Interdisciplinary Scholar Award. His research focuses on hardware and system solutions for high-bandwidth brain-machine interfaces that can interact with the nervous system at natural resolution. Download figure Open in new tab E. J. Chichilnisky is the John R. Adler Professor of Neurosurgery, and Professor of Ophthalmology, at Stanford University, where he has worked since 2013. Previously, he worked at the Salk Institute for Biological Studies for 15 years. He received his B.A. in Mathematics from Princeton University, and his M.S. in mathematics and Ph.D. in neuroscience from Stanford University. His research has focused on understanding the spatiotemporal patterns of electrical activity in the retina that convey visual information to the brain, and their origins in retinal circuitry, using large-scale multielectrode recordings. His ongoing work now focuses on using basic science knowledge along with electrical stimulation to develop a novel high-fidelity artificial retina for treating incurable blindness. He is the recipient of an Alfred P. Sloan Research Fellowship, a McKnight Scholar Award, a McKnight Technological Innovation in Neuroscience Award, and a Research to Prevent Blindness Stein Innovation Award. Download figure Open in new tab Boris Murmann (Fellow, IEEE) received the Dipl.-Ing. (FH) degree in communications engineering from Fachhochschule Dieburg, Dieburg, Germany, in 1994, the M.S. degree in electrical engineering from Santa Clara University, Santa Clara, CA, USA, in 1999, and the Ph.D. degree in electrical engineering from the University of California at Berkeley, Berkeley, CA, USA, in 2003. From 1994 to 1997, he was with Neutron Mikroelektronik GmbH, Hanau, Germany, where he was involved in the development of low-power and smart-power application-specific integrated circuits (ASICs) in automotive CMOS technology. From 2004 to 2023, he was with the Department of Electrical Engineering, Stanford University, Stanford, CA, USA, where he served as an Assistant Professor, an Associate Professor, and a Full Professor. He is currently with the Department of Electrical and Computer Engineering, University of Hawai’i at Mānoa, Honolulu, HI, USA. His research interests are in the area of mixed-signal integrated circuit design, including sensor interfaces, A/D and D/A conversion, high-speed communication links, embedded machine learning (tinyML), electronic design automation, as well as open-source chip design. Dr. Murmann was a co-recipient of the Best Student Paper Award at the Very Large-Scale Integration Circuits Symposium in 2008 and 2021 and the Best Invited Paper Award at the IEEE Custom Integrated Circuits Conference (CICC) in 2008. He received the Agilent Early Career Professor Award in 2009, the Friedrich Wilhelm Bessel Research Award in 2012, the SIA-SRC University Researcher Award for lifetime research contributions to the U.S. semiconductor industry in 2021, and the SRC Aristotle Award for contributions to teaching and mentorship in 2024. He was the 2017 Program Chair of the IEEE International Solid-State Circuits Conference (ISSCC) and the 2023 General Co-Chair of the IEEE International Symposium on Circuits and Systems (ISCAS). He currently serves as the Editor-in-Chief of the IEEE Journal of Solid-State Circuits. Download figure Open in new tab Tsachy weissman (Fellow, IEEE), is the Robert and Barbara Kleist Professor of Electrical Engineering at Stanford University since 2003, researching and teaching the science of informa-tion, with applications spanning genomics, neuroscience, and technology. He has been serving on editorial boards for scientific journals, technical advisory boards in industry, and as the Founding Director of the Stanford Compression Forum. His recent projects include the SHTEM summer internship program for high schoolers, the starling initiative for data integrity, and stagecast, a low-latency video platform allowing actors and singers to perform together in real-time while geographically distributed. He has received multiple awards for his research and teaching, including Best Paper Awards from the IEEE Information Theory and Communications Societies, while his students received best student authored paper awards at the top conferences of their areas of scholarship. He has prototyped guardant health’s first algorithms for early detection of cancer from blood tests and has recently co-founded and sold compressable to Amazon, reducing humanity’s cloud storage footprint. His favorite gig to date was advising the HBO show “Silicon Valley.” Footnotes (e-mail: pumiaoy{at}stanford.edu , tsachy{at}stanford.edu ). (e-mail: d.g.muratore{at}tudelft.nl ). (e-mail: bmurmann{at}hawaii.edu ) (e-mail: ej{at}stanford.edu ). This project was supported in part by Stanford’s Wu Tsai Neurosciences Institute. P. Y. was supported by a Stanford Bio-X SIGF fellowship. ↵ 1 Intuitively, the observed voltage at a given electrode is the superposition of the underlying spike signal and Gaussian noise. In such settings, quantization optimized for the clean signal often performs nearly as well as one optimized for the noisy observation. See [ 47 ] for theoretical discussion. ↵ 2 Here the mean square error is normalized to the spike peak to peak amplitude Vpeak−peak amplitude . ↵ 3 This is an empirical number dependent on the sampling rate of the system. ↵ 4 Electrical images are generated by averaging spike waveforms to capture the characteristic signature of each cell–electrode pair. ↵ 5 For each potential spike, we consider the center electrode and its 6 adjacent electrodes and buffer 30 samples per electrode. ↵ 6 A conservative 4KB estimate accounts for two 1024-entry Huffman lookup tables of the channel addresses and recorded quantized ADC amplitudes. ↵ 7 Here, we use the compression ratio results from the ExVivo-2 simulation as a representative example. R eferences [1]. ↵ Y. Wang , X. Yang , X. Zhang , Y. Wang , and W. Pei , “ Implantable intracortical microelectrodes: reviewing the present with a focus on the future ,” Microsyst Nanoeng , vol. 9 , p. 7 , Jan . 2023 . OpenUrl PubMed [2]. ↵ T. Matsuo , K. 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