Hardware-Software Concealing of Secret Key and Enhancement of Pipelined Advanced Encryption Standard Cryptographic Core via Reconfigurable Devices for Hybrid Fast Connection Oriented Networks

Hardware-Software Concealing of Secret Key and Enhancement of Pipelined Advanced Encryption Standard Cryptographic Core via Reconfigurable Devices for Hybrid Fast Connection Oriented Networks | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Article Hardware-Software Concealing of Secret Key and Enhancement of Pipelined Advanced Encryption Standard Cryptographic Core via Reconfigurable Devices for Hybrid Fast Connection Oriented Networks Omer Alkelany This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-9277766/v1 This work is licensed under a CC BY 4.0 License Status: Under Review Version 1 posted 6 You are reading this latest preprint version Abstract Connection-oriented networks are vastly used in Local Area Networks, which typically involve insecure segments. Cryptography is a crucial technique, to protect confidentiality. Advanced Encryption Standard (AES) has been extensively investigated thoroughly, and recently for its 256-bit key implementations. A given pipelined two-cycle AES-256-bit key core is selected for further analysis, and evaluation. Then, a single clock was designed and implemented. Experimental results show an encryption throughput of 12.8 Gb/s, with an FPGA utilization of only 9% Cyclone V SX SoC 5CSXFC6D6F31C6N. So, a speed up the encryption rate by 7 times is reported, compared to recent results, both operating at maximum clock frequencies of 96 and 100 MHz respectively. Even though VLSI implementations are much faster, but they don’t allow for concealing the secret key on the chip fabric. Consequently, two desktop applications using Microsoft Visual C were developed to demonstrate the application in Gigabit Ethernet connections, and hardware-software concealment of the secret key. These applications were in hybrid TCP/IP networks which has a physically secure domain, and insecure domains. The network experiment demonstrates a network maximum utilization of 90Mb/s, of a 100 Mb/s Ethernet. Therefore, the designed core can be used in faster connection-oriented networks effectively. Physical sciences/Engineering Physical sciences/Mathematics and computing Computer aided design logic design Reconfigurable devices hardware software codesign Concealing secret key Full Text Additional Declarations No competing interests reported. Cite Share Download PDF Status: Under Review Version 1 posted Reviewers agreed at journal 29 Apr, 2026 Reviewers invited by journal 27 Apr, 2026 Editor invited by journal 10 Apr, 2026 Editor assigned by journal 01 Apr, 2026 Submission checks completed at journal 01 Apr, 2026 First submitted to journal 31 Mar, 2026 You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-9277766","acceptedTermsAndConditions":true,"allowDirectSubmit":false,"archivedVersions":[],"articleType":"Article","associatedPublications":[],"authors":[{"id":634682598,"identity":"a0ce81ca-8b47-4cb8-8aff-018fe938bda0","order_by":0,"name":"Omer Alkelany","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAABAElEQVRIiWNgGAWjYFAC5mYGhgIgzd4DE0kgpIURqMUASPOcIVmLRA6RWvjZDzYbfDCwyzO4+fbg48q2OqBIjgHDh1+4tUj2JDYnzjBILja4nZdseLbtMFDkjQHjzD7cWgwOJDYf5jFgTtxwO8dMsrHtAIPBjRwDZt4ePFrOP2w+/MegPnHDzTMgLXUM9iAtf/FpuZHYnMxgcDhxww0ekBZmBgMJoBaGH3j8MuNhs2GPwfHEmWdyjA0bzh3mkTjzrOBgbwNuLfz8yYclflRUJ/YdP2P4sKGsTo6/PXnjgx9/cGuBA4UDEJoHRBxgbCNCizyqU4ixZRSMglEwCkYKAAAGp1bVHUchFwAAAABJRU5ErkJggg==","orcid":"","institution":"Horus University","correspondingAuthor":true,"prefix":"","firstName":"Omer","middleName":"","lastName":"Alkelany","suffix":""}],"badges":[],"createdAt":"2026-03-31 09:38:07","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-9277766/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-9277766/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":108572313,"identity":"11921fa2-4a0a-4c7e-90d0-892c8b131e5a","added_by":"auto","created_at":"2026-05-06 06:26:46","extension":"pdf","order_by":1,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":1122233,"visible":true,"origin":"","legend":"","description":"","filename":"revtoSciReps.pdf","url":"https://assets-eu.researchsquare.com/files/rs-9277766/v1_covered_431f5eef-227b-40d2-a671-6f8c5004dc60.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"Hardware-Software Concealing of Secret Key and Enhancement of Pipelined Advanced Encryption Standard Cryptographic Core via Reconfigurable Devices for Hybrid Fast Connection Oriented Networks","fulltext":[],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":false,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":false,"highlight":"","institution":"","isAcceptedByJournal":false,"isAuthorSuppliedPdf":true,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":true,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"scientific-reports","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":false,"externalIdentity":"scirep","sideBox":"Learn more about [Scientific Reports](http://www.nature.com/srep/)","snPcode":"","submissionUrl":"","title":"Scientific Reports","twitterHandle":"","acdcEnabled":true,"dfaEnabled":true,"editorialSystem":"stoa","reportingPortfolio":"Scientific Reports","inReviewEnabled":true,"inReviewRevisionsEnabled":true},"keywords":"Computer aided design, logic design, Reconfigurable devices, hardware software codesign, Concealing secret key","lastPublishedDoi":"10.21203/rs.3.rs-9277766/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-9277766/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eConnection-oriented networks are vastly used in Local Area Networks, which typically involve insecure segments. Cryptography is a crucial technique, to protect confidentiality. Advanced Encryption Standard (AES) has been extensively investigated thoroughly, and recently for its 256-bit key implementations. A given pipelined two-cycle AES-256-bit key core is selected for further analysis, and evaluation. Then, a single clock was designed and implemented. Experimental results show an encryption throughput of 12.8 Gb/s, with an FPGA utilization of only 9% Cyclone V SX SoC 5CSXFC6D6F31C6N. So, a speed up the encryption rate by 7 times is reported, compared to recent results, both operating at maximum clock frequencies of 96 and 100 MHz respectively. Even though VLSI implementations are much faster, but they don\u0026rsquo;t allow for concealing the secret key on the chip fabric. Consequently, two desktop applications using Microsoft Visual C were developed to demonstrate the application in Gigabit Ethernet connections, and hardware-software concealment of the secret key. These applications were in hybrid TCP/IP networks which has a physically secure domain, and insecure domains. The network experiment demonstrates a network maximum utilization of 90Mb/s, of a 100 Mb/s Ethernet. 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