Design and Comparison of low power fault tolerant logic circuit using QCA nano Technology

Design and Comparison of low power fault tolerant logic circuit using QCA nano Technology | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Design and Comparison of low power fault tolerant logic circuit using QCA nano Technology Ami Patel, Vrushank Shah, Dipti Khurge This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-6461225/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract Quantum Dot Cellular Automata (QCA) is a promising alternative to traditional CMOS technologies for future nanocomputing due to its potential for ultra-low power consumption and high-density integration. However, the practical implementation of QCA circuits is challenged by fabrication defects, environmental noise, and the need for fault tolerance, particularly in larger-scale systems. This work examines various defects that may arise in majority gates and subsequently presents a comparative analysis of fault-tolerant majority gates, considering the number of device cells, types of defects, and levels of fault tolerance achieved. QCA Circuits are simulated on the QCA Designer tool version 2.0.3. This paper concentrates on the examination of single and double missing cell defects. The proposed majority gate is analyzed for single and double missing cell defects and also the the full adder is designed using the proposed MG. Quantum dot Cellular Automata Fault tolerance majority gate Full Text Additional Declarations No competing interests reported. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-6461225","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":443700796,"identity":"a2041e46-14bb-4dea-ac55-1fc035a92afb","order_by":0,"name":"Ami Patel","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAABD0lEQVRIiWNgGAWjYFACxgYgIQFlsEkw8IMEEwoIa5GAa5EE8RMMCNslAaHYGBgMDoAYeLTwTzvcwPAzx6KOQSK57cOPMgt54/OrEz88MGCQ5xc7gN3024kNjL3bgA6TSGye2XNOwnDbjbebJYAOM5w5OwG7NUAtDLwgLTwHmxl42yQYt904uwGkJcHgNnYt8iBb/kK1MP5tk7DfPOPs5h/4tBgAtTCDbWFvbGYG2pK4gR/oTnxaDIFaDstuk5BsA2mROSeRPOMG7zaLBAMJnH6Ru53+8OHbbXX8/MzsjxnflNXZ9vef3XzzR4WNPL80Du8DwQEQwQbnSoBVSuBUjgXwHyBF9SgYBaNgFIwAAAA1NFs5N7EsPQAAAABJRU5ErkJggg==","orcid":"","institution":"L J Institute of Engineering and Technology","correspondingAuthor":true,"prefix":"","firstName":"Ami","middleName":"","lastName":"Patel","suffix":""},{"id":443700797,"identity":"56e88be7-9996-481b-9d47-e3809cf09166","order_by":1,"name":"Vrushank Shah","email":"","orcid":"","institution":"Indus University","correspondingAuthor":false,"prefix":"","firstName":"Vrushank","middleName":"","lastName":"Shah","suffix":""},{"id":443700798,"identity":"5975611c-c00c-4ba1-95a2-695ec7143f0a","order_by":2,"name":"Dipti Khurge","email":"","orcid":"","institution":"Pimpri Chinchwad College Of Engineering","correspondingAuthor":false,"prefix":"","firstName":"Dipti","middleName":"","lastName":"Khurge","suffix":""}],"badges":[],"createdAt":"2025-04-16 08:23:32","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-6461225/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-6461225/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":80986084,"identity":"a80a8583-02d2-4357-84bd-eff773fa10e1","added_by":"auto","created_at":"2025-04-21 00:31:24","extension":"pdf","order_by":1,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":1358888,"visible":true,"origin":"","legend":"","description":"","filename":"ManuScriptAmiPatel.pdf","url":"https://assets-eu.researchsquare.com/files/rs-6461225/v1_covered_da1ee0ae-d6f9-40d1-a423-d11952ace67a.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"Design and Comparison of low power fault tolerant logic circuit using QCA nano Technology","fulltext":[],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":false,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":true,"hideJournal":true,"highlight":"","institution":"","isAcceptedByJournal":false,"isAuthorSuppliedPdf":true,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":true,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"Quantum dot Cellular Automata, Fault tolerance, majority gate","lastPublishedDoi":"10.21203/rs.3.rs-6461225/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-6461225/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eQuantum Dot Cellular Automata (QCA) is a promising alternative to traditional CMOS technologies for future nanocomputing due to its potential for ultra-low power consumption and high-density integration. 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