Design and Implementation of an 8-Bit Logical Barrel Shifter Using Cadence Virtuoso and Xcelium in 45 nm CMOS Technology

Design and Implementation of an 8-Bit Logical Barrel Shifter Using Cadence Virtuoso and Xcelium in 45 nm CMOS Technology | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Design and Implementation of an 8-Bit Logical Barrel Shifter Using Cadence Virtuoso and Xcelium in 45 nm CMOS Technology Abhay Surya Rajashekarappa This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-8930915/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract Shifting operations are fundamental to arithmetic and logic units in modern digital systems; however, conventional shift registers perform multi-bit shifts sequentially, leading to increased latency and reduced throughput. To overcome this limitation, barrel shifters are commonly em ployed to achieve single-cycle shifting using combinational logic, though detailed transistor-level implementations and verification are not always presented in academic works. In this paper, an 8-bit logical right barrel shifter is designed using a multiplexer-based static CMOS architecture and implemented at the transistor level using Cadence Virtuoso in 45-nm CMOS technology. The proposed design employs three cascaded stages corre- sponding to conditional shifts of 4, 2, and 1 bits, realized using a total of 24 static CMOS 2:1 multiplexers. Transistor-level verification is performed using Cadence Virtuoso, while functional correctness is validated through a Verilog testbench using Cadence Xcelium. Simulation results confirm correct logical right shift operation with full voltage swing and single-cycle performance at a supply voltage of 1.8 V, demonstrating the suitability of the proposed design for integration into processor and DSP architectures. Electrical Engineering Barrel shifter architecture Static CMOS logic Combinational logic design Transistor-level verification VLSI design 45 nm technology Cadence Xcelium Digital signal processing (DSP) Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 1. Introduction Shifting operations are fundamental in digital systems and are extensively used in arithmetic computations, data alignment, multiplication, division, and address generation. Conventional shift registers perform shift operations sequentially, requiring multiple clock cycles for large shift amounts. This limitation results in increased latency and reduced performance. A barrel shifter overcomes this drawback by performing multi- bit shift operations in a single cycle using combinational logic. Due to its high speed, the barrel shifter is a critical component in modern processors and digital signal processing systems. This work focuses on the design and verification of an 8-bit logical right barrel shifter implemented using static CMOS multiplexers. The implementation is carried out at the transistor level using Cadence Virtuoso in a 45 nm CMOS process and functionally validated using Cadence Xcelium. Therefore, this work presents a detailed transistor-level design and verification of an 8-bit logical barrel shifter using industry standard EDA tools. 2. Barrel Shifter Overview A barrel shifter is a combinational circuit that shifts an input data word by a specified number of bit positions. The shift amount is controlled by a set of control signals, and the operation is completed without the use of clocked elements. Key advantages of barrel shifters include: High-speed operation Single cycle shifting Scalability to higher bit widths Depending on the design, barrel shifters can support logical shift, arithmetic shift and rotate operations. In this work, an 8- bit logical barrel shifter is implemented using 2:1 multiplexers arranged in 8 rows and 3 columns to efficiently perform the required shift operations. The 8-bit barrel shifter requires 𝒏 ∗ 𝐥𝐨𝐠 𝟐 𝒏 2:1 multiplexers, where 𝒏 is the number of bits in the input word, resulting in 24 multiplexers for this implementation. 3. Architecture 3.1 Functional Description The proposed 8-bit barrel shifter accepts an 8-bit input data word A[7:0] and produces an 8-bit output Y[7:0]. The amount of shift is controlled by a 3-bit control signal S[2:0], allowing shift values from 0 to 7. The implemented operation is a logical right shift. Shift control interpretation: S = 000 → No shift S = 001 → Right shift by 1 bit S = 010 → Right shift by 2 bits S = 011 → Right shift by 3 bits S = 100 → Right shift by 4 bits S = 101 → Right shift by 5 bits S = 110 → Right shift by 6 bits S = 111 → Right shift by 7 bits Example Input A[7:0] = 11111111, Shift control S[2:0] = 010 → Output Y[7:0] = 00111111. Since the architecture is purely combinational, the shift operation is completed within a single cycle without any clock dependency. 3.2 Multiplexer-Based Architecture The barrel shifter is implemented using multiplexer-based architecture. For an N-bit barrel shifter, 𝐥𝐨𝐠 𝟐 (N) stages are required. Therefore, the 8-bit design consists of three stages: Stage 1 : Conditional right shift by 4 bits (controlled by S2) Stage 2 : Conditional right shift by 2 bits (controlled by S1) Stage 3 : Conditional right shift by 1 bit (controlled by S0) Each stage contains eight parallel 2:1 multiplexers. The output of one stage serves as the input to the next stage, enabling cumulative right shifting. The architecture is purely combinational, enabling single-cycle shift operation without the use of clocked elements. 4. Circuit Implementation Using Cadence Virtuoso 4.1 Static CMOS 2:1 Multiplexer Design Static CMOS logic was selected due to its full voltage swing, noise immunity, and robustness in scaled CMOS technologies. The multiplexer is implemented using static CMOS logic in Cadence 45 nm technology with a supply voltage of 1.8 V. Figure 2 shows the transistor-level schematic of the multiplexer designed using Cadence Virtuoso. The circuit consists of complementary PMOS pull-up and NMOS pull-down networks controlled by the select signal and its complement. 4.2 Eight-Bit Barrel Shifter Schematic Figure 3 illustrates the complete transistor-level schematic of the 8-bit logical right barrel shifter implemented in Cadence Virtuoso. The design consists of three cascaded stages of multiplexers corresponding to conditional right shifts of 4, 2, and 1 bit positions. The complete barrel shifter consists of 24 static CMOS 2:1 multiplexers arranged across three stages corresponding to shift amounts of 4, 2 and 1 bits. 4.3 Hierarchical and Modular Design Approach The barrel shifter is designed hierarchically by first creating and verifying a single static CMOS 2:1 multiplexer cell. This verified cell is then instantiated multiple times to construct each stage of the barrel shifter. Such a modular design approach simplifies debugging, improves readability, and allows easy scalability to higher bit-width implementations. 5. Simulation and Verification 5.1 Transistor-Level Verification Using Cadence Virtuoso Transistor-level verification of the proposed 8-bit barrel shifter was conducted using the Cadence Virtuoso simulation environment in a 45 nm CMOS process with a supply voltage of 1.8 V. Transient analysis was performed to observe the output waveforms corresponding to input data (A[7:0] = 11111111) and select line (S[2:0] = 111) combination. The waveform confirms correct logical right shift operation with full voltage swing. 5.2 Functional Verification Using Cadence Xcelium Functional verification of the barrel shifter was performed using the Cadence Xcelium simulator with a Verilog test bench. Various input data values and shift control combinations were applied to validate all logical right shift operations. Test vectors are mentioned below: Table 1 Input test vectors and select lines. Input A[7:0] Select Lines S[2:0] Output Y[7:0] 10000000 100 00001000 10000000 010 00100000 10000000 001 01000000 10000000 111 00000001 6. Results and Discussion The proposed 8-bit logical right barrel shifter was verified at both transistor and functional levels to ensure correctness and robustness of the design. Transistor-level transient simulations were carried out using Cadence Virtuoso in a 45 nm CMOS process with a supply voltage of 1.8 V. For an input vector A[7:0] = 11111111 and shift control S[2:0] = 111, the output waveform correctly produces a right shift by seven positions, confirming accurate combinational behavior. The simulated waveforms exhibit full rail-to-rail voltage swing, indicating proper operation of the static CMOS multiplexer design without signal degradation. Functional verification using Cadence Xcelium further validated the design using a Verilog testbench. Multiple test vectors were applied to cover all possible shift control combinations from 0 to 7. The observed outputs matched the expected logical right shift values for all test cases, as summarized in Table 1 . This confirms correct propagation of data through all three multiplexer stages corresponding to shift values of 4, 2, and 1 bits. The multiplexer-based architecture ensures deterministic timing behavior and avoids clock dependency, enabling single-cycle shift operation. Additionally, the hierarchical design approach improves scalability, allowing the architecture to be extended to higher bit-width barrel shifters with minimal design effort. The results demonstrate that the proposed implementation is reliable and suitable for integration into arithmetic logic units and digital signal processing systems. Compared to sequential shift-register-based implementations, the proposed design eliminates multi-cycle latency by completing the shift operation within a single combinational cycle. 7. Conclusion This paper presented the design, implementation, and verification of an 8-bit logical right barrel shifter using a multiplexer-based static CMOS architecture in 45 nm CMOS technology. The design was implemented at the transistor level using Cadence Virtuoso and functionally verified using Cadence Xcelium, ensuring both circuit-level and behavioral correctness. The proposed architecture performs multi-bit shift operations in a single cycle without the use of clocked elements, thereby reducing latency compared to conventional shift registers. Simulation results confirm correct logical right shift functionality with full voltage swing and reliable operation at a supply voltage of 1.8 V. The hierarchical and modular design approach enables easy scalability to higher bit-width implementations, making the design suitable for use in processors, digital signal processors, and other high- performance digital systems. Future work may include power and delay analysis, layout-level implementation, and comparison with alternative shifter architectures such as transmission-gate-based or pass-transistor designs. References Gavaskar K, Paramasivam K, Thilagavathy KP, Sri Vishnu MV, Logash B, Karthikeyan S (2025) Design of Barrel Shift Registers with Enhanced Performance Analysis for Modern Processors, 2025 3rd International Conference on Advancements in Electrical, Electronics, Communication, Computing and Automation (ICAECA), Coimbatore, India, pp. 1–6. 10.1109/ICAECA63854.2025.11012175 Rabaey JM, Chandrakasan A, Nikolić B (2003) Digital Integrated Circuits: A Design Perspective, 2nd edn. Prentice Hall Kang S, Leblebici Y (2003) CMOS Digital Integrated Circuits: Analysis and Design, 3rd edn. McGraw-Hill Weste NHE, Harris D (2011) CMOS VLSI Design: A Circuits and Systems Perspective, 4th ed., Pearson Education Systems CD (2023) Xcelium™ Logic Simulator User Guide. Cadence Documentation Zimmermann R, Fichtner W (1997) Low-power logic styles: CMOS versus pass-transistor logic, IEEE J. Solid- State Circuits, vol. 32, no. 7, pp. 1079–1090, Jul Morris Mano M, Ciletti MD (2013) Digital Design, 5th ed., Pearson Furber SB (1989) VLSI RISC Architecture and Organization, 1st edn. CRC Chandrakasan A, Sheng S, Brodersen R (1992) Low- power CMOS digital design, IEEE J. Solid-State Circuits, vol. 27, no. 4, pp. 473–484, Apr Uyemura JP (2002) Introduction to VLSI Circuits and Systems. Wiley Itoh K (2001) VLSI Memory Chip Design. Springer Hodges DA, Jackson HG, Saleh RA (2004) Analysis and Design of Digital Integrated Circuits, 3rd edn. McGraw- Hill Cadence Design Systems (2023) Virtuoso® Schematic Editor User Guide. Cadence Documentation Chandrakasan AP, Brodersen RW (1995) Minimizing power consumption in digital CMOS circuits, Proc. IEEE, vol. 83, no. 4, pp. 498–523, Apr Taur Y, Ning TH (2009) Fundamentals of Modern VLSI Devices, 2nd edn. Cambridge University Press Additional Declarations The authors declare no competing interests. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-8930915","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":594761913,"identity":"c8fb1a09-c20a-4829-b375-0acc0abef26c","order_by":0,"name":"Abhay Surya Rajashekarappa","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAABB0lEQVRIiWNgGAWjYDACCR4E+8CHCiDJzNxAtBbGhzPOgLQwEq+F2Zi3DawVvxb+2b0HP/P8OZxvcPzsMwneebXR/O1ALT8qtuG25M65ZGnetsOWG86km0lIbjueO+MwYwNjz5nbuK25kWMgzdtw2MDgQBqbhOG2Y7kNQC3MjG24tcjfyDH+DXSYgcH5Z2wSiXOO5c4npMXgRo6ZNA8bUMuNNGaDgw01uRsIaTG8c8bMcm5buoHkjWeMDxuOHcjdCNRyEJ9f5G73GN9488fagO98GsPhPzV1ufPOHz744EcFHu8DARMoahQOgNmHweQBvOqBgPEHkJBvALPrCCkeBaNgFIyCEQgAe25hquhkmTIAAAAASUVORK5CYII=","orcid":"https://orcid.org/0009-0006-9700-2556","institution":"B.M.S. College Of Engineering","correspondingAuthor":true,"prefix":"","firstName":"Abhay","middleName":"Surya","lastName":"Rajashekarappa","suffix":""}],"badges":[],"createdAt":"2026-02-21 05:55:04","currentVersionCode":1,"declarations":{"humanSubjects":false,"vertebrateSubjects":false,"conflictsOfInterestStatement":false,"humanSubjectEthicalGuidelines":false,"humanSubjectConsent":false,"humanSubjectClinicalTrial":false,"humanSubjectCaseReport":false,"vertebrateSubjectEthicalGuidelines":false},"doi":"10.21203/rs.3.rs-8930915/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-8930915/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":103285895,"identity":"ff93907f-e1b8-48b7-840a-e319df248055","added_by":"auto","created_at":"2026-02-24 04:50:36","extension":"jpeg","order_by":1,"title":"Figure 1","display":"","copyAsset":false,"role":"figure","size":36545,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cem\u003e2:1 Multiplexer based Architecture\u003c/em\u003e\u003c/p\u003e","description":"","filename":"image1.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-8930915/v1/f4be3be0da8eef009f5bc151.jpeg"},{"id":103285896,"identity":"67c2a98b-31b6-4bce-b1a8-8971dd5c60d3","added_by":"auto","created_at":"2026-02-24 04:50:36","extension":"png","order_by":2,"title":"Figure 2","display":"","copyAsset":false,"role":"figure","size":428605,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cem\u003eTransistor level schematic of 2:1 Multiplexer\u003c/em\u003e\u003c/p\u003e","description":"","filename":"image2.png","url":"https://assets-eu.researchsquare.com/files/rs-8930915/v1/7d49751cb93def7d6ac1cef6.png"},{"id":103285899,"identity":"1f8c5b3a-cd90-439c-ab17-322f701fbb75","added_by":"auto","created_at":"2026-02-24 04:50:36","extension":"jpeg","order_by":3,"title":"Figure 3","display":"","copyAsset":false,"role":"figure","size":83343,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cem\u003e8 Bit Barrel Shifter Schematic\u003c/em\u003e\u003c/p\u003e","description":"","filename":"image3.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-8930915/v1/7be82c62fd2ede619604624b.jpeg"},{"id":103285898,"identity":"7fb1886d-6c5e-4841-8487-7119207c0e03","added_by":"auto","created_at":"2026-02-24 04:50:36","extension":"jpeg","order_by":4,"title":"Figure 4","display":"","copyAsset":false,"role":"figure","size":52646,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cem\u003eView of 2:1 Multiplexer\u003c/em\u003e\u003c/p\u003e","description":"","filename":"image4.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-8930915/v1/7df22cfc9636c7dc2bb0406b.jpeg"},{"id":103285900,"identity":"dcdd5a20-f3c2-4a0c-ac06-8ee80ac7f635","added_by":"auto","created_at":"2026-02-24 04:50:36","extension":"jpeg","order_by":5,"title":"Figure 5","display":"","copyAsset":false,"role":"figure","size":100077,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cem\u003eTransient Response\u003c/em\u003e\u003c/p\u003e","description":"","filename":"image5.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-8930915/v1/83b7da29b297a4a2e240701c.jpeg"},{"id":103506649,"identity":"21344088-8a8c-4044-8e3a-eb09e7a821a1","added_by":"auto","created_at":"2026-02-26 13:38:25","extension":"jpeg","order_by":6,"title":"Figure 6","display":"","copyAsset":false,"role":"figure","size":35605,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cem\u003eInput test vectors and select lines\u003c/em\u003e\u003c/p\u003e","description":"","filename":"image6.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-8930915/v1/a2a6da9a66b97e66ab070de6.jpeg"},{"id":103506389,"identity":"bad6dff7-fe60-4f36-94a0-74782a7cfcd9","added_by":"auto","created_at":"2026-02-26 13:35:53","extension":"jpeg","order_by":7,"title":"Figure 7","display":"","copyAsset":false,"role":"figure","size":33932,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cem\u003eFunctional verification waveform\u003c/em\u003e\u003c/p\u003e","description":"","filename":"image7.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-8930915/v1/4f4db4a9f3b71c9e56660061.jpeg"},{"id":103509788,"identity":"840a1f7f-b35d-44db-9bf9-27e16df55745","added_by":"auto","created_at":"2026-02-26 14:01:11","extension":"pdf","order_by":0,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":1233918,"visible":true,"origin":"","legend":"","description":"","filename":"manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-8930915/v1/b403990d-488c-4a47-82f9-12331f4e4af8.pdf"}],"financialInterests":"The authors declare no competing interests.","formattedTitle":"\u003cp\u003eDesign and Implementation of an 8-Bit Logical Barrel Shifter Using Cadence Virtuoso and Xcelium in 45 nm CMOS Technology\u003c/p\u003e","fulltext":[{"header":"1. Introduction","content":"\u003cp\u003eShifting operations are fundamental in digital systems and are extensively used in arithmetic computations, data alignment, multiplication, division, and address generation. Conventional shift registers perform shift operations sequentially, requiring multiple clock cycles for large shift amounts. This limitation results in increased latency and reduced performance.\u003c/p\u003e \u003cp\u003eA barrel shifter overcomes this drawback by performing multi- bit shift operations in a single cycle using combinational logic. Due to its high speed, the barrel shifter is a critical component in modern processors and digital signal processing systems. This work focuses on the design and verification of an 8-bit logical right barrel shifter implemented using static CMOS multiplexers. The implementation is carried out at the transistor level using Cadence Virtuoso in a 45 nm CMOS process and functionally validated using Cadence Xcelium. Therefore, this work presents a detailed transistor-level design and verification of an 8-bit logical barrel shifter using industry standard EDA tools.\u003c/p\u003e"},{"header":"2. Barrel Shifter Overview","content":"\u003cp\u003eA barrel shifter is a combinational circuit that shifts an input data word by a specified number of bit positions. The shift amount is controlled by a set of control signals, and the operation is completed without the use of clocked elements. Key advantages of barrel shifters include:\u003c/p\u003e \u003cp\u003e \u003cul\u003e \u003cli\u003e \u003cp\u003eHigh-speed operation\u003c/p\u003e \u003c/li\u003e \u003cli\u003e \u003cp\u003eSingle cycle shifting\u003c/p\u003e \u003c/li\u003e \u003cli\u003e \u003cp\u003eScalability to higher bit widths\u003c/p\u003e \u003c/li\u003e \u003c/ul\u003e \u003c/p\u003e \u003cp\u003eDepending on the design, barrel shifters can support logical shift, arithmetic shift and rotate operations. In this work, an 8- bit logical barrel shifter is implemented using 2:1 multiplexers arranged in 8 rows and 3 columns to efficiently perform the required shift operations.\u003c/p\u003e \u003cp\u003eThe 8-bit barrel shifter requires \u0026#119951; \u0026lowast; \u0026#119845;\u0026#119848;\u0026#119840; \u0026#120784; \u0026#119951; 2:1 multiplexers, where \u0026#119951; is the number of bits in the input word, resulting in \u003cb\u003e24 multiplexers\u003c/b\u003e for this implementation.\u003c/p\u003e"},{"header":"3. Architecture","content":"\u003cdiv id=\"Sec4\" class=\"Section2\"\u003e \u003ch2\u003e3.1 Functional Description\u003c/h2\u003e \u003cp\u003e \u003cdiv class=\"BlockQuote\"\u003e \u003cp\u003eThe proposed 8-bit barrel shifter accepts an 8-bit input data word A[7:0] and produces an 8-bit output Y[7:0]. The amount of shift is controlled by a 3-bit control signal S[2:0], allowing shift values from 0 to 7. The implemented operation is a logical right shift.\u003c/p\u003e \u003cp\u003eShift control interpretation:\u003c/p\u003e \u003c/div\u003e \u003c/p\u003e \u003cp\u003e \u003cul\u003e \u003cli\u003e \u003cp\u003eS\u0026thinsp;=\u0026thinsp;000 \u0026rarr; No shift\u003c/p\u003e \u003c/li\u003e \u003cli\u003e \u003cp\u003eS\u0026thinsp;=\u0026thinsp;001 \u0026rarr; Right shift by 1 bit\u003c/p\u003e \u003c/li\u003e \u003cli\u003e \u003cp\u003eS\u0026thinsp;=\u0026thinsp;010 \u0026rarr; Right shift by 2 bits\u003c/p\u003e \u003c/li\u003e \u003cli\u003e \u003cp\u003eS\u0026thinsp;=\u0026thinsp;011 \u0026rarr; Right shift by 3 bits\u003c/p\u003e \u003c/li\u003e \u003cli\u003e \u003cp\u003eS\u0026thinsp;=\u0026thinsp;100 \u0026rarr; Right shift by 4 bits\u003c/p\u003e \u003c/li\u003e \u003cli\u003e \u003cp\u003eS\u0026thinsp;=\u0026thinsp;101 \u0026rarr; Right shift by 5 bits\u003c/p\u003e \u003c/li\u003e \u003cli\u003e \u003cp\u003eS\u0026thinsp;=\u0026thinsp;110 \u0026rarr; Right shift by 6 bits\u003c/p\u003e \u003c/li\u003e \u003cli\u003e \u003cp\u003eS\u0026thinsp;=\u0026thinsp;111 \u0026rarr; Right shift by 7 bits\u003c/p\u003e \u003c/li\u003e \u003c/ul\u003e \u003c/p\u003e \u003cp\u003e \u003cstrong\u003eExample\u003c/strong\u003e \u003cp\u003eInput A[7:0]\u0026thinsp;=\u0026thinsp;11111111, Shift control S[2:0]\u0026thinsp;=\u0026thinsp;010 \u0026rarr; Output Y[7:0]\u0026thinsp;=\u0026thinsp;00111111.\u003c/p\u003e \u003c/p\u003e \u003cp\u003e \u003cdiv class=\"BlockQuote\"\u003e \u003cp\u003eSince the architecture is purely combinational, the shift operation is completed within a single cycle without any clock dependency.\u003c/p\u003e \u003c/div\u003e \u003c/p\u003e \u003c/div\u003e \u003cdiv id=\"Sec5\" class=\"Section2\"\u003e \u003ch2\u003e3.2 Multiplexer-Based Architecture\u003c/h2\u003e \u003cp\u003e \u003cdiv class=\"BlockQuote\"\u003e \u003cp\u003eThe barrel shifter is implemented using multiplexer-based architecture. For an N-bit barrel shifter, \u0026#119845;\u0026#119848;\u0026#119840; \u0026#120784; \u003cb\u003e(N)\u003c/b\u003e stages are required. Therefore, the 8-bit design consists of three stages:\u003c/p\u003e \u003c/div\u003e \u003c/p\u003e \u003cp\u003e \u003cul\u003e \u003cli\u003e \u003cp\u003e \u003cb\u003eStage 1\u003c/b\u003e: Conditional right shift by 4 bits (controlled by S2)\u003c/p\u003e \u003c/li\u003e \u003cli\u003e \u003cp\u003e \u003cb\u003eStage 2\u003c/b\u003e: Conditional right shift by 2 bits (controlled by S1)\u003c/p\u003e \u003c/li\u003e \u003cli\u003e \u003cp\u003e \u003cb\u003eStage 3\u003c/b\u003e: Conditional right shift by 1 bit (controlled by S0)\u003c/p\u003e \u003c/li\u003e \u003c/ul\u003e \u003cdiv class=\"BlockQuote\"\u003e \u003cp\u003eEach stage contains \u003cb\u003eeight\u003c/b\u003e parallel 2:1 multiplexers. The output of one stage serves as the input to the next stage, enabling cumulative right shifting. The architecture is purely combinational, enabling single-cycle shift operation without the use of clocked elements.\u003c/p\u003e \u003c/div\u003e \u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003c/div\u003e"},{"header":"4. Circuit Implementation Using Cadence Virtuoso","content":"\u003cdiv id=\"Sec7\" class=\"Section2\"\u003e \u003ch2\u003e4.1 Static CMOS 2:1 Multiplexer Design\u003c/h2\u003e \u003cp\u003e \u003cdiv class=\"BlockQuote\"\u003e \u003cp\u003eStatic CMOS logic was selected due to its full voltage swing, noise immunity, and robustness in scaled CMOS technologies. The multiplexer is implemented using static CMOS logic in Cadence 45 nm technology with a supply voltage of 1.8 V. Figure\u0026nbsp;\u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e2\u003c/span\u003e shows the transistor-level\u003c/p\u003e \u003c/div\u003e \u003c/p\u003e \u003cp\u003eschematic of the multiplexer designed using Cadence Virtuoso. The circuit consists of complementary PMOS pull-up and NMOS pull-down networks controlled by the select signal and its complement.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003c/div\u003e \u003cdiv id=\"Sec8\" class=\"Section2\"\u003e \u003ch2\u003e4.2 Eight-Bit Barrel Shifter Schematic\u003c/h2\u003e \u003cp\u003e \u003cdiv class=\"BlockQuote\"\u003e \u003cp\u003eFigure \u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003e illustrates the complete transistor-level schematic of the 8-bit logical right barrel shifter implemented in Cadence Virtuoso. The design consists of three cascaded stages of multiplexers corresponding to conditional right shifts of 4, 2, and 1 bit positions. The complete barrel shifter consists of 24 static CMOS 2:1 multiplexers arranged across three stages corresponding to shift amounts of 4, 2 and 1 bits.\u003c/p\u003e \u003c/div\u003e \u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003c/div\u003e \u003cdiv id=\"Sec9\" class=\"Section2\"\u003e \u003ch2\u003e4.3 Hierarchical and Modular Design Approach\u003c/h2\u003e \u003cp\u003e \u003cdiv class=\"BlockQuote\"\u003e \u003cp\u003eThe barrel shifter is designed hierarchically by first creating and verifying a single static CMOS 2:1 multiplexer cell. This verified cell is then instantiated multiple times to construct each stage of the barrel shifter. Such a modular design approach simplifies debugging, improves readability, and allows easy scalability to higher bit-width implementations.\u003c/p\u003e \u003c/div\u003e \u003c/p\u003e \u003c/div\u003e"},{"header":"5. Simulation and Verification","content":"\u003cdiv id=\"Sec11\" class=\"Section2\"\u003e \u003ch2\u003e5.1 Transistor-Level Verification Using Cadence Virtuoso\u003c/h2\u003e \u003cp\u003e \u003cdiv class=\"BlockQuote\"\u003e \u003cp\u003eTransistor-level verification of the proposed 8-bit barrel shifter was conducted using the Cadence Virtuoso simulation environment in a 45 nm CMOS process with a supply voltage of 1.8 V.\u003c/p\u003e \u003cp\u003eTransient analysis was performed to observe the output waveforms corresponding to input data (A[7:0]\u0026thinsp;=\u0026thinsp;11111111) and select line (S[2:0]\u0026thinsp;=\u0026thinsp;111) combination.\u003c/p\u003e \u003cp\u003eThe waveform confirms correct logical right shift operation with full voltage swing.\u003c/p\u003e \u003c/div\u003e \u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003c/div\u003e \u003cdiv id=\"Sec12\" class=\"Section2\"\u003e \u003ch2\u003e5.2 Functional Verification Using Cadence Xcelium\u003c/h2\u003e \u003cp\u003eFunctional verification of the barrel shifter was performed using the Cadence Xcelium simulator with a Verilog test bench. Various input data values and shift control combinations were applied to validate all logical right shift operations.\u003c/p\u003e \u003cp\u003eTest vectors are mentioned below:\u003c/p\u003e \u003cp\u003e \u003cdiv class=\"gridtable\"\u003e\u003ctable float=\"Yes\" id=\"Tab1\" border=\"1\"\u003e \u003ccaption language=\"En\"\u003e \u003cdiv class=\"CaptionNumber\"\u003eTable 1\u003c/div\u003e \u003cdiv class=\"CaptionContent\"\u003e \u003cp\u003eInput test vectors and select lines.\u003c/p\u003e \u003c/div\u003e \u003c/caption\u003e \u003ccolgroup cols=\"3\"\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c1\" colnum=\"1\"\u003e\u003c/div\u003e \u003cdiv align=\"char\" char=\".\" class=\"colspec\" colname=\"c2\" colnum=\"2\"\u003e\u003c/div\u003e \u003cdiv align=\"char\" char=\".\" class=\"colspec\" colname=\"c3\" colnum=\"3\"\u003e\u003c/div\u003e \u003cthead\u003e \u003ctr\u003e \u003cth align=\"left\" colname=\"c1\"\u003e \u003cp\u003eInput A[7:0]\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c2\"\u003e \u003cp\u003eSelect Lines S[2:0]\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c3\"\u003e \u003cp\u003eOutput Y[7:0]\u003c/p\u003e \u003c/th\u003e \u003c/tr\u003e \u003c/thead\u003e \u003ctbody\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003e10000000\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c2\"\u003e \u003cp\u003e100\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c3\"\u003e \u003cp\u003e00001000\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003e10000000\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c2\"\u003e \u003cp\u003e010\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c3\"\u003e \u003cp\u003e00100000\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003e10000000\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c2\"\u003e \u003cp\u003e001\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c3\"\u003e \u003cp\u003e01000000\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003e10000000\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c2\"\u003e \u003cp\u003e111\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c3\"\u003e \u003cp\u003e00000001\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003c/tbody\u003e \u003c/colgroup\u003e \u003c/table\u003e\u003c/div\u003e \u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003c/div\u003e"},{"header":"6. Results and Discussion","content":"\u003cp\u003eThe proposed 8-bit logical right barrel shifter was verified at both transistor and functional levels to ensure correctness and robustness of the design. Transistor-level transient simulations were carried out using Cadence Virtuoso in a 45 nm CMOS process with a supply voltage of 1.8 V. For an input vector A[7:0]\u0026thinsp;=\u0026thinsp;11111111 and shift control S[2:0]\u0026thinsp;=\u0026thinsp;111, the output waveform correctly produces a right shift by seven positions, confirming accurate combinational behavior. The simulated waveforms exhibit full rail-to-rail voltage swing, indicating proper operation of the static CMOS multiplexer design without signal degradation.\u003c/p\u003e \u003cp\u003eFunctional verification using Cadence Xcelium further validated the design using a Verilog testbench. Multiple test vectors were applied to cover all possible shift control combinations from 0 to 7. The observed outputs matched the expected logical right shift values for all test cases, as summarized in Table\u0026nbsp;\u003cspan refid=\"Tab1\" class=\"InternalRef\"\u003e1\u003c/span\u003e. This confirms correct propagation of data through all three multiplexer stages corresponding to shift values of 4, 2, and 1 bits.\u003c/p\u003e \u003cp\u003eThe multiplexer-based architecture ensures deterministic timing behavior and avoids clock dependency, enabling single-cycle shift operation. Additionally, the hierarchical design approach improves scalability, allowing the architecture to be extended to higher bit-width barrel shifters with minimal design effort. The results demonstrate that the proposed implementation is reliable and suitable for integration into arithmetic logic units and digital signal processing systems.\u003c/p\u003e \u003cp\u003eCompared to sequential shift-register-based implementations, the proposed design eliminates multi-cycle latency by completing the shift operation within a single combinational cycle.\u003c/p\u003e"},{"header":"7. Conclusion","content":"\u003cp\u003eThis paper presented the design, implementation, and verification of an 8-bit logical right barrel shifter using a multiplexer-based static CMOS architecture in 45 nm CMOS technology. The design was implemented at the transistor level using Cadence Virtuoso and functionally verified using Cadence Xcelium, ensuring both circuit-level and behavioral correctness. The proposed architecture performs multi-bit shift operations in a single cycle without the use of clocked elements, thereby reducing latency compared to conventional shift registers.\u003c/p\u003e \u003cp\u003eSimulation results confirm correct logical right shift functionality with full voltage swing and reliable operation at a supply voltage of 1.8 V. The hierarchical and modular design approach enables easy scalability to higher bit-width implementations, making the design suitable for use in processors, digital signal processors, and other high-\u003c/p\u003e \u003cp\u003eperformance digital systems. Future work may include power and delay analysis, layout-level implementation, and comparison with alternative shifter architectures such as transmission-gate-based or pass-transistor designs.\u003c/p\u003e"},{"header":"References","content":"\u003col\u003e\u003cli\u003e\u003cspan\u003eGavaskar K, Paramasivam K, Thilagavathy KP, Sri Vishnu MV, Logash B, Karthikeyan S (2025) Design of Barrel Shift Registers with Enhanced Performance Analysis for Modern Processors, 2025 3rd International Conference on Advancements in Electrical, Electronics, Communication, Computing and Automation (ICAECA), Coimbatore, India, pp. 1\u0026ndash;6. \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003e10.1109/ICAECA63854.2025.11012175\u003c/span\u003e\u003cspan address=\"10.1109/ICAECA63854.2025.11012175\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eRabaey JM, Chandrakasan A, Nikolić B (2003) Digital Integrated Circuits: A Design Perspective, 2nd edn. Prentice Hall\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eKang S, Leblebici Y (2003) CMOS Digital Integrated Circuits: Analysis and Design, 3rd edn. McGraw-Hill\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eWeste NHE, Harris D (2011) CMOS VLSI Design: A Circuits and Systems Perspective, 4th ed., Pearson Education\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eSystems CD (2023) Xcelium\u0026trade; Logic Simulator User Guide. Cadence Documentation\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eZimmermann R, Fichtner W (1997) Low-power logic styles: CMOS versus pass-transistor logic, IEEE J. Solid- State Circuits, vol. 32, no. 7, pp. 1079\u0026ndash;1090, Jul\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eMorris Mano M, Ciletti MD (2013) Digital Design, 5th ed., Pearson\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eFurber SB (1989) VLSI RISC Architecture and Organization, 1st edn. CRC\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eChandrakasan A, Sheng S, Brodersen R (1992) Low- power CMOS digital design, IEEE J. Solid-State Circuits, vol. 27, no. 4, pp. 473\u0026ndash;484, Apr\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eUyemura JP (2002) Introduction to VLSI Circuits and Systems. Wiley\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eItoh K (2001) VLSI Memory Chip Design. Springer\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eHodges DA, Jackson HG, Saleh RA (2004) Analysis and Design of Digital Integrated Circuits, 3rd edn. McGraw- Hill\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eCadence Design Systems (2023) Virtuoso\u0026reg; Schematic Editor User Guide. Cadence Documentation\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eChandrakasan AP, Brodersen RW (1995) Minimizing power consumption in digital CMOS circuits, Proc. IEEE, vol. 83, no. 4, pp. 498\u0026ndash;523, Apr\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eTaur Y, Ning TH (2009) Fundamentals of Modern VLSI Devices, 2nd edn. Cambridge University Press\u003c/span\u003e\u003c/li\u003e\u003c/ol\u003e"}],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":true,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":true,"hideJournal":true,"highlight":"","institution":"B.M.S. College Of Engineering","isAcceptedByJournal":false,"isAuthorSuppliedPdf":false,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":false,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"Barrel shifter architecture, Static CMOS logic, Combinational logic design, Transistor-level verification, VLSI design, 45 nm technology, Cadence Xcelium, Digital signal processing (DSP)","lastPublishedDoi":"10.21203/rs.3.rs-8930915/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-8930915/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eShifting operations are fundamental to arithmetic and logic units in modern digital systems; however, conventional shift registers perform multi-bit shifts sequentially, leading to increased latency and reduced throughput. To overcome this limitation, barrel shifters are commonly em\u003c/p\u003e \u003cp\u003eployed to achieve single-cycle shifting using combinational logic, though detailed transistor-level implementations and verification are not always presented in academic works. In this paper, an 8-bit logical right barrel shifter is designed using a multiplexer-based static CMOS architecture and implemented at the transistor level using Cadence Virtuoso in 45-nm CMOS technology. The proposed design employs three cascaded stages corre- sponding to conditional shifts of 4, 2, and 1 bits, realized using a total of 24 static CMOS 2:1 multiplexers. Transistor-level verification is performed using Cadence Virtuoso, while functional correctness is validated through a Verilog testbench using Cadence Xcelium. Simulation results confirm correct logical right shift operation with full voltage swing and single-cycle performance at a supply voltage of 1.8 V, demonstrating the suitability of the proposed design for integration into processor and DSP architectures.\u003c/p\u003e","manuscriptTitle":"Design and Implementation of an 8-Bit Logical Barrel Shifter Using Cadence Virtuoso and Xcelium in 45 nm CMOS Technology","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2026-02-24 04:50:31","doi":"10.21203/rs.3.rs-8930915/v1","editorialEvents":[{"type":"communityComments","content":0}],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true}}],"origin":"","ownerIdentity":"71cb5f23-f202-4e58-af09-7bfa9e21f5dd","owner":[],"postedDate":"February 24th, 2026","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"posted","subjectAreas":[{"id":63297639,"name":"Electrical Engineering"}],"tags":[],"updatedAt":"2026-02-24T04:50:31+00:00","versionOfRecord":[],"versionCreatedAt":"2026-02-24 04:50:31","video":"","vorDoi":"","vorDoiUrl":"","workflowStages":[]},"version":"v1","identity":"rs-8930915","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-8930915","identity":"rs-8930915","version":["v1"]},"buildId":"XKTyCvWXoU3ODBz1xrDgd","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}