Preliminary Evaluation of SHAVER: Sharing Vector Registers with an Accelerator

Preliminary Evaluation of SHAVER: Sharing Vector Registers with an Accelerator | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Preliminary Evaluation of SHAVER: Sharing Vector Registers with an Accelerator Tomoaki Tanaka, Michiya Kato, Yasunori Osana, Takefumi Miyoshi, and 3 more This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-5328960/v1 This work is licensed under a CC BY 4.0 License Status: Under Review Version 1 posted 20 You are reading this latest preprint version Abstract In recent years, demand for data-parallel processing has been growing, and this parallelism often appears in AI processes. One method to accelerate these processes is using DSA, domain-specific architecture. A common data transfer method on DSA is DMA, which is direct memory access. There are several studies on DMA-based accelerators. However, few studies focus on data transfer methods. In this paper, a vector register-sharing mechanism has been proposed as a new data transfer method. Our proposed mechanism is named "SHAVER". In this mechanism, a part of vector registers is directly shared with an accelerator. An open-source RISC-V vector co-processor is used to evaluate the mechanism's potential. It has been implemented on an FPGA and a simulator for the evaluations. The results indicate the possibility of the proposal mechanism to achieve a maximum of 8.38% speedup over DMA transfer. RISC-V Hardware Acceleration FPGA SoC Full Text Additional Declarations No competing interests reported. Cite Share Download PDF Status: Under Review Version 1 posted Editorial decision: Revision requested 14 Nov, 2024 Reviews received at journal 13 Nov, 2024 Reviews received at journal 13 Nov, 2024 Reviews received at journal 10 Nov, 2024 Reviews received at journal 04 Nov, 2024 Reviewers agreed at journal 02 Nov, 2024 Reviews received at journal 31 Oct, 2024 Reviewers agreed at journal 31 Oct, 2024 Reviewers agreed at journal 30 Oct, 2024 Reviewers agreed at journal 30 Oct, 2024 Reviewers agreed at journal 30 Oct, 2024 Reviewers agreed at journal 29 Oct, 2024 Reviewers agreed at journal 29 Oct, 2024 Reviewers agreed at journal 28 Oct, 2024 Reviewers agreed at journal 28 Oct, 2024 Reviewers agreed at journal 27 Oct, 2024 Reviewers invited by journal 27 Oct, 2024 Editor assigned by journal 26 Oct, 2024 Submission checks completed at journal 26 Oct, 2024 First submitted to journal 24 Oct, 2024 You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. 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Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-5328960","acceptedTermsAndConditions":true,"allowDirectSubmit":false,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":373622121,"identity":"00b235d1-75cb-4361-88d4-572e5e0f5713","order_by":0,"name":"Tomoaki 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