Nonlinear Optical Vector Processing at 50 Gbs using Linear Silicon Photonic Circuits

Nonlinear Optical Vector Processing at 50 Gbs using Linear Silicon Photonic Circuits | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Article Nonlinear Optical Vector Processing at 50 Gbs using Linear Silicon Photonic Circuits Theodoros Moschos, Christos Pappas, Stefanos Kovaios, Ioannis Roumpos, and 8 more This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-5928777/v1 This work is licensed under a CC BY 4.0 License Status: Published Journal Publication published 17 Dec, 2025 Read the published version in Nature Communications → Version 1 posted You are reading this latest preprint version Abstract The need for high-speed, energy-efficient computing in machine learning and real-time communication necessitates innovations beyond conventional digital and analog electronics to sustain computational power advances without requiring prohibitive energy amounts. Photonics has emerged as a promising platform demonstrating significant highlights in the field of linear transformations. Adopting, however, the use of photons within a broad range of computing applications necessitates their successful employment also in nonlinear vector processing and matching functionalities, which still continue to comprise the stronghold of electronics. In this direction, we demonstrate nonlinear optical vector processing in the form of Hamming Distance (HD) calculation and Content Addressable Memory (CAM) bank operations using linear optical circuits on Silicon photonics (SiPho) at a record-high-speed of 50 Gb/s, enabling advances in pattern matching, error-correction and look-up tables. The processor employs a 4×4 crossbar architecture with 56 GHz SiGe electro-absorption modulators to compute HD between 2-bit optical vectors. It achieves error-rates of ~ 10⁻³ in CAM and ternary CAM applications that correspond to zero HD, improving state-of-the-art CAM speed performance by > 2.5x. Scalability is enhanced by employing space-wavelength multiplexing schemes via a WDM-enabled SiPho processor cell, which is experimentally demonstrated at 50 Gb/s and offers the potential to increase the computational capacity in a reduced insertion loss and power consumption envelope. The realization of HD calculation and CAM matchline operations via linear optical transformations can pave the inroad towards implementing additional nonlinear optical vector transformation processes at high data-rates via linear silicon photonic circuits, like the calculation of Euclidean distance and Cosine distance metrics. Physical sciences/Optics and photonics/Optical materials and structures/Silicon photonics Physical sciences/Optics and photonics/Applied optics/Integrated optics Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Introduction The demand for high-speed and energy-efficient computing continues to rise with the proliferation of data-intensive applications, such as machine learning, genomic analysis, and real-time communication [ 1 ]. In this race, digital electronic systems comprise still the steam engine in today’s computational landscape, though analog electronics are also gaining momentum as a viable alternative for energy efficient computations directly in the analog domain [ 2 ]. However, as data rates and dataset sizes continue to grow, electronic computing in both its digital and analog versions is facing diminishing returns due to the native physical constraints of electronic technology: the size and energy advantages of electronic circuitry are naturally counteracted by the speed and power limits of the electronic interconnects inside the circuits due to RC parasitic effects [ 3 ], with current electronic processors hardly exceeding GHz clock frequencies. These limitations indicate that a radical shift from conventional electronic computing architectures towards novel hardware computing paradigms need to be realized. In this direction, silicon photonics (SiPho) emerge as a promising candidate for penetrating the processing and compute domains to turn their well-known dominance in the interconnect sector into a profound advantage also in the computational segment. Migrating, however, into a light-enabled processor technology paradigm has to ensure the successful deployment of fundamental computing operations at both symbol- and vector-/ string-level in the optical domain. In this realm, photonics have already shown an impressive potential in implementing universal linear transformations over analog optical vectors [ 4 ]-[ 8 ], facilitating critical matrix and tensor multiplier building blocks in application fields like quantum [ 9 ],[ 10 ], neuromorphic [ 11 ]-[ 16 ] and microwave photonics [ 17 ],[ 18 ]. However, a broad range of applications like pattern matching, error correction and similarity searches require nonlinear processing functions like comparison and distance calculation processes between strings. These necessitate typically the use of memory and register blocks that are certainly not yet among the strengths of the photonic circuitry [ 19 ][ 20 ]. The calculation of string metrics, like the well-known Hamming Distance (HD), provides critical quantitative information about string and vector similarity [ 21 ], with certain distance values leading often to completely new functional blocks. Content Addressable Memories (CAMs), for example, form a specialized yet highly important pattern matching application [ 22 ] that correspond to a zero HD and constitute a critical element in high-speed routers, address and database lookups, and associative search functions [ 23 ]. Although optical CAMs experienced a significant progress during the last decade [ 24 ]-[ 26 ] and raised expectations even for complete high-speed look-up operations via silicon photonic Microring Resonator- (MRRs) [ 27 ] or electro-absorption modulator-based (EAM) setups [ 28 ], the transition from the specific vector matching to the more generic nonlinear processes like vector distance calculation has still not identified a viable photonic implementation route that would broaden the computational portfolio of integrated optics. In this paper, we introduce for the first time, to the best of our knowledge, the nonlinear transformation of optical vectors by using a linear SiPho circuit and demonstrate HD calculation and CAM operation between binary optical strings at record-high data rates of 50 Gb/s. The processor relies on the recently introduced Crossbar (Xbar) architecture [ 5 ], configured as a 4x4 matrix arrangement and employing 56 GHz bandwidth silicon germanium (SiGe) EAMs as its core computational cells. Its performance was experimentally evaluated in calculating the HD between 2-bit optical vectors, presenting also successful operation as optical CAM and Ternary CAM (TCAM) memory bank for 2-bit optical words with matching error-rates of ~ 10 − 3 at operational speeds 2.5x higher than current state-of-the-art CAMs clock speed. Moreover, we introduce a viable roadmap for increasing computational capacity by using space-wavelength multiplexed memory cells, demonstrating experimentally a wavelength division multiplexing (WDM)-enabled architecture that encodes optical vectors across a 2D space-wavelength dimension and performs vector processing at 50 Gb/s. Results Hamming Distance Calculation using a silicon photonic Xbar PIC HD is a metric widely used in information theory as a measure of difference between two vectors/strings of equal length. It is a nonlinear operation defined as the number of positions at which the corresponding symbols (characters or bits) differ. An illustrative example of its application is depicted in Fig. 1 (a), where the HD metric is applied to two N-length binary vectors X and Y. Mathematically the HD operation is defined by the following equation: $$\:HD\:\left(X,Y\right)=\sum\:_{i=1}^{N}L(X\left(i\right)\ne\:Y\left(i\right))$$ 1 with the function \(\:L(X\left(i\right)\ne\:Y\left(i\right))\) indicating all the positions in the N-length vectors X and Y where their corresponding values differ. The most prominent implementation of the HD operator in digital electronics comprises a XOR-gate array, followed by a Full-Adder Tree, as schematically illustrated in Fig. 1 (b) [ 29 ]. Implementing this nonlinear HD calculation process via linear transformations can be realized by doubling the vector dimensions to incorporate also the inverted vector values and applying a dot product operation, as has been initially demonstrated via a rather low-speed analog electronic HD circuitry, depicted in Fig. 1 (c) [ 21 ]. In this layout, the actual and complementary values of array Y are programmed in a memristor array, while the X actual and complementary values are injected as Voltage signals across the memristor array. The resulting output current is, due to Kirchhoff’s law, directly correlated to the HD of the input X and Y vectors. The employment of this mathematical concept and the transfer of the memristor-based architectural approach into the photonic domain can be realized by adopting an equivalent analog optical circuit, as depicted in Fig. 1 (d) and 1(e), by: (i) Encoding the X actual and complementary vector values into a modulated optical light carrier (ii) Encoding the Y actual and complementary values in the transmission values of optical amplitude modulators, which can be assumed to act as optical memory cells that store the corresponding transmission value, (iii) Injecting the encoded X modulated light beams to the Y amplitude modulating elements and adding coherently the resulting optical fields, with the basic building block of this operation being the Comparison Cell highlighted in Fig. 1 (d) (details for its functionality are provided in Supplementary section 1). The basic analog photonic HD circuitry that performs a dot product operation between two optical vectors has been initially presented in [ 30 ] and is shown in Fig. 1 (d). This can be expanded to a parallel HD processor by employing the coherent Xbar architecture, originally proposed in [ 5 ] and depicted in Fig. 1 (e). In this layout the X actual and complementary values are equally broadcasted to the corresponding M Xbar columns using directional couplers, with properly selected splitting ratios. Each column of the Xbar is configured to hold different predefined/target vectors, with each comparison cell assigned to a distinct symbol value. Hence, the HD operation between the incoming X vector and the respective target #M Y Vectors of the Xbar array, is executed in parallel across all Xbar columns allowing up to M parallel HD calculations. The functionality of the proposed analog photonic HD processor architecture was assessed via a 4×4 SiPho integrated Xbar layout that is capable of 2-bit vector distance processing. The photonic chip was fabricated in imec’s SiPho platform, using PDK-ready components. Particularly, every computing cell of the Xbar prototype incorporates 50 µm-long, 56 GHz Franz-Keldysh (FK) SiGe EAMs and 170 µm-long thermo-optic phase shifters (TO-PSs). The deployed photonic integrated circuit (PIC) supports 2-bit search vectors, encoded through the search vector encoding unit (SVEU), highlighted with the yellow rectangle in Fig. 2 (a), that utilizes four EAMs to generate two pairs of complementary search values. The encoded search information is then forwarded into the Xbar-based HD processor, with the corresponding chip area marked with an orange rectangle. The optical signals are distributed across all Xbar columns, which statically encode all the target vectors at every EAM column. The HD result (“match” / degree of “mismatch”) between the search and target vectors is generated at each Xbar output column. The experimental testbed, established for the evaluation of the HD operations, is depicted in Fig. 2 (b). A tunable laser source (TLS) is employed to generate a continuous wave (CW) optical signal at 1563 nm which is injected into the 4×4 Xbar chip. A 4-channel arbitrary waveform generator (AWG) is used to generate the 2-bit electrical search vector. The first and third channel produces the \(\:{\text{B}\text{i}\text{t}}_{1}\) and \(\:{\text{B}\text{i}\text{t}}_{2}\) , respectively, while the second and fourth channels generates their complementary values, i.e. \(\:\stackrel{-}{{\text{B}\text{i}\text{t}}_{1}}\) and \(\:\stackrel{-}{{\text{B}\text{i}\text{t}}_{2}}\) . After electrical amplification, the electrical signals are fed into the input EAMs (yellow rectangle) to encode the optical SVEU. The target 2-bit vectors (i.e., “00”, “01”, “10” and “11”) are implemented by setting the optical attenuation of EAMs located at each Xbar row. Thermo-optic phase shifters are deployed to ensure constructive interference at the output columns of the Xbar. Both EAMs and TO PSs are controlled by a multi-channel DC control plane. The output of each column is captured by an oscilloscope, after being amplified and detected by a photodiode. More details of the experimental setup can be found in methods section. Experimental Validation of Hamming Distance calculation and TCAM Memory Bank at 50 Gb/s The performance of the proposed parallel HD processor was experimentally assessed with 2-bit optical vectors encoded onto the SVEU and compared with respective 2-bit optical vectors stored onto the four Xbar columns. The case of HD = 0 designates an exact vector matching and corresponds to the ML operation of a complete CAM memory bank, with the incoming optical vector representing the search word and the stored optical vectors the respective address words. The photonic comparison cells are used for representing all the memory states of a Binary CAM cell, i.e. “0”, “1”, but can also support the wildcard/ternary value “X” by storing a zero-transmission value to both EAMs within the comparison cell, allowing in this way for an extension to ternary CAM (TCAM) applications. The HD and ML operations performed through the Xbar processor have been experimentally validated for search vector streams at 20 Gb/s and 50 Gb/s. Figure 3 (a) and (c) illustrate the time sequences of the 2-bit optical vector within the first two rows of the figure for a 10-bit time window at 20 Gb/s and 50 Gb/s operation, respectively, with the additional rows depicting the respective time sequences obtained at the Xbar column output port when the column stored content matches the designated Target Vector. The corresponding eye diagrams for every time sequence are shown in Fig. 3 (b) and (d), respectively. For all cases, the cross-shaped scatter points indicate the optimum sampling points, corresponding to one of the three possible output states of the HD operation i.e. HD = 0 (ML operation), HD = 1, and HD = 2. Particularly, the green highlighted area showcases the principle of operation for a search vector value of ‘01’, that corresponds to Bit 1 and Bit 2 values of ‘0’ and ‘1’, respectively. A logical “match” state occurs, only when compared with the target vectors of “01”, “0X”, “X1” and “XX”. As expected, this results in a “zero” output power (HD = 0), since the wildcard value “X” represents a “don’t care state” leading to a logical “match” regardless of the corresponding search value. On the other hand, if the compared vectors have different values, the comparison operation indicates a logical “mismatch”, resulting in an HD > 0. Specifically, if only one of the two search bits matches the content of the Xbar array, the HD is “1” (HD = 1). Conversely, if none of the search bits match the array values, the HD is “2” (HD = 2), as illustrated in the case of the “10” time trace. The performance of the 4x4 vector processor was assessed by calculating the projected symbol error rate (SER), when HD calculation is targeted, and the match error rate (MER) when optical CAM operation is intended, for each different target vector case. The SER quantifies the HD performance, while the MER specifically refers to the error rate of the ‘0’ level that corresponds solely to the matching functionality without accounting for the degree of mismatch (for more details see supplementary material section 3). Figure 3 (e) and (f) illustrate the calculated MER and SER when the Xbar HD processor operates at 20 Gb/s and 50 Gb/s, respectively. As can be observed, all error-rates are in the order of 10 − 3 , comparable with the performance achieved by electronic HD and CAM computing cells [ 31 ]-[ 33 ]. The results indicate a degradation in both SER/MER measurements as the data rate increases, primarily due to noise arising from the limited frequency response of the deployed electro-optic components. Finally, it is worth mentioning that when the wildcard ‘X’ is included, the output signals are restricted to two levels and MER becomes equivalent to SER, resulting at the same time in improved performance compared to 3-level signals. WDM-Enabled Comparison Cell Architecture for Scalable HD Processor Layouts In the previous section, we validated the capabilities of the coherent Xbar architecture in performing HD operations between vectors by leveraging spatially distributed comparison cells and the interference properties of a single coherent light beam. Synergizing the WDM capabilities of the Xbar architecture [ 34 ],[ 35 ], with the HD architectural approach, can offer an additional axis of computational capacity at a reduced insertion loss budget (for more information see supplementary material section 4), thereby enhanced energy efficiency. Figure 4 (a) illustrates the proposed WDM-enabled comparison cell. The actual and complementary search vector symbol ( \(\:Bit\) and \(\:\stackrel{-}{Bit}\) ) are used to modulate two multi-wavelength light beams. The resulting modulated streams are demultiplexed to their wavelength constituents via a demultiplexer [ 36 ], with each wavelength propagating through an intensity modulator (IM) that encodes a value from the target vector. The resulting signals are subsequently multiplexed [ 36 ] and coherently recombined on a wavelength basis via constructive interference, achieved using TO PSs. Finally, the output is demultiplexed, with each wavelength carrying the dot-product between the assigned symbol and the search bit value. Further information about the functionality of the WDM-based cell is presented in supplementary material section 1. This WDM-enabled comparison cell facilitates the parallel execution of HD operations within a single output, where the number of wavelengths represents the level of parallelism. In order to validate the advantages of the WDM-enabled approach a 3λ-2x1 comparison cell was fabricated using the same technological building blocks (i.e. EAM and TO-PS) as in the 4x4 Xbar. A microscope photo of the fabricated chip is depicted in Fig. 4 (b), while the circuit schematic of the WDM-enabled chip along with the experimental setup used to assess its performance in executing HD operations are presented in Fig. 4 (c). Additional information about the experimental testbed of the WDM-enabled HD chip can be found in the methods section. The experimental validation of the proposed WDM-enabled HD processor was conducted at data rates of 20 and 50 Gb/s, employing 3 different wavelengths. Figure 5 (a) depicts indicative 10-bit long time traces at 20 Gb/s operation for the search \(\:\text{B}\text{i}\text{t}\) and \(\:\stackrel{-}{\text{B}\text{i}\text{t}}\) values encoded in all three wavelengths (λ 1 , λ 2 and λ 3 ) and the target Values ‘0’, ‘1’ and ‘X’ indicatively encoded at wavelengths (λ 1 , λ 2 and λ 3 ) respectively. Figure 5 (b) illustrates their respective eye diagrams. The green highlighted area focuses on the case of the search value of logical “0”, meaning the \(\:\text{B}\text{i}\text{t}\) value is “0” and the \(\:\stackrel{-}{\text{B}\text{i}\text{t}}\) is “1”. As observed, when the search value is compared with the target symbol “0”, the HD circuit output is zero (HD = 0), meaning that a logical “match” state is acquired. Conversely, when the target symbol is “1”, the HD = 1 indicating a “mismatch”. For TCAM operation, when the target symbol is the wildcard “X”, the output power remains always at zero level, signifying a match with any incoming search value. Similarly, Fig. 5 (c) and (d) present the respective time traces and eye diagrams, when the WDM-enabled processor operates at 50 Gb/s, revealing successful HD/TCAM functionality. In view of evaluating the performance at 20 and 50 Gb/s, Fig. 5 (e) and (f) depict the acquired Q factor values for both the actual and supplementary input ( \(\:\text{B}\text{i}\text{t}\) and \(\:\stackrel{-}{\text{B}\text{i}\text{t}}\) ) along with the results when targets ‘1’ and ‘0’ are sequentially encoded to different available wavelength cells. Similarly to the single-λ 4x4 Xbar layout, the 50 Gb/s cases exhibit a performance degradation compared to the 20 Gb/s, stemming from the bandwidth limitation of the deployed electro-optic components. Discussion Following the experimental validation of photonic Xbar-based CAM and HD implementations at up to 50 Gb/s and 3λ parallel layouts, we proceed by developing an analytical framework capable of : (i) Assessing the theoretical error rate performance of Xbar-based HD and CAM-layouts for different scales, operational rates and injected laser powers (ii) Quantifying the required single-λ laser power for different HD, CAM and WDM HD and CAM scales and operational rates (iii) Projecting the achieved energy efficiency of the different targeted HD and CAM single-λ and WDM layouts. A detailed breakdown of the opto-electronic noise sources and different properties of the constituent photonic and electronic components incorporated in the analytical framework can be found in supplementary material section 3. Figure 6 (a) indicatively showcases the simulation framework’s projected error rates vs input laser power for HD and CAM operation, when targeting a single-λ 32x32 Xbar based layout, equivalent to a search word bit length of 16 (N/2) and a stored word capacity of 32 (N). The simulation results highlight: (a) The increased input laser power requirement when targeting high-rate operations, originating from the increased noise-bandwidth and as such noise profile of the photonic layout (b) Decreased input laser power requirements when targeting CAM-only operations i.e. the specific case of HD = 0. This decrease is attributed to the binomial statistical distribution of the power levels arising at the output of the HD photonic processor, originating from the actual and complementary nature of the input representation and the analog XOR operation between the input and target vector. (c) A different error-rate response when CAM-only operations are targeted, as highlighted by the black rectangle in Fig. 6 (a). This is due to the fact that the noise percentage characterizing the error-rate response of each signal level decreases more slowly, from the highest to the lowest power signal level, as the laser power increases. Additionally, since each signal level is associated with unequal probabilities of occurrence at the output of the system, this effect is reflected in the corresponding graphs (Detailed correlation is described in supplementary section 3). By setting an operational threshold comparable to the performance of state-of-the-art electronic CAM implementations (i.e. Error Rate of 10 − 3 [ 31 ]-[ 33 ]), we can derive the required single-λ input laser power for different scales and operational rates. Figure 6 (b) illustrates the required single-λ and 4-λ laser power for the HD, CAM architectures when targeting Xbar layouts with a search word bit length in the range of [2–64] and a stored word capacity range of [4-128]. These layouts correspond to Xbar scales of 4x4 to 128x128 for the single λ case, and 4x1 to 128x32 for the 4-λ case, as the 4λ WDM design effectively acts as a capacity enhancement factor of λ = 4. The derived results showcase that WDM layouts, using 4λ, for both CAM and HD designs, can offer significant insertion loss benefits as compared to the single-λ case (for more details see Supplementary Section 4), that can reach up to 20 dB when targeting 64-bit long search word and 128 stored word capacity for CAM operation at 20 Gb/s. Taking into account, that the currently maximum achievable power of an integrated laser source reaches approximately 22 dBm [ 37 ], the analysis also reveals that WDM designs can also significantly extend the currently achievable CAM designs to up to 64-bit long search words. Finally, Fig. 6 (c) puts in juxtaposition the achieved energy efficiency of single-λ and WDM CAM and HD layouts, taking into account the consumption of the constituent electro-optical components and the increased number of laser sources required for WDM layouts (For details see Supplementary Section 4). In Xbar scales where the required laser power surpasses the current practical limit i.e. >22 dBm, energy efficiency deteriorates because the total power consumption increases substantially and gets dominated by the laser's power requirements. The results also showcase the power consumption reduction properties of WDM layouts, that get even more significant as the targeted scale increases. This highlights the capabilities of photonic WDM CAM layouts to achieve down to 400 fJ/bit and 200 fJ/bit energy efficiencies, while reaching operating speeds of 20 Gb/s and 50 Gb/s, 20 and 50 times higher than state-of-the-art electronic counterparts [ 2 ],[ 38 ],[ 39 ],[ 40 ]. Methods Experimental Setups Single-wavelength 4x4 Xbar-based HD processor A tunable laser source (Santec TSL 550) is employed to generate a CW signal at the wavelength of 1563 nm. The operational wavelength has been appropriately selected to comply with the response of the grating couplers (GCs) and the EAMs, providing an optimal extinction ratio (ER), as well as insertion losses (ILs). The optical signal, is propagated into the 4×4 Χbar-based comparison structure within the PIC through an angled multi-port fiber array unit, retaining a constant TE polarization mode. The GCs of the integrated structure were found to have an IL of around 3.5 dB. After entering the structure, the signal is split (1x4 splitting stage) and gets injected into the four-search word vector EAMs, with an electro-optical (EO) bandwidth of 56 GHz. Each EAM is driven by a waveform generator (AWG Keysight M8194A), generating non-return-to-zero (NRZ) pseudo random bit sequences (PRBS 7 ) at 50 Gb/s, in order to emulate the incoming search vector information cases. The AWG generates the electrical signals with the channels having a power raging between [270–380 mV], for all the different cases of the 20 and 50 Gb/s, which were further amplified using RF amplifiers (SHF S804B), reaching the required ~ 1.9 Vpp to drive the EAM modules. A pair of EAMs was exploited to encode the information of a single search bit as a pair of complementary data, and as such the first pair of EAMs imprints the \(\:{\text{B}\text{i}\text{t}}_{1}\) and \(\:\stackrel{-}{{\text{B}\text{i}\text{t}}_{1}}\) , while the second pair the \(\:{\text{B}\text{i}\text{t}}_{2}\) and \(\:\stackrel{-}{{\text{B}\text{i}\text{t}}_{2}}\) values. The encoded search bits of the second EAM pair were time-shifted during the electrical signal generation stage relative to the first EAM pair, enabling the acquisition of all possible 2-bit combinations. The search vector values are propagated into the device, where the EAMs of the array are statically assigned to encode all the different binary and ternary vector values. Each optical signal at every Xbar output column, representing the logical comparison between the incoming search and statically assigned vectors, exits the optical chip via the same fiber array. It is then amplified by an EDFA, filtered through an optical band-pass filter (OBPF) with a 0.8 nm bandwidth, and directed to a 70 GHz photodiode (Finisar XPDV3120) before being recorded by a 75 GHz sampling oscilloscope (Keysight DCA-X N1000A). Moreover, the EAMs that were responsible for the generation of the search vector values have been reversely biased at voltages ranging between [-1.6, -1.4V] for 20 Gb/s, while the biasing values were ranging between [-1.6, -1.3] for the 50 Gb/s cases. In both operational cases the EAMs of the comparison cells were biased with either 0 or -4V. Furthermore, a 4th -order butterworth software-based filter was implemented via the OSC module and applied to the captured signals, with a manually adjusted 3 dB bandwidth for the 20 and 50 GHz, respectively, in order to mitigate the excess noise bandwidth response of the transmitting channel. Pattern correlation and error rate calculations were performed off-line. WDM Comparison cell Three TLSs are deployed to generate three CW signal beams at the wavelengths of, λ 1 = 1548.4 nm, λ 2 = 1558 nm and λ 3 = 1554.9 nm. The three signals are then multiplexed via a multiplexer (Mux) module (details about the design of (de)mux are given in supplementary material section 2), creating a WDM stream. The combined signal stream is amplified by an EDFA prior entering the chip, through an angled multi-fiber array. A constant TE mode is ensured for the signals upon entering to the respective GCs, via in-line polarization controllers during CW signal generation. The GCs are calculated to have ~ 4 dB of ILs. Within the optical chip, the WDM signal is split and directed to two input EAMs of the SVEU, each with an EO bandwidth of 56 GHz. Each input EAM was driven by an AWG (Keysight M8194A) to generate, as in the single wavelength case, 50 Gb/s PRBS 7 data sequences for the \(\:\text{B}\text{i}\text{t}\) and \(\:\stackrel{-}{\text{B}\text{i}\text{t}}\) complementary search value information. The generated electrical signals have amplitudes ranging between [260–370 mV], at the 20 Gb/s and 50 Gb/s cases, being amplified by RF amplifiers (SHF S804B), reaching the necessary voltage of ~ 1.9 Vpp to drive the EAMs. After the optical generation of the \(\:\text{B}\text{i}\text{t}\) and \(\:\stackrel{-}{\text{B}\text{i}\text{t}}\) signals, the WDM stream is propagated to the De-Mux components of each arm of the “outer” MZI structure. Every branch contains a demultiplexer (De-Mux 1 and De-Mux 2 ), which filters the incoming WDM stream up to three different paths, each containing a statically configured EAM and a PS. All possible combinations between the wavelengths (λ 1 = 1548.4 nm, λ 2 = 1558 nm, λ 3 = 1554.9 nm) and symbol values ( “0”, “1”, “X”) have been investigated. The optical signals are then multiplexed by the corresponding multiplexers (Mux 1 and Mux 2 ) and the two recombined WDM streams are constructively interfered before exiting the Xbar through a single output port. The output of the photonic crossbar is filtered to each wavelength-constituent and was amplified via an EDFA, followed by a BPF with 0.8 nm bandwidth prior entering a 70 GHz PD (Finisar XPDV3120) and being recorded by a 75 GHz OSC (Keysight DCA-X N1000A). Additionally, the EAMs used for the search bit’s information have been reversely biased at voltages between [-1.5, -1.2V] for all the cases of the 20 and 50 Gb/s, while the EAMs that were used for the statically configured cells have been biased at 0 or -3V. As before, a software-based 4th -order butterworth filter is implemented and applied via the OSC upon receiving the signals, with manually adjusting a 3 dB bandwidth of 20 or 50 GHz in order to mitigate the excess noise response of the PD. Pattern correlation and Q-factor calculations were performed off-line. Declarations Competing interest The authors declare no competing interest. Author contributions T. Moschos, C. Pappas, and N. Pleros conceived the experiment. T. Moschos, C. Pappas, S. Kovaios, I. Roumpos and A. Prapas deployed the experimental setups for the 4x4 and the WDM Xbar prototypes, performed the experiments and processed the experimental results. T. Moschos, A. Tsakyridis, M. Moralis-Pegios and C. Vagionas performed the simulation analyses. Y. London, T. Van Vaerenbergh and B. Tossoun contributed to the discussion on the original idea and on the organization of the results and the manuscript. All authors discussed the results and wrote the manuscript. Acknowledgements This work was supported by the European Commission (EC) through the H2020 projects GATEPOST (101120938) and OCTAPUS (101070009). Data Availability All the data that support the results and findings of the study, as well as all the validation methods and procedures, are available upon request. References R. S. Williams, "What's Next? [The end of Moore's law]," in Computing in Science & Engineering, vol. 19, no. 2, pp. 7–13, Mar.-Apr. 2017, doi: 10.1109/MCSE.2017.31 R. Mao, et al., “Experimentally validated memristive memory augmented neural network with efficient hashing and similarity search,” Nature Communications, vol. 13, no. 1, Oct. 2022, doi: 10.1038/s41467-022-33629-7 . P. R. Prucnal, B. J. Shastri, T. Ferreira de Lima, M. A. Nahmias, and A. N. Tait, “Recent progress in semiconductor excitable lasers for photonic spike processing,” Adv. Opt. Photon., vol. 8, no. 2, pp. 228–299, 2016. Moralis-Pegios, M., Giamougiannis, G., Tsakyridis, A. et al. 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Wang, et al., "A Novel Multi-Context Non-Volatile Content-Addressable Memory Cell and Multi-Level Architecture for High Reliability and Density," 2021 IEEE 10th Non-Volatile Memory Systems and Applications Symposium (NVMSA) , Beijing, China, 2021, pp. 1–6, doi: 10.1109/NVMSA53655.2021.9628720 . A. Totovic, et al., "WDM equipped universal linear optics for programmable neuromorphic photonic processors," Neuromorphic Computing and Engineering, 2022, doi: 10.1088/2634-4386/ac724d . A. Totovic et al., “Programmable photonic neural networks combining WDM with coherent linear optics,” Sci. Rep. 12, 5605 (2022). P. De Heyn, et al., "Fabrication-Tolerant Four-Channel Wavelength-Division-Multiplexing Filter Based on Collectively Tuned Si Microrings," Journal of Lightwave Technology, vol. 31, pp. 2785–2792, 2013. DOI: 10.1109/JLT.2013.2273391 . Jörn P. Epping, et. al."Hybrid integrated silicon nitride lasers", Proc. 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Supplementary Files supplementarymaterialNonlinearOpticalVectorProcessingat50GbsusingLinearSiliconPhotonicCircuits.docx Nonlinear Optical Vector Processing at 50 Gbs using Linear Silicon Photonic Circuits Cite Share Download PDF Status: Published Journal Publication published 17 Dec, 2025 Read the published version in Nature Communications → Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-5928777","acceptedTermsAndConditions":true,"allowDirectSubmit":false,"archivedVersions":[],"articleType":"Article","associatedPublications":[],"authors":[{"id":412945782,"identity":"ee37ba5c-b0e0-47d8-b25b-2c03b968e510","order_by":0,"name":"Theodoros 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States)","correspondingAuthor":false,"prefix":"","firstName":"Thomas","middleName":"Van","lastName":"Vaerenbergh","suffix":""},{"id":412945793,"identity":"6a50a0b7-6c5c-49b6-9f21-81b0a116a69a","order_by":11,"name":"Nikos Pleros","email":"","orcid":"","institution":"Aristotle University of Thessaloniki","correspondingAuthor":false,"prefix":"","firstName":"Nikos","middleName":"","lastName":"Pleros","suffix":""}],"badges":[],"createdAt":"2025-01-30 08:50:10","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-5928777/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-5928777/v1","draftVersion":[],"editorialEvents":[{"content":"https://doi.org/10.1038/s41467-025-66286-7","type":"published","date":"2025-12-17T05:00:00+00:00"}],"editorialNote":"","failedWorkflow":false,"files":[{"id":76644899,"identity":"b90cf67f-997d-48ca-84fa-0647f18eec73","added_by":"auto","created_at":"2025-02-19 08:48:51","extension":"png","order_by":1,"title":"Figure 1","display":"","copyAsset":false,"role":"figure","size":268208,"visible":true,"origin":"","legend":"\u003cp\u003e(a) Illustrative example of the HD metric, when applied to two N-length binary vectors X and Y, (b) Digital Electronic HD circuit, implemented by XOR comparison gates and an Adder Tree N-symbol length comparison and (c) Analog Electronic implementation of the HD operation using Memristive elements (d) Analog photonic HD circuit, based on amplitude modulators and coherent light summation (e) Parallel analog photonic HD processor based on a coherent Xbar array.\u003c/p\u003e","description":"","filename":"1.png","url":"https://assets-eu.researchsquare.com/files/rs-5928777/v1/a268533c6641104351798c79.png"},{"id":76644901,"identity":"c1e4fdbc-1e51-457c-8968-29f9f22e8c0a","added_by":"auto","created_at":"2025-02-19 08:48:51","extension":"png","order_by":2,"title":"Figure 2","display":"","copyAsset":false,"role":"figure","size":382724,"visible":true,"origin":"","legend":"\u003cp\u003e(a) Microscope photo of the integrated 4x4 crossbar prototype comparison unit. Inset: Single Xbar comparison cell, consisting of two EAMs and two TO PSs. The search vector encoding unit and the 4x4 crossbar, are marked with yellow and orange rectangles, respectively, (b) Experimental testbed for the HD comparison operation at 20 and 50 Gb/s, highlighting the search vector encoding unit (yellow) and the 4x4 Xbar-based HD processor (orange), along with the respective comparison cells (red). A DC control plane is employed for biasing the static EAMs and PSs located in the Xbar layout.\u003c/p\u003e","description":"","filename":"2.png","url":"https://assets-eu.researchsquare.com/files/rs-5928777/v1/62b30e7d7cdda18a92729526.png"},{"id":76645994,"identity":"5107c376-6eed-42ca-944a-91f53a556ace","added_by":"auto","created_at":"2025-02-19 08:56:51","extension":"png","order_by":3,"title":"Figure 3","display":"","copyAsset":false,"role":"figure","size":598158,"visible":true,"origin":"","legend":"\u003cp\u003e(a) Synchronized time traces (50 ps/div) showing 10 encoded search bits (Bit\u003csub\u003e1\u003c/sub\u003e-Bit\u003csub\u003e2\u003c/sub\u003e) along with the respective comparison outcomes with the target vector cases of “00”-“XX”, (b) Corresponding eye diagrams at 20 Gb/s operation, (c) Synchronized time traces (20 ps/div) of 10 optically encoded search bits (Bit\u003csub\u003e1\u003c/sub\u003e-Bit\u003csub\u003e2\u003c/sub\u003e) and comparison contents and (d) Εye diagrams at 50 Gb/s operation. (e) Error-rates of all cases at 20 Gb/s, (f) Error rates when the processor operates at 50 Gb/s. MER: Match Error Rate, SER: Symbol Error Rate\u003c/p\u003e","description":"","filename":"3.png","url":"https://assets-eu.researchsquare.com/files/rs-5928777/v1/6414c2a96b2be94cc282ca12.png"},{"id":76645995,"identity":"a0ab70d5-3e0c-4d10-bdbb-555263059d26","added_by":"auto","created_at":"2025-02-19 08:56:52","extension":"png","order_by":4,"title":"Figure 4","display":"","copyAsset":false,"role":"figure","size":457572,"visible":true,"origin":"","legend":"\u003cp\u003eSee image above for figure legend.\u003c/p\u003e","description":"","filename":"4.png","url":"https://assets-eu.researchsquare.com/files/rs-5928777/v1/73a8342880f762414b4fe3bc.png"},{"id":76646504,"identity":"f6a87d40-36a9-415b-8616-41f5d3977085","added_by":"auto","created_at":"2025-02-19 09:04:52","extension":"png","order_by":5,"title":"Figure 5","display":"","copyAsset":false,"role":"figure","size":467369,"visible":true,"origin":"","legend":"\u003cp\u003eSee image above for figure legend.\u003c/p\u003e","description":"","filename":"55.png","url":"https://assets-eu.researchsquare.com/files/rs-5928777/v1/e0d59f4d1d00d8bd55e6eed0.png"},{"id":76648065,"identity":"f7aff2b8-1616-4887-bf18-3130c3c869f9","added_by":"auto","created_at":"2025-02-19 09:12:52","extension":"png","order_by":6,"title":"Figure 6","display":"","copyAsset":false,"role":"figure","size":234378,"visible":true,"origin":"","legend":"\u003cp\u003e(a) Projected Error Rates for a 32x32 Xbar implementation at 20 and 50 Gb/s operation. The CAM operation refers to the specific HD case HD=0, and as such is correlated to the MER metric, while the HD case is correlated to the SER metric. The operational threshold is set based on state-of-the-art electronic counterparts (b) Required single-λ laser power for HD,CAM and WDM layouts. The horizontal axis is expressed in search word length (bit) / stored word capacity, in order to provide similar capacity points for single and multi-λ layout comparison. The laser limit refers to the currently achievable maximum power in integrated photonics. (c) Energy efficiency for single-λ and WDM HD and CAM layouts at 20 Gb/s. The respective results for 50 Gb/s operation can be found in Supplementary material section 4.\u003c/p\u003e","description":"","filename":"6.png","url":"https://assets-eu.researchsquare.com/files/rs-5928777/v1/dc8ad4071376e26dea05286c.png"},{"id":99212995,"identity":"8ee09001-a71a-4cc3-875a-e2725bb9f211","added_by":"auto","created_at":"2025-12-30 08:37:10","extension":"pdf","order_by":0,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":2799875,"visible":true,"origin":"","legend":"","description":"","filename":"manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-5928777/v1/f6cbcd54-51e8-4928-87cd-7d1488b88762.pdf"},{"id":76645998,"identity":"3a60a4e9-69d2-43c6-977a-70406ed4e403","added_by":"auto","created_at":"2025-02-19 08:56:52","extension":"docx","order_by":1,"title":"","display":"","copyAsset":false,"role":"supplement","size":4139336,"visible":true,"origin":"","legend":"Nonlinear Optical Vector Processing at 50 Gbs using Linear Silicon Photonic Circuits","description":"","filename":"supplementarymaterialNonlinearOpticalVectorProcessingat50GbsusingLinearSiliconPhotonicCircuits.docx","url":"https://assets-eu.researchsquare.com/files/rs-5928777/v1/99b72047d0620abca63dea85.docx"}],"financialInterests":"There is \u003cb\u003eNO\u003c/b\u003e Competing Interest.","formattedTitle":"Nonlinear Optical Vector Processing at 50 Gbs using Linear Silicon Photonic Circuits","fulltext":[{"header":"Introduction","content":"\u003cp\u003eThe demand for high-speed and energy-efficient computing continues to rise with the proliferation of data-intensive applications, such as machine learning, genomic analysis, and real-time communication [\u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e]. In this race, digital electronic systems comprise still the steam engine in today\u0026rsquo;s computational landscape, though analog electronics are also gaining momentum as a viable alternative for energy efficient computations directly in the analog domain [\u003cspan citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e]. However, as data rates and dataset sizes continue to grow, electronic computing in both its digital and analog versions is facing diminishing returns due to the native physical constraints of electronic technology: the size and energy advantages of electronic circuitry are naturally counteracted by the speed and power limits of the electronic interconnects inside the circuits due to RC parasitic effects [\u003cspan citationid=\"CR3\" class=\"CitationRef\"\u003e3\u003c/span\u003e], with current electronic processors hardly exceeding GHz clock frequencies. These limitations indicate that a radical shift from conventional electronic computing architectures towards novel hardware computing paradigms need to be realized.\u003c/p\u003e \u003cp\u003eIn this direction, silicon photonics (SiPho) emerge as a promising candidate for penetrating the processing and compute domains to turn their well-known dominance in the interconnect sector into a profound advantage also in the computational segment. Migrating, however, into a light-enabled processor technology paradigm has to ensure the successful deployment of fundamental computing operations at both symbol- and vector-/ string-level in the optical domain. In this realm, photonics have already shown an impressive potential in implementing universal linear transformations over analog optical vectors [\u003cspan additionalcitationids=\"CR5 CR6 CR7\" citationid=\"CR4\" class=\"CitationRef\"\u003e4\u003c/span\u003e]-[\u003cspan citationid=\"CR8\" class=\"CitationRef\"\u003e8\u003c/span\u003e], facilitating critical matrix and tensor multiplier building blocks in application fields like quantum [\u003cspan citationid=\"CR9\" class=\"CitationRef\"\u003e9\u003c/span\u003e],[\u003cspan citationid=\"CR10\" class=\"CitationRef\"\u003e10\u003c/span\u003e], neuromorphic [\u003cspan additionalcitationids=\"CR12 CR13 CR14 CR15\" citationid=\"CR11\" class=\"CitationRef\"\u003e11\u003c/span\u003e]-[\u003cspan citationid=\"CR16\" class=\"CitationRef\"\u003e16\u003c/span\u003e] and microwave photonics [\u003cspan citationid=\"CR17\" class=\"CitationRef\"\u003e17\u003c/span\u003e],[\u003cspan citationid=\"CR18\" class=\"CitationRef\"\u003e18\u003c/span\u003e]. However, a broad range of applications like pattern matching, error correction and similarity searches require nonlinear processing functions like comparison and distance calculation processes between strings. These necessitate typically the use of memory and register blocks that are certainly not yet among the strengths of the photonic circuitry [\u003cspan citationid=\"CR19\" class=\"CitationRef\"\u003e19\u003c/span\u003e][\u003cspan citationid=\"CR20\" class=\"CitationRef\"\u003e20\u003c/span\u003e]. The calculation of string metrics, like the well-known Hamming Distance (HD), provides critical quantitative information about string and vector similarity [\u003cspan citationid=\"CR21\" class=\"CitationRef\"\u003e21\u003c/span\u003e], with certain distance values leading often to completely new functional blocks. Content Addressable Memories (CAMs), for example, form a specialized yet highly important pattern matching application [\u003cspan citationid=\"CR22\" class=\"CitationRef\"\u003e22\u003c/span\u003e] that correspond to a zero HD and constitute a critical element in high-speed routers, address and database lookups, and associative search functions [\u003cspan citationid=\"CR23\" class=\"CitationRef\"\u003e23\u003c/span\u003e]. Although optical CAMs experienced a significant progress during the last decade [\u003cspan additionalcitationids=\"CR25\" citationid=\"CR24\" class=\"CitationRef\"\u003e24\u003c/span\u003e]-[\u003cspan citationid=\"CR26\" class=\"CitationRef\"\u003e26\u003c/span\u003e] and raised expectations even for complete high-speed look-up operations via silicon photonic Microring Resonator- (MRRs) [\u003cspan citationid=\"CR27\" class=\"CitationRef\"\u003e27\u003c/span\u003e] or electro-absorption modulator-based (EAM) setups [\u003cspan citationid=\"CR28\" class=\"CitationRef\"\u003e28\u003c/span\u003e], the transition from the specific vector matching to the more generic nonlinear processes like vector distance calculation has still not identified a viable photonic implementation route that would broaden the computational portfolio of integrated optics.\u003c/p\u003e \u003cp\u003eIn this paper, we introduce for the first time, to the best of our knowledge, the nonlinear transformation of optical vectors by using a linear SiPho circuit and demonstrate HD calculation and CAM operation between binary optical strings at record-high data rates of 50 Gb/s. The processor relies on the recently introduced Crossbar (Xbar) architecture [\u003cspan citationid=\"CR5\" class=\"CitationRef\"\u003e5\u003c/span\u003e], configured as a 4x4 matrix arrangement and employing 56 GHz bandwidth silicon germanium (SiGe) EAMs as its core computational cells. Its performance was experimentally evaluated in calculating the HD between 2-bit optical vectors, presenting also successful operation as optical CAM and Ternary CAM (TCAM) memory bank for 2-bit optical words with matching error-rates of ~\u0026thinsp;10\u003csup\u003e\u0026minus;\u0026thinsp;3\u003c/sup\u003e at operational speeds 2.5x higher than current state-of-the-art CAMs clock speed. Moreover, we introduce a viable roadmap for increasing computational capacity by using space-wavelength multiplexed memory cells, demonstrating experimentally a wavelength division multiplexing (WDM)-enabled architecture that encodes optical vectors across a 2D space-wavelength dimension and performs vector processing at 50 Gb/s.\u003c/p\u003e"},{"header":"Results","content":"\u003cdiv id=\"Sec3\" class=\"Section2\"\u003e \u003ch2\u003eHamming Distance Calculation using a silicon photonic Xbar PIC\u003c/h2\u003e \u003cp\u003eHD is a metric widely used in information theory as a measure of difference between two vectors/strings of equal length. It is a nonlinear operation defined as the number of positions at which the corresponding symbols (characters or bits) differ. An illustrative example of its application is depicted in Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003e (a), where the HD metric is applied to two N-length binary vectors X and Y. Mathematically the HD operation is defined by the following equation:\u003cdiv id=\"Equ1\" class=\"Equation\"\u003e\u003cdiv format=\"TEX\" class=\"mathdisplay\" id=\"FileID_Equ1\" name=\"EquationSource\"\u003e\n$$\\:HD\\:\\left(X,Y\\right)=\\sum\\:_{i=1}^{N}L(X\\left(i\\right)\\ne\\:Y\\left(i\\right))$$\u003c/div\u003e\u003cdiv class=\"EquationNumber\"\u003e1\u003c/div\u003e\u003c/div\u003e\u003c/p\u003e \u003cp\u003ewith the function \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:L(X\\left(i\\right)\\ne\\:Y\\left(i\\right))\\)\u003c/span\u003e\u003c/span\u003e indicating all the positions in the N-length vectors X and Y where their corresponding values differ. The most prominent implementation of the HD operator in digital electronics comprises a XOR-gate array, followed by a Full-Adder Tree, as schematically illustrated in Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003e (b) [\u003cspan citationid=\"CR29\" class=\"CitationRef\"\u003e29\u003c/span\u003e]. Implementing this nonlinear HD calculation process via linear transformations can be realized by doubling the vector dimensions to incorporate also the inverted vector values and applying a dot product operation, as has been initially demonstrated via a rather low-speed analog electronic HD circuitry, depicted in Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003e (c) [\u003cspan citationid=\"CR21\" class=\"CitationRef\"\u003e21\u003c/span\u003e]. In this layout, the actual and complementary values of array Y are programmed in a memristor array, while the X actual and complementary values are injected as Voltage signals across the memristor array. The resulting output current is, due to Kirchhoff\u0026rsquo;s law, directly correlated to the HD of the input X and Y vectors.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eThe employment of this mathematical concept and the transfer of the memristor-based architectural approach into the photonic domain can be realized by adopting an equivalent analog optical circuit, as depicted in Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003e(d) and 1(e), by: (i) Encoding the X actual and complementary vector values into a modulated optical light carrier (ii) Encoding the Y actual and complementary values in the transmission values of optical amplitude modulators, which can be assumed to act as optical memory cells that store the corresponding transmission value, (iii) Injecting the encoded X modulated light beams to the Y amplitude modulating elements and adding coherently the resulting optical fields, with the basic building block of this operation being the Comparison Cell highlighted in Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003e (d) (details for its functionality are provided in Supplementary section 1). The basic analog photonic HD circuitry that performs a dot product operation between two optical vectors has been initially presented in [\u003cspan citationid=\"CR30\" class=\"CitationRef\"\u003e30\u003c/span\u003e] and is shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003e(d). This can be expanded to a parallel HD processor by employing the coherent Xbar architecture, originally proposed in [\u003cspan citationid=\"CR5\" class=\"CitationRef\"\u003e5\u003c/span\u003e] and depicted in Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003e(e). In this layout the X actual and complementary values are equally broadcasted to the corresponding M Xbar columns using directional couplers, with properly selected splitting ratios. Each column of the Xbar is configured to hold different predefined/target vectors, with each comparison cell assigned to a distinct symbol value. Hence, the HD operation between the incoming X vector and the respective target #M Y Vectors of the Xbar array, is executed in parallel across all Xbar columns allowing up to M parallel HD calculations.\u003c/p\u003e \u003cp\u003eThe functionality of the proposed analog photonic HD processor architecture was assessed via a 4\u0026times;4 SiPho integrated Xbar layout that is capable of 2-bit vector distance processing. The photonic chip was fabricated in imec\u0026rsquo;s SiPho platform, using PDK-ready components. Particularly, every computing cell of the Xbar prototype incorporates 50 \u0026micro;m-long, 56 GHz Franz-Keldysh (FK) SiGe EAMs and 170 \u0026micro;m-long thermo-optic phase shifters (TO-PSs). The deployed photonic integrated circuit (PIC) supports 2-bit search vectors, encoded through the search vector encoding unit (SVEU), highlighted with the yellow rectangle in Fig.\u0026nbsp;\u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e2\u003c/span\u003e (a), that utilizes four EAMs to generate two pairs of complementary search values. The encoded search information is then forwarded into the Xbar-based HD processor, with the corresponding chip area marked with an orange rectangle. The optical signals are distributed across all Xbar columns, which statically encode all the target vectors at every EAM column. The HD result (\u0026ldquo;match\u0026rdquo; / degree of \u0026ldquo;mismatch\u0026rdquo;) between the search and target vectors is generated at each Xbar output column. The experimental testbed, established for the evaluation of the HD operations, is depicted in Fig.\u0026nbsp;\u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e2\u003c/span\u003e (b). A tunable laser source (TLS) is employed to generate a continuous wave (CW) optical signal at 1563 nm which is injected into the 4\u0026times;4 Xbar chip. A 4-channel arbitrary waveform generator (AWG) is used to generate the 2-bit electrical search vector. The first and third channel produces the \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{\\text{B}\\text{i}\\text{t}}_{1}\\)\u003c/span\u003e\u003c/span\u003e and \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{\\text{B}\\text{i}\\text{t}}_{2}\\)\u003c/span\u003e\u003c/span\u003e, respectively, while the second and fourth channels generates their complementary values, i.e. \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:\\stackrel{-}{{\\text{B}\\text{i}\\text{t}}_{1}}\\)\u003c/span\u003e\u003c/span\u003e and \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:\\stackrel{-}{{\\text{B}\\text{i}\\text{t}}_{2}}\\)\u003c/span\u003e\u003c/span\u003e. After electrical amplification, the electrical signals are fed into the input EAMs (yellow rectangle) to encode the optical SVEU. The target 2-bit vectors (i.e., \u0026ldquo;00\u0026rdquo;, \u0026ldquo;01\u0026rdquo;, \u0026ldquo;10\u0026rdquo; and \u0026ldquo;11\u0026rdquo;) are implemented by setting the optical attenuation of EAMs located at each Xbar row. Thermo-optic phase shifters are deployed to ensure constructive interference at the output columns of the Xbar. Both EAMs and TO PSs are controlled by a multi-channel DC control plane. The output of each column is captured by an oscilloscope, after being amplified and detected by a photodiode. More details of the experimental setup can be found in methods section.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003c/div\u003e\n\u003ch3\u003eExperimental Validation of Hamming Distance calculation and TCAM Memory Bank at 50 Gb/s\u003c/h3\u003e\n\u003cp\u003eThe performance of the proposed parallel HD processor was experimentally assessed with 2-bit optical vectors encoded onto the SVEU and compared with respective 2-bit optical vectors stored onto the four Xbar columns. The case of HD\u0026thinsp;=\u0026thinsp;0 designates an exact vector matching and corresponds to the ML operation of a complete CAM memory bank, with the incoming optical vector representing the search word and the stored optical vectors the respective address words. The photonic comparison cells are used for representing all the memory states of a Binary CAM cell, i.e. \u0026ldquo;0\u0026rdquo;, \u0026ldquo;1\u0026rdquo;, but can also support the wildcard/ternary value \u0026ldquo;X\u0026rdquo; by storing a zero-transmission value to both EAMs within the comparison cell, allowing in this way for an extension to ternary CAM (TCAM) applications.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eThe HD and ML operations performed through the Xbar processor have been experimentally validated for search vector streams at 20 Gb/s and 50 Gb/s. Figure\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003e (a) and (c) illustrate the time sequences of the 2-bit optical vector within the first two rows of the figure for a 10-bit time window at 20 Gb/s and 50 Gb/s operation, respectively, with the additional rows depicting the respective time sequences obtained at the Xbar column output port when the column stored content matches the designated Target Vector. The corresponding eye diagrams for every time sequence are shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003e(b) and (d), respectively. For all cases, the cross-shaped scatter points indicate the optimum sampling points, corresponding to one of the three possible output states of the HD operation i.e. HD\u0026thinsp;=\u0026thinsp;0 (ML operation), HD\u0026thinsp;=\u0026thinsp;1, and HD\u0026thinsp;=\u0026thinsp;2. Particularly, the green highlighted area showcases the principle of operation for a search vector value of \u0026lsquo;01\u0026rsquo;, that corresponds to Bit\u003csub\u003e1\u003c/sub\u003e and Bit\u003csub\u003e2\u003c/sub\u003e values of \u0026lsquo;0\u0026rsquo; and \u0026lsquo;1\u0026rsquo;, respectively. A logical \u0026ldquo;match\u0026rdquo; state occurs, only when compared with the target vectors of \u0026ldquo;01\u0026rdquo;, \u0026ldquo;0X\u0026rdquo;, \u0026ldquo;X1\u0026rdquo; and \u0026ldquo;XX\u0026rdquo;. As expected, this results in a \u0026ldquo;zero\u0026rdquo; output power (HD\u0026thinsp;=\u0026thinsp;0), since the wildcard value \u0026ldquo;X\u0026rdquo; represents a \u0026ldquo;don\u0026rsquo;t care state\u0026rdquo; leading to a logical \u0026ldquo;match\u0026rdquo; regardless of the corresponding search value. On the other hand, if the compared vectors have different values, the comparison operation indicates a logical \u0026ldquo;mismatch\u0026rdquo;, resulting in an HD\u0026thinsp;\u0026gt;\u0026thinsp;0. Specifically, if only one of the two search bits matches the content of the Xbar array, the HD is \u0026ldquo;1\u0026rdquo; (HD\u0026thinsp;=\u0026thinsp;1). Conversely, if none of the search bits match the array values, the HD is \u0026ldquo;2\u0026rdquo; (HD\u0026thinsp;=\u0026thinsp;2), as illustrated in the case of the \u0026ldquo;10\u0026rdquo; time trace.\u003c/p\u003e \u003cp\u003eThe performance of the 4x4 vector processor was assessed by calculating the projected symbol error rate (SER), when HD calculation is targeted, and the match error rate (MER) when optical CAM operation is intended, for each different target vector case. The SER quantifies the HD performance, while the MER specifically refers to the error rate of the \u0026lsquo;0\u0026rsquo; level that corresponds solely to the matching functionality without accounting for the degree of mismatch (for more details see supplementary material section 3). Figure\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003e (e) and (f) illustrate the calculated MER and SER when the Xbar HD processor operates at 20 Gb/s and 50 Gb/s, respectively. As can be observed, all error-rates are in the order of 10\u003csup\u003e\u0026minus;\u0026thinsp;3\u003c/sup\u003e, comparable with the performance achieved by electronic HD and CAM computing cells [\u003cspan additionalcitationids=\"CR32\" citationid=\"CR31\" class=\"CitationRef\"\u003e31\u003c/span\u003e]-[\u003cspan citationid=\"CR33\" class=\"CitationRef\"\u003e33\u003c/span\u003e]. The results indicate a degradation in both SER/MER measurements as the data rate increases, primarily due to noise arising from the limited frequency response of the deployed electro-optic components. Finally, it is worth mentioning that when the wildcard \u0026lsquo;X\u0026rsquo; is included, the output signals are restricted to two levels and MER becomes equivalent to SER, resulting at the same time in improved performance compared to 3-level signals.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003e \u003cb\u003eWDM-Enabled Comparison Cell Architecture for Scalable HD Processor Layouts\u003c/b\u003e \u003c/p\u003e \u003cp\u003eIn the previous section, we validated the capabilities of the coherent Xbar architecture in performing HD operations between vectors by leveraging spatially distributed comparison cells and the interference properties of a single coherent light beam. Synergizing the WDM capabilities of the Xbar architecture [\u003cspan citationid=\"CR34\" class=\"CitationRef\"\u003e34\u003c/span\u003e],[\u003cspan citationid=\"CR35\" class=\"CitationRef\"\u003e35\u003c/span\u003e], with the HD architectural approach, can offer an additional axis of computational capacity at a reduced insertion loss budget (for more information see supplementary material section 4), thereby enhanced energy efficiency. Figure\u0026nbsp;\u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003e (a) illustrates the proposed WDM-enabled comparison cell. The actual and complementary search vector symbol (\u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:Bit\\)\u003c/span\u003e\u003c/span\u003e and \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:\\stackrel{-}{Bit}\\)\u003c/span\u003e\u003c/span\u003e) are used to modulate two multi-wavelength light beams. The resulting modulated streams are demultiplexed to their wavelength constituents via a demultiplexer [\u003cspan citationid=\"CR36\" class=\"CitationRef\"\u003e36\u003c/span\u003e], with each wavelength propagating through an intensity modulator (IM) that encodes a value from the target vector. The resulting signals are subsequently multiplexed [\u003cspan citationid=\"CR36\" class=\"CitationRef\"\u003e36\u003c/span\u003e] and coherently recombined on a wavelength basis via constructive interference, achieved using TO PSs. Finally, the output is demultiplexed, with each wavelength carrying the dot-product between the assigned symbol and the search bit value. Further information about the functionality of the WDM-based cell is presented in supplementary material section 1. This WDM-enabled comparison cell facilitates the parallel execution of HD operations within a single output, where the number of wavelengths represents the level of parallelism. In order to validate the advantages of the WDM-enabled approach a 3λ-2x1 comparison cell was fabricated using the same technological building blocks (i.e. EAM and TO-PS) as in the 4x4 Xbar. A microscope photo of the fabricated chip is depicted in Fig.\u0026nbsp;\u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003e (b), while the circuit schematic of the WDM-enabled chip along with the experimental setup used to assess its performance in executing HD operations are presented in Fig.\u0026nbsp;\u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003e (c). Additional information about the experimental testbed of the WDM-enabled HD chip can be found in the methods section.\u003c/p\u003e \u003cp\u003eThe experimental validation of the proposed WDM-enabled HD processor was conducted at data rates of 20 and 50 Gb/s, employing 3 different wavelengths. Figure\u0026nbsp;\u003cspan refid=\"Fig5\" class=\"InternalRef\"\u003e5\u003c/span\u003e (a) depicts indicative 10-bit long time traces at 20 Gb/s operation for the search \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:\\text{B}\\text{i}\\text{t}\\)\u003c/span\u003e\u003c/span\u003e and \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:\\stackrel{-}{\\text{B}\\text{i}\\text{t}}\\)\u003c/span\u003e\u003c/span\u003e values encoded in all three wavelengths (λ\u003csub\u003e1\u003c/sub\u003e, λ\u003csub\u003e2\u003c/sub\u003e and λ\u003csub\u003e3\u003c/sub\u003e) and the target Values \u0026lsquo;0\u0026rsquo;, \u0026lsquo;1\u0026rsquo; and \u0026lsquo;X\u0026rsquo; indicatively encoded at wavelengths (λ\u003csub\u003e1\u003c/sub\u003e, λ\u003csub\u003e2\u003c/sub\u003e and λ\u003csub\u003e3\u003c/sub\u003e) respectively. Figure\u0026nbsp;\u003cspan refid=\"Fig5\" class=\"InternalRef\"\u003e5\u003c/span\u003e (b) illustrates their respective eye diagrams. The green highlighted area focuses on the case of the search value of logical \u0026ldquo;0\u0026rdquo;, meaning the \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:\\text{B}\\text{i}\\text{t}\\)\u003c/span\u003e\u003c/span\u003e value is \u0026ldquo;0\u0026rdquo; and the \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:\\stackrel{-}{\\text{B}\\text{i}\\text{t}}\\)\u003c/span\u003e\u003c/span\u003e is \u0026ldquo;1\u0026rdquo;. As observed, when the search value is compared with the target symbol \u0026ldquo;0\u0026rdquo;, the HD circuit output is zero (HD\u0026thinsp;=\u0026thinsp;0), meaning that a logical \u0026ldquo;match\u0026rdquo; state is acquired. Conversely, when the target symbol is \u0026ldquo;1\u0026rdquo;, the HD\u0026thinsp;=\u0026thinsp;1 indicating a \u0026ldquo;mismatch\u0026rdquo;. For TCAM operation, when the target symbol is the wildcard \u0026ldquo;X\u0026rdquo;, the output power remains always at zero level, signifying a match with any incoming search value. Similarly, Fig.\u0026nbsp;\u003cspan refid=\"Fig5\" class=\"InternalRef\"\u003e5\u003c/span\u003e (c) and (d) present the respective time traces and eye diagrams, when the WDM-enabled processor operates at 50 Gb/s, revealing successful HD/TCAM functionality. In view of evaluating the performance at 20 and 50 Gb/s, Fig.\u0026nbsp;\u003cspan refid=\"Fig5\" class=\"InternalRef\"\u003e5\u003c/span\u003e (e) and (f) depict the acquired Q factor values for both the actual and supplementary input (\u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:\\text{B}\\text{i}\\text{t}\\)\u003c/span\u003e\u003c/span\u003e and \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:\\stackrel{-}{\\text{B}\\text{i}\\text{t}}\\)\u003c/span\u003e\u003c/span\u003e ) along with the results when targets \u0026lsquo;1\u0026rsquo; and \u0026lsquo;0\u0026rsquo; are sequentially encoded to different available wavelength cells. Similarly to the single-λ 4x4 Xbar layout, the 50 Gb/s cases exhibit a performance degradation compared to the 20 Gb/s, stemming from the bandwidth limitation of the deployed electro-optic components.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e"},{"header":"Discussion","content":"\u003cp\u003eFollowing the experimental validation of photonic Xbar-based CAM and HD implementations at up to 50 Gb/s and 3λ parallel layouts, we proceed by developing an analytical framework capable of : (i) Assessing the theoretical error rate performance of Xbar-based HD and CAM-layouts for different scales, operational rates and injected laser powers (ii) Quantifying the required single-λ laser power for different HD, CAM and WDM HD and CAM scales and operational rates (iii) Projecting the achieved energy efficiency of the different targeted HD and CAM single-λ and WDM layouts. A detailed breakdown of the opto-electronic noise sources and different properties of the constituent photonic and electronic components incorporated in the analytical framework can be found in supplementary material section 3.\u003c/p\u003e \u003cp\u003eFigure \u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e (a) indicatively showcases the simulation framework\u0026rsquo;s projected error rates vs input laser power for HD and CAM operation, when targeting a single-λ 32x32 Xbar based layout, equivalent to a search word bit length of 16 (N/2) and a stored word capacity of 32 (N). The simulation results highlight: (a) The increased input laser power requirement when targeting high-rate operations, originating from the increased noise-bandwidth and as such noise profile of the photonic layout (b) Decreased input laser power requirements when targeting CAM-only operations i.e. the specific case of HD\u0026thinsp;=\u0026thinsp;0. This decrease is attributed to the binomial statistical distribution of the power levels arising at the output of the HD photonic processor, originating from the actual and complementary nature of the input representation and the analog XOR operation between the input and target vector. (c) A different error-rate response when CAM-only operations are targeted, as highlighted by the black rectangle in Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(a). This is due to the fact that the noise percentage characterizing the error-rate response of each signal level decreases more slowly, from the highest to the lowest power signal level, as the laser power increases. Additionally, since each signal level is associated with unequal probabilities of occurrence at the output of the system, this effect is reflected in the corresponding graphs (Detailed correlation is described in supplementary section 3). By setting an operational threshold comparable to the performance of state-of-the-art electronic CAM implementations (i.e. Error Rate of 10\u003csup\u003e\u0026minus;\u0026thinsp;3\u003c/sup\u003e [\u003cspan additionalcitationids=\"CR32\" citationid=\"CR31\" class=\"CitationRef\"\u003e31\u003c/span\u003e]-[\u003cspan citationid=\"CR33\" class=\"CitationRef\"\u003e33\u003c/span\u003e]), we can derive the required single-λ input laser power for different scales and operational rates.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eFigure \u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e (b) illustrates the required single-λ and 4-λ laser power for the HD, CAM architectures when targeting Xbar layouts with a search word bit length in the range of [2\u0026ndash;64] and a stored word capacity range of [4-128]. These layouts correspond to Xbar scales of 4x4 to 128x128 for the single λ case, and 4x1 to 128x32 for the 4-λ case, as the 4λ WDM design effectively acts as a capacity enhancement factor of λ\u0026thinsp;=\u0026thinsp;4. The derived results showcase that WDM layouts, using 4λ, for both CAM and HD designs, can offer significant insertion loss benefits as compared to the single-λ case (for more details see Supplementary Section 4), that can reach up to 20 dB when targeting 64-bit long search word and 128 stored word capacity for CAM operation at 20 Gb/s. Taking into account, that the currently maximum achievable power of an integrated laser source reaches approximately 22 dBm [\u003cspan citationid=\"CR37\" class=\"CitationRef\"\u003e37\u003c/span\u003e], the analysis also reveals that WDM designs can also significantly extend the currently achievable CAM designs to up to 64-bit long search words. Finally, Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e (c) puts in juxtaposition the achieved energy efficiency of single-λ and WDM CAM and HD layouts, taking into account the consumption of the constituent electro-optical components and the increased number of laser sources required for WDM layouts (For details see Supplementary Section 4). In Xbar scales where the required laser power surpasses the current practical limit i.e. \u0026gt;22 dBm, energy efficiency deteriorates because the total power consumption increases substantially and gets dominated by the laser's power requirements. The results also showcase the power consumption reduction properties of WDM layouts, that get even more significant as the targeted scale increases. This highlights the capabilities of photonic WDM CAM layouts to achieve down to 400 fJ/bit and 200 fJ/bit energy efficiencies, while reaching operating speeds of 20 Gb/s and 50 Gb/s, 20 and 50 times higher than state-of-the-art electronic counterparts [\u003cspan citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e],[\u003cspan citationid=\"CR38\" class=\"CitationRef\"\u003e38\u003c/span\u003e],[\u003cspan citationid=\"CR39\" class=\"CitationRef\"\u003e39\u003c/span\u003e],[\u003cspan citationid=\"CR40\" class=\"CitationRef\"\u003e40\u003c/span\u003e].\u003c/p\u003e"},{"header":"Methods","content":"\u003cdiv id=\"Sec7\" class=\"Section2\"\u003e \u003ch2\u003eExperimental Setups\u003c/h2\u003e \u003cdiv id=\"Sec8\" class=\"Section3\"\u003e \u003ch2\u003eSingle-wavelength 4x4 Xbar-based HD processor\u003c/h2\u003e \u003cp\u003eA tunable laser source (Santec TSL 550) is employed to generate a CW signal at the wavelength of 1563 nm. The operational wavelength has been appropriately selected to comply with the response of the grating couplers (GCs) and the EAMs, providing an optimal extinction ratio (ER), as well as insertion losses (ILs). The optical signal, is propagated into the 4\u0026times;4 Χbar-based comparison structure within the PIC through an angled multi-port fiber array unit, retaining a constant TE polarization mode. The GCs of the integrated structure were found to have an IL of around 3.5 dB. After entering the structure, the signal is split (1x4 splitting stage) and gets injected into the four-search word vector EAMs, with an electro-optical (EO) bandwidth of 56 GHz. Each EAM is driven by a waveform generator (AWG Keysight M8194A), generating non-return-to-zero (NRZ) pseudo random bit sequences (PRBS\u003csup\u003e7\u003c/sup\u003e) at 50 Gb/s, in order to emulate the incoming search vector information cases. The AWG generates the electrical signals with the channels having a power raging between [270\u0026ndash;380 mV], for all the different cases of the 20 and 50 Gb/s, which were further amplified using RF amplifiers (SHF S804B), reaching the required\u0026thinsp;~\u0026thinsp;1.9 Vpp to drive the EAM modules. A pair of EAMs was exploited to encode the information of a single search bit as a pair of complementary data, and as such the first pair of EAMs imprints the \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{\\text{B}\\text{i}\\text{t}}_{1}\\)\u003c/span\u003e\u003c/span\u003e and \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:\\stackrel{-}{{\\text{B}\\text{i}\\text{t}}_{1}}\\)\u003c/span\u003e\u003c/span\u003e, while the second pair the \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{\\text{B}\\text{i}\\text{t}}_{2}\\)\u003c/span\u003e\u003c/span\u003e and \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:\\stackrel{-}{{\\text{B}\\text{i}\\text{t}}_{2}}\\)\u003c/span\u003e\u003c/span\u003e values. The encoded search bits of the second EAM pair were time-shifted during the electrical signal generation stage relative to the first EAM pair, enabling the acquisition of all possible 2-bit combinations. The search vector values are propagated into the device, where the EAMs of the array are statically assigned to encode all the different binary and ternary vector values. Each optical signal at every Xbar output column, representing the logical comparison between the incoming search and statically assigned vectors, exits the optical chip via the same fiber array. It is then amplified by an EDFA, filtered through an optical band-pass filter (OBPF) with a 0.8 nm bandwidth, and directed to a 70 GHz photodiode (Finisar XPDV3120) before being recorded by a 75 GHz sampling oscilloscope (Keysight DCA-X N1000A). Moreover, the EAMs that were responsible for the generation of the search vector values have been reversely biased at voltages ranging between [-1.6, -1.4V] for 20 Gb/s, while the biasing values were ranging between [-1.6, -1.3] for the 50 Gb/s cases. In both operational cases the EAMs of the comparison cells were biased with either 0 or -4V. Furthermore, a 4th -order butterworth software-based filter was implemented via the OSC module and applied to the captured signals, with a manually adjusted 3 dB bandwidth for the 20 and 50 GHz, respectively, in order to mitigate the excess noise bandwidth response of the transmitting channel. Pattern correlation and error rate calculations were performed off-line.\u003c/p\u003e \u003cp\u003e \u003cspan type=\"Underline\" class=\"Underline\" name=\"Emphasis\"\u003eWDM Comparison cell\u003c/span\u003e \u003c/p\u003e \u003cp\u003eThree TLSs are deployed to generate three CW signal beams at the wavelengths of, λ\u003csub\u003e1\u003c/sub\u003e\u0026thinsp;=\u0026thinsp;1548.4 nm, λ\u003csub\u003e2\u003c/sub\u003e\u0026thinsp;=\u0026thinsp;1558 nm and λ\u003csub\u003e3\u003c/sub\u003e\u0026thinsp;=\u0026thinsp;1554.9 nm. The three signals are then multiplexed via a multiplexer (Mux) module (details about the design of (de)mux are given in supplementary material section 2), creating a WDM stream. The combined signal stream is amplified by an EDFA prior entering the chip, through an angled multi-fiber array. A constant TE mode is ensured for the signals upon entering to the respective GCs, via in-line polarization controllers during CW signal generation. The GCs are calculated to have ~\u0026thinsp;4 dB of ILs. Within the optical chip, the WDM signal is split and directed to two input EAMs of the SVEU, each with an EO bandwidth of 56 GHz. Each input EAM was driven by an AWG (Keysight M8194A) to generate, as in the single wavelength case, 50 Gb/s PRBS\u003csup\u003e7\u003c/sup\u003e data sequences for the \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:\\text{B}\\text{i}\\text{t}\\)\u003c/span\u003e\u003c/span\u003e and \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:\\stackrel{-}{\\text{B}\\text{i}\\text{t}}\\)\u003c/span\u003e\u003c/span\u003e complementary search value information. The generated electrical signals have amplitudes ranging between [260\u0026ndash;370 mV], at the 20 Gb/s and 50 Gb/s cases, being amplified by RF amplifiers (SHF S804B), reaching the necessary voltage of ~\u0026thinsp;1.9 Vpp to drive the EAMs. After the optical generation of the \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:\\text{B}\\text{i}\\text{t}\\)\u003c/span\u003e\u003c/span\u003e and \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:\\stackrel{-}{\\text{B}\\text{i}\\text{t}}\\)\u003c/span\u003e\u003c/span\u003e signals, the WDM stream is propagated to the De-Mux components of each arm of the \u0026ldquo;outer\u0026rdquo; MZI structure. Every branch contains a demultiplexer (De-Mux\u003csub\u003e1\u003c/sub\u003e and De-Mux\u003csub\u003e2\u003c/sub\u003e), which filters the incoming WDM stream up to three different paths, each containing a statically configured EAM and a PS. All possible combinations between the wavelengths (λ\u003csub\u003e1\u003c/sub\u003e\u0026thinsp;=\u0026thinsp;1548.4 nm, λ\u003csub\u003e2\u003c/sub\u003e\u0026thinsp;=\u0026thinsp;1558 nm, λ\u003csub\u003e3\u003c/sub\u003e\u0026thinsp;=\u0026thinsp;1554.9 nm) and symbol values ( \u0026ldquo;0\u0026rdquo;, \u0026ldquo;1\u0026rdquo;, \u0026ldquo;X\u0026rdquo;) have been investigated. The optical signals are then multiplexed by the corresponding multiplexers (Mux\u003csub\u003e1\u003c/sub\u003e and Mux\u003csub\u003e2\u003c/sub\u003e) and the two recombined WDM streams are constructively interfered before exiting the Xbar through a single output port. The output of the photonic crossbar is filtered to each wavelength-constituent and was amplified via an EDFA, followed by a BPF with 0.8 nm bandwidth prior entering a 70 GHz PD (Finisar XPDV3120) and being recorded by a 75 GHz OSC (Keysight DCA-X N1000A). Additionally, the EAMs used for the search bit\u0026rsquo;s information have been reversely biased at voltages between [-1.5, -1.2V] for all the cases of the 20 and 50 Gb/s, while the EAMs that were used for the statically configured cells have been biased at 0 or -3V. As before, a software-based 4th -order butterworth filter is implemented and applied via the OSC upon receiving the signals, with manually adjusting a 3 dB bandwidth of 20 or 50 GHz in order to mitigate the excess noise response of the PD. Pattern correlation and Q-factor calculations were performed off-line.\u003c/p\u003e \u003c/div\u003e \u003c/div\u003e"},{"header":"Declarations","content":"\u003ch2\u003eCompeting interest\u003c/h2\u003e \u003cp\u003eThe authors declare no competing interest.\u003c/p\u003e\u003ch2\u003eAuthor contributions\u003c/h2\u003e \u003cp\u003eT. Moschos, C. Pappas, and N. Pleros conceived the experiment. T. Moschos, C. Pappas, S. Kovaios, I. Roumpos and A. Prapas deployed the experimental setups for the 4x4 and the WDM Xbar prototypes, performed the experiments and processed the experimental results. T. Moschos, A. Tsakyridis, M. Moralis-Pegios and C. Vagionas performed the simulation analyses. Y. London, T. Van Vaerenbergh and B. Tossoun contributed to the discussion on the original idea and on the organization of the results and the manuscript. All authors discussed the results and wrote the manuscript.\u003c/p\u003e\u003ch2\u003eAcknowledgements\u003c/h2\u003e \u003cp\u003eThis work was supported by the European Commission (EC) through the H2020 projects GATEPOST (101120938) and OCTAPUS (101070009).\u003c/p\u003e\n\u003ch3\u003eData Availability\u003c/h3\u003e\n\u003cp\u003eAll the data that support the results and findings of the study, as well as all the validation methods and procedures, are available upon request.\u003c/p\u003e"},{"header":"References","content":"\u003col\u003e\u003cli\u003e\u003cspan\u003eR. S. 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Park, \"Low Cost Ternary Content Addressable Memory Using Adaptive Matchline Discharging Scheme,\" 2018 \u003cem\u003eIEEE International Symposium on Circuits and Systems (ISCAS)\u003c/em\u003e, Florence, Italy, 2018, pp. 1\u0026ndash;4, doi: \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003e10.1109/ISCAS.2018.8351461\u003c/span\u003e\u003cspan address=\"10.1109/ISCAS.2018.8351461\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e.\u003c/span\u003e\u003c/li\u003e\u003c/ol\u003e"}],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":true,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":true,"hideJournal":false,"highlight":"","institution":"","isAcceptedByJournal":true,"isAuthorSuppliedPdf":false,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":false,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"nature-portfolio","isNatureJournal":true,"hasQc":false,"allowDirectSubmit":false,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"","title":"Nature Portfolio","twitterHandle":"","acdcEnabled":false,"dfaEnabled":false,"editorialSystem":"ejp","reportingPortfolio":"","inReviewEnabled":true,"inReviewRevisionsEnabled":false},"keywords":"","lastPublishedDoi":"10.21203/rs.3.rs-5928777/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-5928777/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eThe need for high-speed, energy-efficient computing in machine learning and real-time communication necessitates innovations beyond conventional digital and analog electronics to sustain computational power advances without requiring prohibitive energy amounts. Photonics has emerged as a promising platform demonstrating significant highlights in the field of linear transformations. Adopting, however, the use of photons within a broad range of computing applications necessitates their successful employment also in nonlinear vector processing and matching functionalities, which still continue to comprise the stronghold of electronics. In this direction, we demonstrate nonlinear optical vector processing in the form of Hamming Distance (HD) calculation and Content Addressable Memory (CAM) bank operations using linear optical circuits on Silicon photonics (SiPho) at a record-high-speed of 50 Gb/s, enabling advances in pattern matching, error-correction and look-up tables. The processor employs a 4\u0026times;4 crossbar architecture with 56 GHz SiGe electro-absorption modulators to compute HD between 2-bit optical vectors. It achieves error-rates of ~\u0026thinsp;10⁻\u0026sup3; in CAM and ternary CAM applications that correspond to zero HD, improving state-of-the-art CAM speed performance by \u0026gt;\u0026thinsp;2.5x. Scalability is enhanced by employing space-wavelength multiplexing schemes via a WDM-enabled SiPho processor cell, which is experimentally demonstrated at 50 Gb/s and offers the potential to increase the computational capacity in a reduced insertion loss and power consumption envelope. The realization of HD calculation and CAM matchline operations via linear optical transformations can pave the inroad towards implementing additional nonlinear optical vector transformation processes at high data-rates via linear silicon photonic circuits, like the calculation of Euclidean distance and Cosine distance metrics.\u003c/p\u003e","manuscriptTitle":"Nonlinear Optical Vector Processing at 50 Gbs using Linear Silicon Photonic Circuits","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2025-02-19 08:48:47","doi":"10.21203/rs.3.rs-5928777/v1","editorialEvents":[],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"nature-communications","isNatureJournal":true,"hasQc":false,"allowDirectSubmit":false,"externalIdentity":"NCOMMS","sideBox":"Learn more about [Nature Communications](http://www.nature.com/ncomms/)","snPcode":"","submissionUrl":"https://mts-ncomms.nature.com/","title":"Nature Communications","twitterHandle":"","acdcEnabled":true,"dfaEnabled":true,"editorialSystem":"ejp","reportingPortfolio":"Nature Communications","inReviewEnabled":true,"inReviewRevisionsEnabled":false}}],"origin":"","ownerIdentity":"39f0d609-f816-4ed4-b15d-b6492c020856","owner":[],"postedDate":"February 19th, 2025","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"published-in-journal","subjectAreas":[{"id":44038436,"name":"Physical sciences/Optics and photonics/Optical materials and structures/Silicon photonics"},{"id":44038437,"name":"Physical sciences/Optics and photonics/Applied optics/Integrated optics"}],"tags":[],"updatedAt":"2025-12-30T08:37:03+00:00","versionOfRecord":{"articleIdentity":"rs-5928777","link":"https://doi.org/10.1038/s41467-025-66286-7","journal":{"identity":"nature-communications","isVorOnly":false,"title":"Nature Communications"},"publishedOn":"2025-12-17 05:00:00","publishedOnDateReadable":"December 17th, 2025"},"versionCreatedAt":"2025-02-19 08:48:47","video":"","vorDoi":"10.1038/s41467-025-66286-7","vorDoiUrl":"https://doi.org/10.1038/s41467-025-66286-7","workflowStages":[]},"version":"v1","identity":"rs-5928777","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-5928777","identity":"rs-5928777","version":["v1"]},"buildId":"8U1c8b4HqxoKbykW_rLl7","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}