Design and Simulation of 1.9GHz Phase-Locked Loop Clock Generator with 45nm Generic CMOS (For High speed Serial Link Applications)

Design and Simulation of 1.9GHz Phase-Locked Loop Clock Generator with 45nm Generic CMOS (For High speed Serial Link Applications) | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Design and Simulation of 1.9GHz Phase-Locked Loop Clock Generator with 45nm Generic CMOS (For High speed Serial Link Applications) Amrita Adhikari, Ankur Beohar This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-6587493/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract The demand for high-speed serial links (HSSLs) is increasing rapidly due to the need for faster, more robust, and more power-efficient inter-IC communication. HSSLs are used in a variety of applications, including data centers, networking, and high-performance computing. A key component of an HSSL is the clock generator, which provides a low-jitter, low-phase-noise clock signal that is essential for reliable data transmission. This paper presents the design and simulation of a phase-locked loop (PLL) based clock generator for HSSL applications. The PLL is designed to generate a 1.9 GHz clock signal with a considerably low phase noise and low jitter. The design is implemented in a 45nm Generic CMOS process and is simulated using Cadence Virtuoso tools. The simulation results show that the PLL meets the desired specifications and is suitable for HSSL applications. High-speed serial link phase-locked loop clock generator jitter phase noise 45nm Generic CMOS Cadence Virtuoso Full Text Additional Declarations No competing interests reported. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-6587493","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":455497002,"identity":"8b1508da-8a9f-4977-8334-9ae16ae7ff91","order_by":0,"name":"Amrita Adhikari","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAABJElEQVRIiWNgGAWjYJCCA0AsJw8kJBIMJHjs2xuATAML/FqAeowNgQolHlTYyBjwgIwwkCBoTWIDkJB8cCbNxkAiASSGWwv/tLMPD3+oYWBsnHbG8EZi22Eec8nnVzf8KJBg4G/vTsCmReJ2usGBA8cYmNmlc4wtQFosZ+eU3ewBOkzizNkNWK25nQb0CxsDG+PstDQJkBaG2zlpN3iAWgwkcrFqkQdr+ccAVAnTcvNM2s0/eLQYgLQcbAP69nbyMYmEM2k8BjfYj93GZ4shSMvZPgkDw9nJhy0SKmx4JHty2G7LACMIl1/kbqcxf6j4ZlM/Xzqx8eYPAwl7fvbjz26++WMjx9/ei9370IBD5vAYgEk8yjEA+wNSVI+CUTAKRsHwBwDTdGjBlGSDlQAAAABJRU5ErkJggg==","orcid":"","institution":"VIT Bhopal University","correspondingAuthor":true,"prefix":"","firstName":"Amrita","middleName":"","lastName":"Adhikari","suffix":""},{"id":455497003,"identity":"c07542cc-a0b4-44bf-8430-58e736e6e6e5","order_by":1,"name":"Ankur Beohar","email":"","orcid":"","institution":"VIT Bhopal University","correspondingAuthor":false,"prefix":"","firstName":"Ankur","middleName":"","lastName":"Beohar","suffix":""}],"badges":[],"createdAt":"2025-05-04 08:53:04","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-6587493/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-6587493/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":84161601,"identity":"ff0f1e6b-01e3-4cca-a121-6d99b21e375a","added_by":"auto","created_at":"2025-06-08 14:17:10","extension":"pdf","order_by":1,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":597145,"visible":true,"origin":"","legend":"","description":"","filename":"Amrita23MVD10015PLLHSSLresearchpaper.pdf","url":"https://assets-eu.researchsquare.com/files/rs-6587493/v1_covered_bb40cf30-5c82-4a06-bda4-d4e7a99c025b.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"Design and Simulation of 1.9GHz Phase-Locked Loop Clock Generator with 45nm Generic CMOS (For High speed Serial Link Applications)","fulltext":[],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":false,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":true,"highlight":"","institution":"","isAcceptedByJournal":false,"isAuthorSuppliedPdf":true,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":true,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"High-speed serial link, phase-locked loop, clock generator, jitter, phase noise, 45nm Generic CMOS, Cadence Virtuoso","lastPublishedDoi":"10.21203/rs.3.rs-6587493/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-6587493/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"The demand for high-speed serial links (HSSLs) is increasing rapidly due to the need for faster, more robust, and more power-efficient inter-IC communication. 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