ATOMiK: Empirical Validation of Delta-State Computationwith Hardware Verification

ATOMiK: Empirical Validation of Delta-State Computationwith Hardware Verification | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Article ATOMiK: Empirical Validation of Delta-State Computationwith Hardware Verification Matthew Rockwell This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-8790663/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract Delta-state algebra was recently formalized and verified in the Lean4 proof assistant, establishing the theoretical foundations for computation based on composable state differences rather than persistent state. While 92 theorems proved the mathematical properties of this approach - including closure, commutativity, and Turing completeness - the practical performance implications remained empirical questions. We present a comprehensive validation of delta-state computation through two methodologies: (1) software benchmarks comparing ATOMiK against traditional state-centric architectures across 360 measurements spanning 9 workloads. (2) FPGA hardware implementation validating single-cycle operation and algebraic properties in silicon. Results demonstrate a 95-100% in memory traffic reduction across all workloads, with write-heavy operations achieving 22-55% execution time improvements. Critically, hardware implementation eliminates software observed reconstruction overhead, achieving uniform single-cycle latency (10.6 ns @ 94.5 MHz) for all operations - LOAD, ACCUMULATE, and READ. The commutative property enables 85% parallel efficiency, impossible in traditional architectures. All algebraic properties from the formal proofs are validated in silicon (10/10 hardware tests passing on Gowin GW1NR-9FPGA). To our knowledge, this represents the first delta-state architecture to demonstrate theory-to-silicon validation with uniform read/write performance, establishing that the software-observed read penalty is an implementation artifact, not a fundamental limitation. Physical sciences/Engineering Physical sciences/Mathematics and computing Physical sciences/Physics Delta-state algebra hardware acceleration formal verification FPGA memory effi- ciency parallel computation Full Text Additional Declarations No competing interests reported. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. 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Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-8790663","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Article","associatedPublications":[],"authors":[{"id":608430334,"identity":"4b0907b3-7037-4a77-b147-1c6b5287f5c6","order_by":0,"name":"Matthew Rockwell","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAABFUlEQVRIie3SMUvDQBTA8RcO7pYXuwaU+AmEhEBU/DItQqYUHB2KFgLnUpwFv4STc+AwXQJZD7JEDhycCgHp1PaSUkRMA91E7j88brgfdwcHYDL90UgzvHaZAhwxoic4Jz3ASn4QSuiwIXgIwXa9l5w9FHN1cyvgHOz3apkLV5P6U04uEJh4e+kgYX5tJU+5gMspC/yZFAEl9utVnOmLYRTJLpJqYvMSvJTSY1iUI65JEFNNHAw7SaE0WX2Te07wI4hXPUQ2p0x3RJZD/RaixryPKP8ZszV6ghJ/lq99TmhIxo8O0n1vKUZVjZPI9ebcqpZZdDpgiarjrzt3wETWRXbh9g9so047e7b/iiwO2W0ymUz/vg3Ja11Vrp2mWQAAAABJRU5ErkJggg==","orcid":"","institution":"Rockwell Industries","correspondingAuthor":true,"prefix":"","firstName":"Matthew","middleName":"","lastName":"Rockwell","suffix":""}],"badges":[],"createdAt":"2026-02-04 23:08:13","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-8790663/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-8790663/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":105035047,"identity":"46d1af44-5485-494c-b1bf-52ea812226f1","added_by":"auto","created_at":"2026-03-20 07:25:21","extension":"pdf","order_by":1,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":325714,"visible":true,"origin":"","legend":"","description":"","filename":"Paper2ATOMiKBenchmarksSubmissionUpdated.pdf","url":"https://assets-eu.researchsquare.com/files/rs-8790663/v1_covered_48562061-6120-4c4c-a65e-3393c2fd9183.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"ATOMiK: Empirical Validation of Delta-State Computationwith Hardware Verification","fulltext":[],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":false,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":true,"hideJournal":true,"highlight":"","institution":"","isAcceptedByJournal":false,"isAuthorSuppliedPdf":true,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":true,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"Delta-state algebra, hardware acceleration, formal verification, FPGA, memory effi- ciency, parallel computation","lastPublishedDoi":"10.21203/rs.3.rs-8790663/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-8790663/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"Delta-state algebra was recently formalized and verified in the Lean4 proof assistant, establishing the theoretical foundations for computation based on composable state differences rather than persistent state. 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