FPGA Design and Implementation for Montgomery Multiplication Algorithm Using MATLAB HDL Coder

FPGA Design and Implementation for Montgomery Multiplication Algorithm Using MATLAB HDL Coder | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article FPGA Design and Implementation for Montgomery Multiplication Algorithm Using MATLAB HDL Coder Ghada Elsayed, Eman Abass This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-5069431/v1 This work is licensed under a CC BY 4.0 License Status: Published Journal Publication published 23 Dec, 2024 Read the published version in Bulletin of the National Research Centre → Version 1 posted 3 You are reading this latest preprint version Abstract Background: Modular multiplication for large numbers is very important in cryptography algorithms such as RSA and Elliptic curves. The Montgomery algorithm is the most famous and efficient one for calculating it. Hardware implementation for cryptography co-processors is better than software implementation in terms of speed and security. Many FPGA Designs for the Montgomery Multiplication algorithm was published based on hardware description languages like VERILOG and VHDL. This paper proposes the FPGA Design and implementation using MATLAB HDL Coder. Results: We modified the algorithm such that it can fit any small/Large FPGA by introducing scaling factor. The design is configurable in both modulus length and the scaling factor. This paper performs a comparison between the synthesizing results for different scales and for different modulus lengths. We synthesized up to 8K bit modulus length and we can increase it easily. In this paper we can implement different modulus lengths with different frequencies and with different area utilization. The design utilizes different area resources for each configuration. The target is xc7vx330t-2ffg1157 Virtex-7 Xilinx FPGA. The maximum frequency is 80.81MHz for 4K bit modulus length with 8-bit data width and 2 serialization factor. The minimum area utilization is achieved for minimum configurations i.e. 1kbit modulus length with 8-bit data width and for unity serialization factor. Conclusions: In this paper, we propose an efficient and configurable FPGA Design for Montgomery Multiplication Co-processor based HDL coder design. FPGA MATLAB HDL Coder Cryptographic co-processors Full Text Cite Share Download PDF Status: Published Journal Publication published 23 Dec, 2024 Read the published version in Bulletin of the National Research Centre → Version 1 posted Reviewers invited by journal 11 Oct, 2024 Editor assigned by journal 08 Oct, 2024 First submitted to journal 07 Oct, 2024 You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-5069431","acceptedTermsAndConditions":true,"allowDirectSubmit":false,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":365079712,"identity":"68ada284-cd24-4622-89ed-d2ba9b35a19a","order_by":0,"name":"Ghada Elsayed","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAABLklEQVRIie3QsUrDQBjA8S8UmuUgm5yk2le4cFAp0eZVctyQJYLQJUOHg0K6BFxv8CXEF4gE4hLQMYKDIjh1yCQdSrGXVCxyzSyY/xC+hPz4LgHo6vqDWRIAA5yquQfV7mmqbg6Fy5rQmhgSGtpKCN4jPbQj0Ers+Vu5AjI8WySUnkcvE3H0eJ9C5DJhLp60ZJDTcQLEuSkKysPigwubbw9WBEyg4kpHnNIfYQRrQ+KQZpdxxkERI86YwKGv3VIGn8drIF5NxptvstmS4fIACUc2AsIU4YbIJg0RaouZ6gguw6k7IIRLlE+dJM/8vs1J6ucBjVGo/WOWDG6flxG5kOb8Dq9mmWfZ7L2qZu7JtfnwqjXN8X5GFqur+og+IKJ//Vfe3my2bOnq6ur6R30B1ABgLJ/pdsIAAAAASUVORK5CYII=","orcid":"https://orcid.org/0000-0002-3802-5620","institution":"British University in Egypt","correspondingAuthor":true,"prefix":"","firstName":"Ghada","middleName":"","lastName":"Elsayed","suffix":""},{"id":365079713,"identity":"6ca07bec-6e00-49fe-a8a7-02207483a8f3","order_by":1,"name":"Eman Abass","email":"","orcid":"","institution":"Modern University For Technology and Information","correspondingAuthor":false,"prefix":"","firstName":"Eman","middleName":"","lastName":"Abass","suffix":""}],"badges":[],"createdAt":"2024-09-11 08:24:46","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-5069431/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-5069431/v1","draftVersion":[],"editorialEvents":[{"content":"https://doi.org/10.1186/s42269-024-01285-0","type":"published","date":"2024-12-23T15:57:48+00:00"}],"editorialNote":"","failedWorkflow":false,"files":[{"id":72641147,"identity":"08e3ab69-4205-4638-9652-b0d01f17ccdd","added_by":"auto","created_at":"2024-12-30 16:11:09","extension":"pdf","order_by":1,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":1523037,"visible":true,"origin":"","legend":"","description":"","filename":"BNRCD2400728.pdf","url":"https://assets-eu.researchsquare.com/files/rs-5069431/v1_covered_b128abea-dff3-4e09-9dc3-90e4916f310f.pdf"}],"financialInterests":"","formattedTitle":"FPGA Design and Implementation for Montgomery Multiplication Algorithm Using MATLAB HDL Coder","fulltext":[],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":false,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":false,"highlight":"","institution":"","isAcceptedByJournal":true,"isAuthorSuppliedPdf":true,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":true,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"bulletin-of-the-national-research-centre","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":false,"externalIdentity":"bnrc","sideBox":"Learn more about [Bulletin of the National Research Centre](https://BNRC.springeropen.com)","snPcode":"42269","submissionUrl":"https://submission.springernature.com/new-submission/42269/3","title":"Bulletin of the National Research Centre","twitterHandle":"","acdcEnabled":true,"dfaEnabled":true,"editorialSystem":"stoa","reportingPortfolio":"Springer Open","inReviewEnabled":true,"inReviewRevisionsEnabled":true},"keywords":"FPGA, MATLAB HDL Coder, Cryptographic co-processors","lastPublishedDoi":"10.21203/rs.3.rs-5069431/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-5069431/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eBackground: Modular multiplication for large numbers is very important in cryptography algorithms such as RSA and Elliptic curves. The Montgomery algorithm is the most famous and efficient one for calculating it. Hardware implementation for cryptography co-processors is better than software implementation in terms of speed and security. Many FPGA Designs for the Montgomery Multiplication algorithm was published based on hardware description languages like VERILOG and VHDL. This paper proposes the FPGA Design and implementation using MATLAB HDL Coder.\u0026nbsp;\u003c/p\u003e\n\u003cp\u003eResults: We modified the algorithm such that it can fit any small/Large FPGA by introducing scaling factor. The design is configurable in both modulus length and the scaling factor. This paper performs a comparison between the synthesizing results for different scales and for different modulus lengths. We synthesized up to 8K bit modulus length and we can increase it easily. In this paper we can implement different modulus lengths with different frequencies and with different area utilization. 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