VLSI Implementation of Radix Binary Coded Decimal Multiplier using Reversible Logic

VLSI Implementation of Radix Binary Coded Decimal Multiplier using Reversible Logic | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article VLSI Implementation of Radix Binary Coded Decimal Multiplier using Reversible Logic Hamirdhavalle DV, K. N. Vijeyakumar, K.R. Prem This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-3568596/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract In CMOS design, conventional logic design plays a vital role. Even though, irrespective of its many advantages, it lacks efficiency in terms of speed, area, power, and delay leading to much heat dissipation and delay on circuit design. Therefore, in replacement of conventional digital computers, Reversible logic acts as a promising technology that can improve the standard of the circuits in terms of power, speed, area, heat dissipation, lifespan, and input traceability. In this project, we propose a high-speed reversible radix binary-coded decimal multiplier (HS-RBCDM) and a Power Enhanced- High speed reversible binary-coded decimal multiplier (HS-RBCDMPE) each efficient in terms of speed, power and area respectively. In comparison with recent designs, the proposed methodology gives a single gate level architecture for multiple multiplicand generator (MMG) and reversible adder and a Radix-recoder for converting 8221 to 4221 codes for HS-RBCDM that achieves low power dissipation and shifting operation using copying gate instead of MMG for HS-RBCDMPE to achieve high-speed reducing delay in the circuit and area efficiency. The proposed multipliers HS-RBCDM and HS-RBCDMPE is designed with 90- nm ASIC technology using the Cadence EDA tool and is compared with state-of-art reversible BCD algorithm. Performance evaluations of the proposed designs compared with recent proposed methods reveals that the proposed HS-RBCDM multiplier and HS-RBCDMPE achieves 64.9% and 69.6% Area reduction, 51.3% and 71.9% Delay reduction and 52.6% and PDP reduction respectively. Binary Coded Decimal Radix Re-coder Reversible gates Quantum computing Power-Delay Product Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 1. Introduction In computing and electronic systems, Binary Coded Decimal (BCD) is a class of binary encodings of decimal numbers where each digit is represented by a fixed number of bits, usually four or eight. BCD is still used with Real Time Clocks (RTC) chips to keep track of wall-clock time and it’s becoming more common for embedded microprocessors to include an RTC. Adder and Multiplier are main components of any BCD processing unit. BCD multiplier is the critical component that consumes more hardware area, dissipate more power, and exhibit high critical delay in design of BCD processing unit [ 7 ]. Reversible logic that recovers inputs from the outputs is a suitable alternative to design low power systems. Hence in this work, an attempt is made to design high speed area efficient BCD multiplier [ 25 ] for portable processing units using reversible logic. The proposed High-Speed Binary-Coded Decimal Multiplier (HS-RBCDM) incorporates structural modifications to the RR-BCDM design [ 18 ]. Evaluations of RR-BCDM revealed that the MMG unit contributes for high delay and gate count due to series of reversible gates in each multiple generation. However, the proposed design achieves area and speed efficiency using single gate level structure for each multiple multiplicand generation. The further enhancements done to the HS-RBCDM in terms of PDP reduction is achieved using a single gate level block for unit multiple generation and generating the higher multiples with a right shift operation in HS-RBCDM PE . In rest of the paper, Section 2 elaborates the basic reversible logic gates. Section 3 illustrates a detailed discussion of the proposed methodology. In Section 4 , the proposed reversible radix binary-coded multiplier is compared with previous proposed designs. Further, Section 5 compares the quantum matrices and power, delay comparison with previous designs. 2. Overview of basic Reversible Logic Gates Reversible logic is one of the alternative paradigm that reduces heat dissipation and delay logic depth in a circuit. It is been recognized as a memory less logic element that realize a one-to-one logic function. Reversible gates consist of equal number of inputs and outputs for the traceability of input from output and vice versa. Fan out is attained in reversible logic. The important parameters backing the design of reversible circuits are garbage outputs (GO), quantum cost (QC) and constant inputs (CI). The quantum cost of a reversible circuit is the number of 1x1 and 2x2 quantum gates that are used to construct the circuit. Constant inputs (CI) are the number of inputs that are to be maintaining constant at either 0 or 1 in order to synthesize the logical function. Garbage outputs are the ones that are neither the primary outputs nor the ones required for further computation. The following subsections discuss the reversible logic gates in detail. 2.1 Feynman Gate (FG) A 2*2 Feynman gate [ 22 ] shown in Fig. 2.1 does the logical XOR function. The quantum cost of FG is 1. The Boolean expression defining the logic of the FG is given by Eq. (2.1) and Eq. (2.2). Symbol ^ represents the logic EXOR operation. 2.2 Fredkin Gate (FRG) Figure 2.2 shows the logic diagram and quantum representation of 3*3 Reversible FRG [ 23 ], The inputs and outputs are defined by A, B, C and P, Q, R respectively. FRG performs as a reversible multiplexer and is used in data selection applications. The Boolean expressions representing the working of FRG are given in Eq. (2.3) to Eq. (2.5). P = A (2.3) Q = (A&(~ B)) | (A&C) (2.4) R = (A&B) | (A&(~ C)) (2.5) Note from Eq. (2.3) to Eq. (2.5) that for logic low on ‘A’ input, the outputs are viz., Q = B, and R = C. When ‘A’ is logic high then the outputs are viz., Q = Cand R = B. Note from the Quantum diagram shown in Fig. 2.2(b) FRG demonstrates QC of 5. Fredkin gate not only act as reversible multiplexer it also performs different Boolean operations viz., COPY, SWAP, AND, and OR. 2.3 Peres Gate (PG) 3x3 PG [ 24 ] performs Copy, XOR, AND, NAND and NOR operations as shown in Table 4.1. It is noted from Fig. 2.3 that PG has A, B, C as inputs and P, Q, R as outputs as shown in Eq. (2.6) to Eq. (2.8). The output Q produces the Sum and output R produces the Carry. If C input is logic low, XOR operation of A and B occur at Q output and “&” operation of A and B occurs at R output. The quantum cost of PG is 4. P = A (2.6) Q = A^B (2.7) R = (A&B)^C (2.8) 3. Proposed Reversible BCD Multiplier This section briefs in detail the design of High-Speed Reversible Radix Binary-Coded Decimal Multiplier (HS-RBCDM) and Enhanced High-Speed Reversible Radix Binary-Coded Decimal Multiplier (HS-RBCDM PE ). The design consists reversible preprocessing unit [RPU] for 4221 radix recoding developed using RRG as in of [ 1 ]. The reversible multiple generation block (RMGB) and Compression unit designed using reversible accumulation unit [RAU] for multiplication is shown in Fig. 3.1 . The HS-BCDM is designed using PG, FRG and FG gates. The following subsections give a detailed illustration on the various block functions of the proposed multiplier. A. HS-RBCDM 3.1 Reversible Preprocessing Unit Among various binary codes like gray code, 4221, 2421, excess-3 code and 8421, the 4221 binary code has been chosen to be appropriate code for BCD representation as the maximum weight of 4221 is up to 9. Eq:- 3.1 gives the boolean expression of RPU and the respective logic is shown in Table- 3.1. Figure 3.2 shows the block diagram of RPU structured combining FG and PG reversible gates. Eq:- 3.1 {y [ 3 ], y [ 2 ], y [ 1 ], y[0]} = {B [ 3 ] + B [ 2 ], B [ 3 ], B [ 3 ] + B [ 1 ], B[0]} The BCD input B [3:0] in 8421 binary code, is passed through the RPU. The RPU converts 8421 to 4221 binary code. The RPU output y [3:0] is used as select signal in RMBU for transmitting data or zeros to the reversible accumulation unit (RAU). Table:-3.1 shows the input–output configuration of the 4221 reversible pre-processing unit. The QC of RPU is 11 and that the GO count is 6. Though the GO of the RPU is relatively high, it is utilized in making the gate reversible and faster and allowing it to dissipate less heat. 3.2 Reversible Multiple Generation Block A Reversible Multiple Generation Block(RMGB) also known as a Data selector, is the unit that selects the specific multiplicands and in turn it generates the multiples for the proposed HS-RBCDM. In [ 18 ], the design proposes a Multiplicand Multiple Generator [MMG] where the selection is directed by a separate set of digital inputs known as select lines. The binary information is received from the input lines and directed to the output line as 4X,2X,2X,1X blocks. On the basis of the values of the selection lines, one of these data inputs will be connected to the output. The MMG [ 18 ] consists of 4 DPG and 12 PG gates in order direct the output line leading to high gate count of 81 and QC of 397. Instead, in this design we have proposed a single gate level architecture for 4X,2X,2X,1X generation each. The RMGB consists of four FRG gate presenting as a multiplexer unit having output y[3:0] of RPU as select signal. Each unit generates the multiples such as 4X,2X,2X,1X respectively, which will either generate X[3:0] or 4'b0000 as output S i [3:0] based on the select signal for 4x,2x,1x,1x individually which we denote as M3[3:0], M2[3:0], M1[3:0], M0[3:0] respectively. The below Fig. 3.3 represents the Reversible Multiple Generation Block (RMGB) with reduced gate count and QC leading to less heat dissipation and power consumption proportionally with reduced area. 3.3 Reversible Accumulation Unit A Full adder is a circuit that takes two input bits (A ,B), a carry bit(C) to produces the output sum and carry out .The 3x3 Peres Gate is singly worked as half adder circuit when third input is set to zero i.e. third input is treated as a constant input. Reversible Full Adder produces four garbage outputs (G0, G1, G2, G3), and requires three constant input. Using the above full adder (RF) and Peres gate we have designed the reversible accumulation unit as shown in Fig. 3.5 for multiplication of the multiplicand and multiplier values. B. Area Enhanced HS-RBCDM (PE) Design As an enhancement to the HS-RBCDM in terms of power and speed, the RMGB part and RAU block is implemented by pre-producing the 4X,2X,2X,1X blocks for appending zeros to the input values for multiplication. This is done in replacement for shifting process done in reversible adder in HS-RBCDM in order to increase speed and reduce delay. The produced outputs are then selected by multiplexers with respect to the RPU output. 3.4 Enhanced Reversible Multiple Generation Block The 4X,2X,1X each block is generated using four Feynman gates. Feynman Gate acts as a copying gate [ 23 ]. Therefore for 1X by keeping one input of the FG-1X Block (FG gate) '0', input A [3:0] is given fed to the FG gate producing output a 1 [3:0] which holds the value of A itself and one GO0 = 0. The FG-1X output a 1 [3:0] is further fed to FG-2X block as similar to FG-1X. The output of FG-2X is taken as a 2 [3:0] and GO1 = 0. In order to append a zero to the 2X output, the GO1 is taken as a 2 [0] and a 2 [3:0] is taken as a 2 [4:1]. Thus, the output of FG-2X will be a 2 [4:0]. Similarly, FG-4X will produce output a 3 [5:0] as shown in Fig. 3.6 . The outputs a 1 ,a 2, a 3 are fed the 4X,2X,2X,1X RMGB block which acts a multiplexer, it produces output based on the RPU output y[3:0] as in of HS-RBCDM RMGB block process. Now, the RMGB output is should be added to attain the final multiplied output. In order to attain it, we use a simple RTL add operator (+) instead of the RAU unit in HS-RBCDM. The proposed Enhanced HS-RBCDM (HS-RBCDM PE ) works more efficiently in terms of speed and power consumption. 4. Results and Discussion 4.1 Quantum Metrics The various quantum parameters that are used to evaluate the performance of reversible circuits are the QC, CI, GO, and total quantum operating cost (TQOC). QC represents the cost of the circuit in terms of the cost of a primitive gate. The QC is calculated by counting the number of primitive reversible logic gates (1*1 or 2*2) required to realize the circuit. The QC of a 1*1 gate is 0, and that of a 2*2 gate is 1. The CI represents the number of inputs that have to be maintained constant at either 0 or 1 to synthesize the given logical function and maintain reversibility. The GO represents the extra outputs that are not used in the synthesis of a given circuit but are added to make an k-input, n-output function ((k; n) function) reversible. Eq. (7) gives the relation between the numbers of GOs and CIs to be maintained in the reversible gates. Input + CI = Logical output + GO (7) TQOC = QC + CI + RGC (8) Declarations Competing interests: The authors declare no competing interests References C.H. Bennett, “Logical Reversibility of Computation” IBM J. Res. Dev. 17(6), 525–1973. H.M.H. Babu, A.R. Chowdhury, “Design pf a Reversible Binary Coded Decimal Adder by using Reversible 4-bit Parallel Adder” 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design, pp. 255-260-2005. Rolf Launder: "Irreversiblity and heat generation in the computing process", IBM Journal of Research and Development, vol.5, pp 183–191, 1961. K. Bhardwaj, B.M. Deshpande, “K-Algorithm: Improved Booth’s Recording for Optimal Fault-Tolerant Reversible Multiplier” 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems (2013), pp. 362–367. K.S.R. Baby Janagam, “ASIC Implementation of Processing Unit Using Radix Decimal Multiplier” Int. J. Adv. Comput. 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Comput. 2, 112 “A Reversible Design of BCD Multiplier” – 2010. Saranya K, Vijeyakumar K.N. “A Novel n-Decimal Reversible Radix Binary-Coded Decimal Multiplier Using Radix Encoding Scheme” – 2021 H. Thapliyal, M. Srinivas, “Novel Reversible Multiplier Architecture using Reversible TGS Gate”, Asia-Pacific Conference on Advances in Computer Systems Architecture, pp. 805-817-2005. H. Thapliyal, S. Kotiyal, M.B. Srinivas, “Novel BCD Adders and their Reversible Logic Implementation for IEEE 754r Format”, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID’06), pp. 6 -2006. E.A. Vázquez, J.D. Bruguera, “Fast Radix-10 Multiplication Using Redundant BCD codes”, IEEE Trans. Comput. 63(8), 1902–2014. R.P. Feynman, “Quantum Mechanical Computers” Found. Phys. 16(6), 507–1986. E. Fredkin, T. Toffoli, Conservative logic. Int. J. Theor. Phys. 21, 219–253(1982). Peres, A.: Reversible logic and quantum computers, Phys Rev, 1985, 32, 3266–76. Vazquez, E.Antelo,P.Montuschi,“A New Family of High- Performance Parllel Multiplier”, 18th IEEE Symposium on Computer Arithmetic (ARITH’07), pp. 195-204-2007. Tables Tables 3.1 and 4.1-4.4 are available in the Supplementary Files section. Supplementary Files Tables.docx Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-3568596","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":246515399,"identity":"ce56c3ac-f91c-4b95-8674-d7d369dc7bf5","order_by":0,"name":"Hamirdhavalle DV","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAAA80lEQVRIiWNgGAWjYBACAyA+wMB2AEgxNx5gqADRzA3EamFsOMBwBqSFkbAWBrgWxjYGMAOvFnP204mHK8ruyBscP9hw4OO82mj+dqCWHxXbcGqx7MndcPDMuWeGG84kNhycue147ozDjA2MPWdu43bYAaCWxrbDjDMbEhsO8247ltsA1MLM2IZHy/m3YC32M/sfNhz+O+dY7nyCWm5AbEnsl0gEmV+Tu4GwFqAtDecOJ/dLPGw42HPsQO5GoJaDeP1yPnfzx4ayw7Zt/MkHH/yoqcudd/4wkFGBWws6OAwmDxCtHgjqSFE8CkbBKBgFIwQAAHgRcLaxHS3qAAAAAElFTkSuQmCC","orcid":"","institution":"","correspondingAuthor":true,"prefix":"","firstName":"Hamirdhavalle","middleName":"","lastName":"DV","suffix":""},{"id":246515400,"identity":"b077d1c6-dfc0-4934-8cc2-65199cc62ece","order_by":1,"name":"K. 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Accumulation Unit (RAU)\u003c/strong\u003e\u003c/p\u003e","description":"","filename":"3.5.png","url":"https://assets-eu.researchsquare.com/files/rs-3568596/v1/dbef0c4531e34c5034c14fbb.png"},{"id":46382024,"identity":"e1fa8d1c-664e-48b6-a825-567929c87ab2","added_by":"auto","created_at":"2023-11-14 03:09:02","extension":"png","order_by":9,"title":"Figure 9","display":"","copyAsset":false,"role":"figure","size":18507,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eFig 3.6:- Enhanced RMG Block\u003c/strong\u003e\u003c/p\u003e","description":"","filename":"3.6.png","url":"https://assets-eu.researchsquare.com/files/rs-3568596/v1/0aec87c68efe9f5a413e3bf0.png"},{"id":46385430,"identity":"8924bf7e-280f-4729-9fe3-a2d8c509f766","added_by":"auto","created_at":"2023-11-14 03:33:03","extension":"pdf","order_by":0,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":627077,"visible":true,"origin":"","legend":"","description":"","filename":"manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-3568596/v1/9d896560-a9b8-4758-8303-a2a47cfc03c7.pdf"},{"id":46382023,"identity":"8fd78a60-a42b-4dca-b919-eee16831b6ee","added_by":"auto","created_at":"2023-11-14 03:09:02","extension":"docx","order_by":1,"title":"","display":"","copyAsset":false,"role":"supplement","size":224173,"visible":true,"origin":"","legend":"","description":"","filename":"Tables.docx","url":"https://assets-eu.researchsquare.com/files/rs-3568596/v1/3872d64e191fd48b506cb24e.docx"}],"financialInterests":"","formattedTitle":"\u003cp\u003eVLSI Implementation of Radix Binary Coded Decimal Multiplier using Reversible Logic\u003c/p\u003e","fulltext":[{"header":"1. Introduction","content":"\u003cp\u003eIn computing and electronic systems, Binary Coded Decimal (BCD) is a class of binary encodings of decimal numbers where each digit is represented by a fixed number of bits, usually four or eight. BCD is still used with Real Time Clocks (RTC) chips to keep track of wall-clock time and it\u0026rsquo;s becoming more common for embedded microprocessors to include an RTC. Adder and Multiplier are main components of any BCD processing unit. BCD multiplier is the critical component that consumes more hardware area, dissipate more power, and exhibit high critical delay in design of BCD processing unit [\u003cspan citationid=\"CR7\" class=\"CitationRef\"\u003e7\u003c/span\u003e]. Reversible logic that recovers inputs from the outputs is a suitable alternative to design low power systems. Hence in this work, an attempt is made to design high speed area efficient BCD multiplier [\u003cspan citationid=\"CR25\" class=\"CitationRef\"\u003e25\u003c/span\u003e] for portable processing units using reversible logic. The proposed High-Speed Binary-Coded Decimal Multiplier (HS-RBCDM) incorporates structural modifications to the RR-BCDM design [\u003cspan citationid=\"CR18\" class=\"CitationRef\"\u003e18\u003c/span\u003e]. Evaluations of RR-BCDM revealed that the MMG unit contributes for high delay and gate count due to series of reversible gates in each multiple generation. However, the proposed design achieves area and speed efficiency using single gate level structure for each multiple multiplicand generation. The further enhancements done to the HS-RBCDM in terms of PDP reduction is achieved using a single gate level block for unit multiple generation and generating the higher multiples with a right shift operation in HS-RBCDM\u003csub\u003ePE\u003c/sub\u003e.\u003c/p\u003e \u003cp\u003eIn rest of the paper, Section \u003cspan refid=\"Sec2\" class=\"InternalRef\"\u003e2\u003c/span\u003e elaborates the basic reversible logic gates. Section \u003cspan refid=\"Sec6\" class=\"InternalRef\"\u003e3\u003c/span\u003e illustrates a detailed discussion of the proposed methodology. In Section \u003cspan refid=\"Sec11\" class=\"InternalRef\"\u003e4\u003c/span\u003e, the proposed reversible radix binary-coded multiplier is compared with previous proposed designs. Further, Section 5 compares the quantum matrices and power, delay comparison with previous designs.\u003c/p\u003e"},{"header":"2. Overview of basic Reversible Logic Gates","content":"\u003cp\u003eReversible logic is one of the alternative paradigm that reduces heat dissipation and delay logic depth in a circuit. It is been recognized as a memory less logic element that realize a one-to-one logic function. Reversible gates consist of equal number of inputs and outputs for the traceability of input from output and vice versa. Fan out is attained in reversible logic. The important parameters backing the design of reversible circuits are garbage outputs (GO), quantum cost (QC) and constant inputs (CI). The quantum cost of a reversible circuit is the number of 1x1 and 2x2 quantum gates that are used to construct the circuit. Constant inputs (CI) are the number of inputs that are to be maintaining constant at either 0 or 1 in order to synthesize the logical function. Garbage outputs are the ones that are neither the primary outputs nor the ones required for further computation.\u003c/p\u003e\n\u003cp\u003eThe following subsections discuss the reversible logic gates in detail.\u003c/p\u003e\n\u003cdiv id=\"Sec3\" class=\"Section2\"\u003e\n \u003ch2\u003e\u003cstrong\u003e2.1 Feynman Gate (FG)\u003c/strong\u003e\u003c/h2\u003e\n \u003cdiv class=\"BlockQuote\"\u003e\n \u003cp\u003eA 2*2 Feynman gate [\u003cspan class=\"CitationRef\"\u003e22\u003c/span\u003e] shown in Fig. 2.1 does the logical XOR function. The quantum cost of FG is 1. The Boolean expression defining the logic of the FG is given by Eq. (2.1) and Eq. (2.2). Symbol \u003cstrong\u003e^\u003c/strong\u003e represents the logic EXOR operation.\u003c/p\u003e\n \u003c/div\u003e\n\u003c/div\u003e\n\u003cdiv id=\"Sec4\" class=\"Section2\"\u003e\n \u003ch2\u003e\u003cstrong\u003e2.2 Fredkin Gate (FRG)\u003c/strong\u003e\u003c/h2\u003e\n \u003cdiv class=\"BlockQuote\"\u003e\n \u003cp\u003eFigure 2.2 shows the logic diagram and quantum representation of 3*3 Reversible FRG [\u003cspan class=\"CitationRef\"\u003e23\u003c/span\u003e], The inputs and outputs are defined by A, B, C and P, Q, R respectively. FRG performs as a reversible multiplexer and is used in data selection applications. The Boolean expressions representing the working of FRG are given in Eq. (2.3) to Eq. (2.5).\u003c/p\u003e\n \u003c/div\u003e\n \u003cp\u003eP\u0026thinsp;=\u0026thinsp;A (2.3)\u003c/p\u003e\n \u003cp\u003eQ = (A\u0026amp;(~\u0026thinsp;B)) | (A\u0026amp;C) (2.4)\u003c/p\u003e\n \u003cp\u003eR = (A\u0026amp;B) | (A\u0026amp;(~\u0026thinsp;C)) (2.5)\u003c/p\u003e\n \u003cdiv class=\"BlockQuote\"\u003e\n \u003cp\u003eNote from Eq. (2.3) to Eq. (2.5) that for logic low on \u0026lsquo;A\u0026rsquo; input, the outputs are viz., Q\u0026thinsp;=\u0026thinsp;B, and R\u0026thinsp;=\u0026thinsp;C. When \u0026lsquo;A\u0026rsquo; is logic high then the outputs are viz., Q\u0026thinsp;=\u0026thinsp;Cand R\u0026thinsp;=\u0026thinsp;B.\u003c/p\u003e\n \u003c/div\u003e\n \u003cdiv class=\"BlockQuote\"\u003e\n \u003cp\u003eNote from the Quantum diagram shown in Fig. 2.2(b) FRG demonstrates QC of 5. Fredkin gate not only act as reversible multiplexer it also performs different Boolean operations viz., COPY, SWAP, AND, and OR.\u003c/p\u003e\n \u003c/div\u003e\n\u003c/div\u003e\n\u003cdiv id=\"Sec5\" class=\"Section2\"\u003e\n \u003ch2\u003e\u003cstrong\u003e2.3 Peres Gate (PG)\u003c/strong\u003e\u003c/h2\u003e\n \u003cdiv class=\"BlockQuote\"\u003e\n \u003cp\u003e3x3 PG [\u003cspan class=\"CitationRef\"\u003e24\u003c/span\u003e] performs Copy, XOR, AND, NAND and NOR operations as shown in Table\u0026nbsp;4.1. It is noted from Fig.\u0026nbsp;2.3 that PG has A, B, C as inputs and P, Q, R as outputs as shown in Eq.\u0026nbsp;(2.6) to Eq.\u0026nbsp;(2.8). The output Q produces the Sum and output R produces the Carry. If C input is logic low, XOR operation of A and B occur at Q output and \u0026ldquo;\u0026amp;\u0026rdquo; operation of A and B occurs at R output. The quantum cost of PG is 4.\u003c/p\u003e\n \u003cp\u003eP\u0026thinsp;=\u0026thinsp;A (2.6)\u003c/p\u003e\n \u003cp\u003eQ\u0026thinsp;=\u0026thinsp;A^B (2.7)\u003c/p\u003e\n \u003cp\u003eR = (A\u0026amp;B)^C (2.8)\u003c/p\u003e\n \u003c/div\u003e\n\u003c/div\u003e"},{"header":"3. Proposed Reversible BCD Multiplier","content":"\u003cp\u003eThis section briefs in detail the design of High-Speed Reversible Radix Binary-Coded Decimal Multiplier (HS-RBCDM) and Enhanced High-Speed Reversible Radix Binary-Coded Decimal Multiplier (HS-RBCDM\u003csub\u003ePE\u003c/sub\u003e). The design consists reversible preprocessing unit [RPU] for 4221 radix recoding developed using RRG as in of [\u003cspan class=\"CitationRef\"\u003e1\u003c/span\u003e]. The reversible multiple generation block (RMGB) and Compression unit designed using reversible accumulation unit [RAU] for multiplication is shown in Fig. \u003cspan class=\"InternalRef\"\u003e3.1\u003c/span\u003e. The HS-BCDM is designed using PG, FRG and FG gates. The following subsections give a detailed illustration on the various block functions of the proposed multiplier.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eA. HS-RBCDM\u003c/strong\u003e\u003c/p\u003e\n\u003cdiv id=\"Sec7\" class=\"Section2\"\u003e\n \u003ch2\u003e3.1 Reversible Preprocessing Unit\u003c/h2\u003e\n \u003cp\u003eAmong various binary codes like gray code, 4221, 2421, excess-3 code and 8421, the 4221 binary code has been chosen to be appropriate code for BCD representation as the maximum weight of 4221 is up to 9. Eq:- 3.1 gives the boolean expression of RPU and the respective logic is shown in Table- 3.1. Figure \u003cspan class=\"InternalRef\"\u003e3.2\u003c/span\u003e shows the block diagram of RPU structured combining FG and PG reversible gates.\u003c/p\u003e\n \u003cdiv class=\"BlockQuote\"\u003e\n \u003cp\u003eEq:- 3.1\u003c/p\u003e\n \u003cp\u003e\u003cstrong\u003e{y\u003c/strong\u003e[\u003cspan class=\"CitationRef\"\u003e3\u003c/span\u003e], \u003cstrong\u003ey\u003c/strong\u003e[\u003cspan class=\"CitationRef\"\u003e2\u003c/span\u003e], \u003cstrong\u003ey\u003c/strong\u003e[\u003cspan class=\"CitationRef\"\u003e1\u003c/span\u003e], \u003cstrong\u003ey[0]} = {B\u003c/strong\u003e[\u003cspan class=\"CitationRef\"\u003e3\u003c/span\u003e]\u0026thinsp;\u003cstrong\u003e+\u0026thinsp;B\u003c/strong\u003e[\u003cspan class=\"CitationRef\"\u003e2\u003c/span\u003e], \u003cstrong\u003eB\u003c/strong\u003e[\u003cspan class=\"CitationRef\"\u003e3\u003c/span\u003e], \u003cstrong\u003eB\u003c/strong\u003e[\u003cspan class=\"CitationRef\"\u003e3\u003c/span\u003e]\u0026thinsp;\u003cstrong\u003e+\u0026thinsp;B\u003c/strong\u003e[\u003cspan class=\"CitationRef\"\u003e1\u003c/span\u003e], \u003cstrong\u003eB[0]}\u003c/strong\u003e\u003c/p\u003e\n \u003cp\u003eThe BCD input B [3:0] in 8421 binary code, is passed through the RPU. The RPU converts 8421 to 4221 binary code. The RPU output y [3:0] is used as select signal in RMBU for transmitting data or zeros to the reversible accumulation unit (RAU).\u003c/p\u003e\n \u003c/div\u003e\n \u003cdiv class=\"BlockQuote\"\u003e\n \u003cp\u003eTable:-3.1 shows the input\u0026ndash;output configuration of the 4221 reversible pre-processing unit. The QC of RPU is 11 and that the GO count is 6. Though the GO of the RPU is relatively high, it is utilized in making the gate reversible and faster and allowing it to dissipate less heat.\u003c/p\u003e\n \u003c/div\u003e\n\u003c/div\u003e\n\u003cdiv id=\"Sec8\" class=\"Section2\"\u003e\n \u003ch2\u003e3.2 Reversible Multiple Generation Block\u003c/h2\u003e\n \u003cdiv class=\"BlockQuote\"\u003e\n \u003cp\u003eA Reversible Multiple Generation Block(RMGB) also known as a Data selector, is the unit that selects the specific multiplicands and in turn it generates the multiples for the proposed HS-RBCDM. In [\u003cspan class=\"CitationRef\"\u003e18\u003c/span\u003e], the design proposes a Multiplicand Multiple Generator [MMG] where the selection is directed by a separate set of digital inputs known as select lines. The binary information is received from the input lines and directed to the output line as 4X,2X,2X,1X blocks. On the basis of the values of the selection lines, one of these data inputs will be connected to the output. The MMG [\u003cspan class=\"CitationRef\"\u003e18\u003c/span\u003e] consists of 4 DPG and 12 PG gates in order direct the output line leading to high gate count of 81 and QC of 397.\u003c/p\u003e\n \u003c/div\u003e\n \u003cdiv class=\"BlockQuote\"\u003e\n \u003cp\u003eInstead, in this design we have proposed a single gate level architecture for 4X,2X,2X,1X generation each. The RMGB consists of four FRG gate presenting as a multiplexer unit having output y[3:0] of RPU as select signal. Each unit generates the multiples such as 4X,2X,2X,1X respectively, which will either generate X[3:0] or 4\u0026apos;b0000 as output S\u003csub\u003ei\u003c/sub\u003e[3:0] based on the select signal for 4x,2x,1x,1x individually which we denote as M3[3:0], M2[3:0], M1[3:0], M0[3:0] respectively. The below Fig. \u003cspan class=\"InternalRef\"\u003e3.3\u003c/span\u003e represents the Reversible Multiple Generation Block (RMGB) with reduced gate count and QC leading to less heat dissipation and power consumption proportionally with reduced area.\u003c/p\u003e\n \u003c/div\u003e\n\u003c/div\u003e\n\u003cdiv id=\"Sec9\" class=\"Section2\"\u003e\n \u003ch2\u003e3.3 Reversible Accumulation Unit\u003c/h2\u003e\n \u003cdiv class=\"BlockQuote\"\u003e\n \u003cp\u003eA Full adder is a circuit that takes two input bits (A ,B), a carry bit(C) to produces the output sum and carry out .The 3x3 Peres Gate is singly worked as half adder circuit when third input is set to zero i.e. third input is treated as a constant input. Reversible Full Adder produces four garbage outputs (G0, G1, G2, G3), and requires three constant input.\u003c/p\u003e\n \u003c/div\u003e\n \u003cdiv class=\"BlockQuote\"\u003e\n \u003cp\u003eUsing the above full adder (RF) and Peres gate we have designed the reversible accumulation unit as shown in Fig. \u003cspan class=\"InternalRef\"\u003e3.5\u003c/span\u003e for multiplication of the multiplicand and multiplier values.\u003c/p\u003e\n \u003c/div\u003e\n \u003cp\u003e\u003cstrong\u003eB.\u003c/strong\u003e \u003cstrong\u003eArea Enhanced HS-RBCDM\u003c/strong\u003e\u003csub\u003e\u003cstrong\u003e(PE)\u003c/strong\u003e\u003c/sub\u003e \u003cstrong\u003eDesign\u003c/strong\u003e\u003c/p\u003e\n \u003cdiv class=\"BlockQuote\"\u003e\n \u003cp\u003eAs an enhancement to the HS-RBCDM in terms of power and speed, the RMGB part and RAU block is implemented by pre-producing the 4X,2X,2X,1X blocks for appending zeros to the input values for multiplication. This is done in replacement for shifting process done in reversible adder in HS-RBCDM in order to increase speed and reduce delay. The produced outputs are then selected by multiplexers with respect to the RPU output.\u003c/p\u003e\n \u003c/div\u003e\n\u003c/div\u003e\n\u003cdiv id=\"Sec10\" class=\"Section2\"\u003e\n \u003ch2\u003e3.4 Enhanced Reversible Multiple Generation Block\u003c/h2\u003e\n \u003cdiv class=\"BlockQuote\"\u003e\n \u003cp\u003eThe 4X,2X,1X each block is generated using four Feynman gates. Feynman Gate acts as a copying gate [\u003cspan class=\"CitationRef\"\u003e23\u003c/span\u003e]. Therefore for 1X by keeping one input of the FG-1X Block (FG gate) \u0026apos;0\u0026apos;, input A [3:0] is given fed to the FG gate producing output a\u003csub\u003e1\u003c/sub\u003e[3:0] which holds the value of A itself and one GO0\u0026thinsp;=\u0026thinsp;0. The FG-1X output a\u003csub\u003e1\u003c/sub\u003e[3:0] is further fed to FG-2X block as similar to FG-1X. The output of FG-2X is taken as a\u003csub\u003e2\u003c/sub\u003e[3:0] and GO1\u0026thinsp;=\u0026thinsp;0. In order to append a zero to the 2X output, the GO1 is taken as a\u003csub\u003e2\u003c/sub\u003e[0] and a\u003csub\u003e2\u003c/sub\u003e[3:0] is taken as a\u003csub\u003e2\u003c/sub\u003e[4:1]. Thus, the output of FG-2X will be a\u003csub\u003e2\u003c/sub\u003e[4:0]. Similarly, FG-4X will produce output a\u003csub\u003e3\u003c/sub\u003e[5:0] as shown in Fig. \u003cspan class=\"InternalRef\"\u003e3.6\u003c/span\u003e.\u003c/p\u003e\n \u003c/div\u003e\n \u003cdiv class=\"BlockQuote\"\u003e\n \u003cp\u003eThe outputs a\u003csub\u003e1\u003c/sub\u003e,a\u003csub\u003e2,\u003c/sub\u003ea\u003csub\u003e3\u003c/sub\u003e are fed the 4X,2X,2X,1X RMGB block which acts a multiplexer, it produces output based on the RPU output y[3:0] as in of HS-RBCDM RMGB block process. Now, the RMGB output is should be added to attain the final multiplied output. In order to attain it, we use a simple RTL add operator (+) instead of the RAU unit in HS-RBCDM. The proposed Enhanced HS-RBCDM (HS-RBCDM\u003csub\u003ePE\u003c/sub\u003e) works more efficiently in terms of speed and power consumption.\u003c/p\u003e\n \u003c/div\u003e\n\u003c/div\u003e"},{"header":"4. Results and Discussion","content":"\u003cdiv id=\"Sec12\" class=\"Section2\"\u003e\n \u003ch2\u003e4.1 Quantum Metrics\u003c/h2\u003e\n \u003cdiv class=\"BlockQuote\"\u003e\n \u003cp\u003eThe various quantum parameters that are used to evaluate the performance of reversible circuits are the QC, CI, GO, and total quantum operating cost (TQOC). QC represents the cost of the circuit in terms of the cost of a primitive gate. The QC is calculated by counting the number of primitive reversible logic gates (1*1 or 2*2) required to realize the circuit. The QC of a 1*1 gate is 0, and that of a 2*2 gate is 1. The CI represents the number of inputs that have to be maintained constant at either 0 or 1 to synthesize the given logical function and maintain reversibility. The GO represents the extra outputs that are not used in the synthesis of a given circuit but are added to make an k-input, n-output function ((k; n) function) reversible. Eq. (7) gives the relation between the numbers of GOs and CIs to be maintained in the reversible gates.\u003c/p\u003e\n \u003c/div\u003e\n \u003cp\u003eInput\u0026thinsp;+\u0026thinsp;CI\u0026thinsp;=\u0026thinsp;Logical output\u0026thinsp;+\u0026thinsp;GO (7)\u003c/p\u003e\n \u003cdiv class=\"BlockQuote\"\u003e\n \u003cp\u003eTQOC\u0026thinsp;=\u0026thinsp;QC\u0026thinsp;+\u0026thinsp;CI\u0026thinsp;+\u0026thinsp;RGC (8)\u003c/p\u003e\n \u003c/div\u003e\n\u003c/div\u003e"},{"header":"Declarations","content":"\u003cp\u003eCompeting interests: The authors declare no competing interests\u003c/p\u003e"},{"header":"References","content":"\u003col\u003e\u003cli\u003e\u003cspan\u003eC.H. Bennett, \u0026ldquo;Logical Reversibility of Computation\u0026rdquo; IBM J. Res. Dev. 17(6), 525\u0026ndash;1973.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eH.M.H. Babu, A.R. Chowdhury, \u0026ldquo;Design pf a Reversible Binary Coded Decimal Adder by using Reversible 4-bit Parallel Adder\u0026rdquo; 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design, pp.\u0026nbsp;255-260-2005.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eRolf Launder: \"Irreversiblity and heat generation in the computing process\", IBM Journal of Research and Development, vol.5, pp\u0026nbsp;183\u0026ndash;191, 1961.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eK. Bhardwaj, B.M. Deshpande, \u0026ldquo;K-Algorithm: Improved Booth\u0026rsquo;s Recording for Optimal Fault-Tolerant Reversible Multiplier\u0026rdquo; 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems (2013), pp.\u0026nbsp;362\u0026ndash;367.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eK.S.R. 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Chen, IEEE Trans Circuits Syst II Analog Digit Signal Process 46(6), 836 (1999).\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eS. Gorgin, G. Jaberipur, \u0026ldquo;A fully redundant decimal adder and its application in parallel decimal multiplier\u0026rdquo; Microelectron. J. 40(10), 1471\u0026ndash;2009.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eC.E.M. Guardia, \u0026ldquo;Disruption-Tolerant Sessions for Seamless Mobility\u0026rdquo; VIII Southern Conference on Programmable Logic, pp.\u0026nbsp;1-6-2012.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eH. Md Hasan Babu, Md. R. Islam, A. R. Chowdhury, S. Mostahed Ali Chowdhury, \u0026ldquo;Reversible Logic Synthesis for Minimization of Full- Adder\u0026rdquo; in Euromicro symposium on digital system design, 2003. Proceedings, pp.\u0026nbsp;50-54-2003.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eS. Gao, D. Al-Khalili, J. Langlois, N. Chabini, \u0026ldquo;Efficient Realization pf BCD Multipliers Using FPGAs\u0026rdquo; Int J Reconfig Comput, 1 -2017.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eR. Landauer, \u0026ldquo;Irreversibility and Heat Generation in the computing Process\u0026rdquo; DIBM J. Res. Dev. 5(3), 183\u0026ndash;1961.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eT. Lang, A. Nannarelli, \u0026ldquo;A Radix-10 Combinational Multiplier\u0026rdquo; in Fortieth Asilomar Conference on Signals, Systems and Computers, pp.\u0026nbsp;313-317-2006.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eM. Mohammadi, M. Eshghi, \u0026ldquo;On Figures of merit in reversible and quantum logic design\u0026rdquo; Quantum Inf. Process. 8(4), 297\u0026ndash;2009.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eS. Narayanamoorthy, H.A. Moghaddam, Z. Liu, T. Park, N.S. Kim, \u0026ldquo;Energy-Efficient Approximate Multiplication for Digital Signal Processing and Classification Applications\u0026rdquo;, IEEE Transactions on Very Large-Scale Integration (VLSI) Systems 23(6), 1180\u0026ndash;2015.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eV.R. Rajmohan, M. Rajmohan, J. Comput. 2, 112 \u0026ldquo;A Reversible Design of BCD Multiplier\u0026rdquo; \u0026ndash; 2010.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eSaranya K, Vijeyakumar K.N. \u0026ldquo;A Novel n-Decimal Reversible Radix Binary-Coded Decimal Multiplier Using Radix Encoding Scheme\u0026rdquo; \u0026ndash; 2021\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eH. Thapliyal, M. Srinivas, \u0026ldquo;Novel Reversible Multiplier Architecture using Reversible TGS Gate\u0026rdquo;, Asia-Pacific Conference on Advances in Computer Systems Architecture, pp.\u0026nbsp;805-817-2005.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eH. Thapliyal, S. Kotiyal, M.B. Srinivas, \u0026ldquo;Novel BCD Adders and their Reversible Logic Implementation for IEEE 754r Format\u0026rdquo;, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID\u0026rsquo;06), pp.\u0026nbsp;6 -2006.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eE.A. V\u0026aacute;zquez, J.D. Bruguera, \u0026ldquo;Fast Radix-10 Multiplication Using Redundant BCD codes\u0026rdquo;, IEEE Trans. Comput. 63(8), 1902\u0026ndash;2014.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eR.P. Feynman, \u0026ldquo;Quantum Mechanical Computers\u0026rdquo; Found. Phys. 16(6), 507\u0026ndash;1986.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eE. Fredkin, T. Toffoli, Conservative logic. Int. J. Theor. Phys. 21, 219\u0026ndash;253(1982).\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003ePeres, A.: Reversible logic and quantum computers, Phys Rev, 1985, 32, 3266\u0026ndash;76.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eVazquez, E.Antelo,P.Montuschi,\u0026ldquo;A New Family of High- Performance Parllel Multiplier\u0026rdquo;, 18th IEEE Symposium on Computer Arithmetic (ARITH\u0026rsquo;07), pp.\u0026nbsp;195-204-2007.\u003c/span\u003e\u003c/li\u003e\u003c/ol\u003e"},{"header":"Tables","content":"\u003cp\u003eTables 3.1 and 4.1-4.4 are available in the Supplementary Files section.\u003c/p\u003e"}],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":true,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":true,"hideJournal":true,"highlight":"","institution":"Dr.Mahalingam College of Engineering and Technology","isAcceptedByJournal":false,"isAuthorSuppliedPdf":false,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":false,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"Binary Coded Decimal, Radix Re-coder, Reversible gates, Quantum computing, Power-Delay Product","lastPublishedDoi":"10.21203/rs.3.rs-3568596/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-3568596/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eIn CMOS design, conventional logic design plays a \u0026nbsp;vital role. Even though, irrespective of its many advantages, it \u0026nbsp;lacks efficiency in terms of speed, area, power, and delay leading \u0026nbsp;to much heat dissipation and delay on circuit design. Therefore, \u0026nbsp;in replacement of conventional digital computers, Reversible \u0026nbsp;logic acts as a promising technology that can improve the \u0026nbsp;standard of the circuits in terms of power, speed, area, heat \u0026nbsp;dissipation, lifespan, and input traceability. In this project, we \u0026nbsp;propose a high-speed reversible radix binary-coded decimal \u0026nbsp;multiplier (HS-RBCDM) and a Power Enhanced- High speed \u0026nbsp;reversible binary-coded decimal multiplier (HS-RBCDMPE) each \u0026nbsp;efficient in terms of speed, power and area respectively. In \u0026nbsp;comparison with recent designs, the proposed methodology gives \u0026nbsp;a single gate level architecture for multiple multiplicand \u0026nbsp;generator (MMG) and reversible adder and a Radix-recoder for \u0026nbsp;converting 8221 to 4221 codes for HS-RBCDM that achieves low \u0026nbsp;power dissipation and shifting operation using copying gate \u0026nbsp;instead of MMG for HS-RBCDMPE to achieve high-speed reducing delay in the circuit and area efficiency. The proposed \u0026nbsp;multipliers HS-RBCDM and HS-RBCDMPE is designed with 90- nm ASIC technology using the Cadence EDA tool and is \u0026nbsp;compared with state-of-art reversible BCD algorithm. \u0026nbsp;Performance evaluations of the proposed designs compared with \u0026nbsp;recent proposed methods reveals that the proposed HS-RBCDM \u0026nbsp;multiplier and HS-RBCDMPE achieves 64.9% and 69.6% Area \u0026nbsp;reduction, 51.3% and 71.9% Delay reduction and 52.6% and PDP reduction respectively.\u003c/p\u003e","manuscriptTitle":"VLSI Implementation of Radix Binary Coded Decimal Multiplier using Reversible Logic","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2023-11-14 03:08:58","doi":"10.21203/rs.3.rs-3568596/v1","editorialEvents":[{"type":"communityComments","content":0}],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true}}],"origin":"","ownerIdentity":"dfbafcb6-0ce7-4a27-94e9-424458080931","owner":[],"postedDate":"November 14th, 2023","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"posted","subjectAreas":[],"tags":[],"updatedAt":"2023-11-14T03:08:58+00:00","versionOfRecord":[],"versionCreatedAt":"2023-11-14 03:08:58","video":"","vorDoi":"","vorDoiUrl":"","workflowStages":[]},"version":"v1","identity":"rs-3568596","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-3568596","identity":"rs-3568596","version":["v1"]},"buildId":"_2-kVJe1T_tPrBINL-cwx","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}