Energy-Efficient Multiplier Design Using Radix- 16 Booth Encoding and Clock Gating

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Abstract In many computational areas, including DSP and machine learning, where speed and energy economy are critical, multiplication is an essential operation. The suggested Radix-16 Booth multiplier optimizes performance by using clock gating, 6-input LUTs, and 4:2 compressors. The experimental results demonstrate notable decreases in power consumption, critical path delay, and LUT utilization. This architecture is ideal for energy-constrained FPGA and VLSI systems because it balances speed, power, and resource efficiency.
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Energy-Efficient Multiplier Design Using Radix- 16 Booth Encoding and Clock Gating | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Energy-Efficient Multiplier Design Using Radix- 16 Booth Encoding and Clock Gating Bhargav Ram R, Pranitha Koduru, Sai Kiran Amaripelly, Sai Rohith Yalldasari This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-6461162/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract In many computational areas, including DSP and machine learning, where speed and energy economy are critical, multiplication is an essential operation. The suggested Radix-16 Booth multiplier optimizes performance by using clock gating, 6-input LUTs, and 4:2 compressors. The experimental results demonstrate notable decreases in power consumption, critical path delay, and LUT utilization. This architecture is ideal for energy-constrained FPGA and VLSI systems because it balances speed, power, and resource efficiency. Full Text Additional Declarations No competing interests reported. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-6461162","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":452752486,"identity":"9f72cd74-c344-426d-b02e-e1f48d87e156","order_by":0,"name":"Bhargav Ram R","email":"","orcid":"","institution":"CMR College of Engineering and Technology","correspondingAuthor":false,"prefix":"","firstName":"Bhargav","middleName":"Ram","lastName":"R","suffix":""},{"id":452752487,"identity":"8e7aa8a6-886c-43c8-8c5d-8d3fb3d55e4d","order_by":1,"name":"Pranitha Koduru","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAABA0lEQVRIie3OvUrEQBDA8TkGNs1o2pWAvsIcCyfCcfcqGwJns4VgK1wRME30WRTBymJhIdVJWgWLpEkdFQ4LkfuoDjQRO4v9wzQDP2YAfL5/WIgUtBokQpjanT13k4OMBFQwDkAWeruh3wiXJAYVzEIAwzukL7dXVPrCRceweH17fpgcTgHrFs5eOsUg3T9lXTh1kl7dRaZJFIFQErjpJIjEUguXsH28R2NtnAOM1g+7TiK25MvNb6xpNmSeQ7DsJYQ0kvHlDNkasSGagPqvSCTF8fUY+alQkbHJMHd0LnUPmZaLYf2xlMhlWr8bOzkKsuy2bT+7yQ/hevRfgM/n8/m+tQJvx1CpVXaedgAAAABJRU5ErkJggg==","orcid":"","institution":"CMR College of Engineering and Technology","correspondingAuthor":true,"prefix":"","firstName":"Pranitha","middleName":"","lastName":"Koduru","suffix":""},{"id":452752488,"identity":"7e8fe365-31e1-48c3-a359-ffaeb3b7b38f","order_by":2,"name":"Sai Kiran Amaripelly","email":"","orcid":"","institution":"CMR College of Engineering and Technology","correspondingAuthor":false,"prefix":"","firstName":"Sai","middleName":"Kiran","lastName":"Amaripelly","suffix":""},{"id":452752491,"identity":"f080a5e3-fb3c-42cd-9c72-7bfec09891cb","order_by":3,"name":"Sai Rohith Yalldasari","email":"","orcid":"","institution":"CMR College of Engineering and Technology","correspondingAuthor":false,"prefix":"","firstName":"Sai","middleName":"Rohith","lastName":"Yalldasari","suffix":""}],"badges":[],"createdAt":"2025-04-16 08:23:16","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-6461162/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-6461162/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":83026627,"identity":"fba9775a-fd78-4765-bf5e-d8fff59cac90","added_by":"auto","created_at":"2025-05-19 08:32:08","extension":"pdf","order_by":1,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":349264,"visible":true,"origin":"","legend":"","description":"","filename":"journalpaper.pdf","url":"https://assets-eu.researchsquare.com/files/rs-6461162/v1_covered_7db5d711-86ce-465b-acdd-c5644a9a8a2b.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"Energy-Efficient Multiplier Design Using Radix- 16 Booth Encoding and Clock Gating","fulltext":[],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":false,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":true,"highlight":"","institution":"","isAcceptedByJournal":false,"isAuthorSuppliedPdf":true,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":true,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"","lastPublishedDoi":"10.21203/rs.3.rs-6461162/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-6461162/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eIn many computational areas, including DSP and machine learning, where speed and energy economy are critical, multiplication is an essential operation. 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