ASIC Design of Area Efficient Analog Frontend for Image Sharpening Applications

ASIC Design of Area Efficient Analog Frontend for Image Sharpening Applications | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article ASIC Design of Area Efficient Analog Frontend for Image Sharpening Applications K N Vijeyakumar, Silambarasan Dharmalingam, Talluri Vineel Jessy, and 2 more This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-4741305/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract In this research article we propose a new analog sharpening filter analog frontend (SAF) for image enhancement. The SAF is built using a bulk-controlled datum pair (BC-DP), enabling threshold equalization between amplifying and load MOSFETs and achieving better linearization in the processed output signal. The reported SAF incorporates a differential weight mask to achieve bias currents in cascaded BC-DPs. To process the 3×3 kernel of the input image, the proposed SAF utilizes nine BC-DP cells connected in parallel. The parallel operation of BC-DP cells achieves better processing speed compared to their digital counterparts, which employ adders and multipliers to realize the filter structure whose processing capability is bottlenecked by the carry propagation delay of adder units. Furthermore, to achieve area efficiency, we omit the corner pixels in the input kernel for processing, and the truncated version of the SAF (SAFTrun) is realized using five BC-DP cells. Simulations reveal that the reported SAF and its truncated version are able to achieve better operating frequencies when compared to the few other AFEs proposed for image processing applications. Semi-Conductor Laboratory (SCL) 180nm MOSFETs are used to implement the reported SAFs. Analog frontend Image Sharpening area-efficient Bulk controlled 3×3 kernel Full Text Additional Declarations No competing interests reported. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. 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Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-4741305","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":331139366,"identity":"4e31c950-c423-47d0-8210-3373e16f9831","order_by":0,"name":"K N Vijeyakumar","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAAA1UlEQVRIiWNgGAWjYDACZoYEMM0PIhIKiNdiwCDZANJiQLxdBgwGByA0EWqPMzx8zMPwJ8/4/OrEDw8MGOT5xQ4Q0HKYIdmYh8Gg2OzG280SQIcZzpydgF+LZDNDmjRQS+K2G2c3gLQkGNwmrCX9N0jL5hlnN/8gSgs/M0MaM0jLBv7ebcTZAtSSLDnHwDhxxg3ebRYJBhKE/cLGfybxw5sKucT+/rObb/6osJHnlyaghYGBJ4GJBxQdEmCVEoSUgwD7AcYfYCceIEb1KBgFo2AUjEQAAP3pPtOID2SNAAAAAElFTkSuQmCC","orcid":"","institution":"Dr.Mahalingam College of Engineering and Technology","correspondingAuthor":true,"prefix":"","firstName":"K","middleName":"N","lastName":"Vijeyakumar","suffix":""},{"id":331139368,"identity":"4adb9ac0-b782-4987-b90d-bc854c6e4c49","order_by":1,"name":"Silambarasan Dharmalingam","email":"","orcid":"","institution":"Sri Venkateswara College of Engineering","correspondingAuthor":false,"prefix":"","firstName":"Silambarasan","middleName":"","lastName":"Dharmalingam","suffix":""},{"id":331139370,"identity":"c4318f88-3f36-4f5a-987f-e2aca66bfa2c","order_by":2,"name":"Talluri Vineel Jessy","email":"","orcid":"","institution":"Dr.Mahalingam College of Engineering and Technology","correspondingAuthor":false,"prefix":"","firstName":"Talluri","middleName":"Vineel","lastName":"Jessy","suffix":""},{"id":331139377,"identity":"d7644383-8a17-44f0-a645-931de95ffc74","order_by":3,"name":"M Manjubala","email":"","orcid":"","institution":"Dr.Mahalingam College of Engineering and Technology","correspondingAuthor":false,"prefix":"","firstName":"M","middleName":"","lastName":"Manjubala","suffix":""},{"id":331139379,"identity":"d833adf9-f2bd-449d-949b-773d2a67f49c","order_by":4,"name":"Bhagavathi Priya","email":"","orcid":"","institution":"Dr.Mahalingam College of Engineering and Technology","correspondingAuthor":false,"prefix":"","firstName":"Bhagavathi","middleName":"","lastName":"Priya","suffix":""}],"badges":[],"createdAt":"2024-07-15 07:22:25","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-4741305/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-4741305/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":84037387,"identity":"6411243e-1b49-4cda-b1d1-f78c062f6bb9","added_by":"auto","created_at":"2025-06-06 04:31:41","extension":"pdf","order_by":1,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":1811518,"visible":true,"origin":"","legend":"","description":"","filename":"Analogfrontendforimagesharpeningapplications.pdf","url":"https://assets-eu.researchsquare.com/files/rs-4741305/v1_covered_139a5ffa-120a-416b-9559-7c0348282463.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"ASIC Design of Area Efficient Analog Frontend for Image Sharpening Applications","fulltext":[],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":false,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":true,"highlight":"","institution":"","isAcceptedByJournal":false,"isAuthorSuppliedPdf":true,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":true,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"Analog frontend, Image Sharpening, area-efficient, Bulk controlled, 3×3 kernel","lastPublishedDoi":"10.21203/rs.3.rs-4741305/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-4741305/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eIn this research article we propose a new analog sharpening filter analog frontend (SAF) for image enhancement. The SAF is built using a bulk-controlled datum pair (BC-DP), enabling threshold equalization between amplifying and load MOSFETs and achieving better linearization in the processed output signal. The reported SAF incorporates a differential weight mask to achieve bias currents in cascaded BC-DPs. To process the 3\u0026times;3 kernel of the input image, the proposed SAF utilizes nine BC-DP cells connected in parallel. The parallel operation of BC-DP cells achieves better processing speed compared to their digital counterparts, which employ adders and multipliers to realize the filter structure whose processing capability is bottlenecked by the carry propagation delay of adder units. Furthermore, to achieve area efficiency, we omit the corner pixels in the input kernel for processing, and the truncated version of the SAF (SAFTrun) is realized using five BC-DP cells. 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