Robust analogue neuromorphic hardware networks using intrinsic physics-adaptive learning

Robust analogue neuromorphic hardware networks using intrinsic physics-adaptive learning | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Physical Sciences - Article Robust analogue neuromorphic hardware networks using intrinsic physics-adaptive learning Feng Miao, Cong Wang, Yichen Zhao, Xing-Jian Yangdong, Wei Wei, and 11 more This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-4651980/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract Analogue neuromorphic computing hardware is highly energy-efficient and has been regarded as one of the most promising technologies for advancing artificial intelligence 1-7 . However, the robust deployment of these analogue neuromorphic systems is hindered by stochastic variations of analogue devices and dynamic changes in hardware structure 8, 9 . Here, we demonstrate an approach called intrinsic physics-adaptive learning (IPAL) that can effectively train analogue neuromorphic networks based on non-ideal hardware. This approach allows us to obtain gradients of the practical physical system by using two-step physical operations ( i.e. , applying stimuli to the physical system and observing its resulting response), eliminating the need for mathematical modelling of the physical system. Experiments validate the effectiveness of IPAL on a neuromorphic hardware network comprised of analogue in-memory computing arrays and analogue activation units. Furthermore, we demonstrate that the approach can effectively train analogue neuromorphic networks with unpredictable hardware variations or impairments, and restore their recognition accuracy even when 60% of electrical synapses and neurons fail to work. We also show that IPAL can be used for analogue neuromorphic networks based on emerging memristive devices. Our work paves the way for developing analogue neuromorphic computing hardware with superior fault-tolerant performance. Physical sciences/Physics/Electronics, photonics and device physics Physical sciences/Materials science Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Main The hardware implementation of fully analogue neuromorphic networks 10-19 , achieved by tiling multiple in-memory computing arrays and analogue nonlinear units 20-25 , can significantly enhance the energy efficiency of artificial intelligence 26-31 . This is because analogue hardware systems, such as electrical and optical systems, can utilize the intrinsic physical characteristics of materials and devices to perform energy-efficient computations 32-48 . However, the practical deployment of such analogue hardware systems remains challenging 9, 49 . One primary issue is that the fundamental physical characteristics are sensitive to variations in material compositions and physical dimensions of analogue devices 40 , but it is impossible to achieve absolute precision in the manufacturing process 50 . The sensitivity, along with resulting variations in hardware behaviours, makes it extremely difficult to use a specific mathematical model to precisely describe these analogue hardware systems 46, 47 . As a result, modelling errors accumulate in fully analogue multilayer neuromorphic networks, making traditional mathematical model-based training approaches problematic. This explains why existing analogue neuromorphic hardware networks often fall short of their software counterparts in terms of recognition accuracy 10, 51, 52 . Furthermore, during the training process, stochastic degradations of analogue devices in the hardware systems lead to dynamic changes in the internal structure of the network 43, 53 , severely compromising the robustness and reliability of the system 54 . Therefore, there is a pressing need to develop a learning approach capable of accommodating analogue hardware variabilities and dynamic internal structural changes, enabling hardware-fault tolerance in training fully analogue neuromorphic networks. In this article, we demonstrate a training approach called IPAL to achieve hardware-fault tolerance in analogue hardware-implemented neuromorphic networks. This approach enables a fully analogue neuromorphic network to achieve high recognition accuracy even surpassing that of a mathematical network trained by the backpropagation (BP) algorithm. Moreover, the physical nature of the IPAL approach makes it adaptive to unpredictable internal hardware variations and unknown hardware changes during the training processes of fully analogue neuromorphic networks. This ability further enables a defective neuromorphic network to restore its functionality, and particularly favors emerging memristive devices, as it can prevent the functionality of analogue computing systems from the impacts of device defects and degradations. The demonstrated training approach in our work can greatly enhance the robustness of analogue neuromorphic hardware networks and provide superior fault-tolerant performance like that in the brain 55 . Intrinsic physics-adaptive learning To achieve superior hardware-fault-tolerance in fully analogue neuromorphic networks, it is essential to train these analogue systems by harnessing their intrinsic physical characteristics, without relying on mathematical modelling. Due to considerations of effectiveness and generalizability, the primary objective for training analogue neuromorphic networks is to derive the actual gradients of physical parameters in these physical computing systems 56 . IPAL is such an approach that can utilize physical operations, such as perturbing the physical computing system and observing the resulting response, rather than utilizing mathematical modelling of the physical systems to obtain the actual gradients and train neuromorphic hardware networks. The core idea of IPAL is introduced in Fig. 1, which illustrates the basic operations to obtain the actual gradient in a fully analogue hardware-implemented neuromorphic network. In this analogue hardware system, a l represents the output signals of the l th -layer neurons; z l represents the input signals of the l th -layer neurons and also the output signals of the l th -layer synaptic connection; and W l denotes the weights of the l th -layer synaptic connection. The weights in all layers are randomly initialized before training. As shown in Fig. 1c, during the implementation of IPAL, we first feed the analogue signal vector representing the training data x train into the input layer of the analogue neuromorphic network, denoted by a 0 . The forward propagation in the hardware system is completed in one shot, and we can measure the results y at the output layer, which is used for calculating the error value Loss in conjunction with the y train of the training data. We then perturb the hardware system by adding a perturbation signal Δ z onto the input signal of a selected neuron. The perturbation will propagate forward through the analogue neuromorphic network. Thereby we can measure the perturbed output signals y ' , resulting in a new error value Loss ' . Based on the measured results, the error perturbation is defined as Δ Loss = Loss ' – Loss . According to the finite difference method, the weight gradients ∂ Loss / ∂W l can be obtained via a l -1 ×Δ Loss /Δ z , in which all the quantities can be experimentally measured. By applying the perturbation into different nodes and traversing a batch of training data, we can collect and accumulate weight gradients of all electrical synapses, and then update the weights according to the weight gradients, following ΔW = Σ - η × ∂ Loss / ∂W , where η represents the learning rate. In this way, the analogue hardware-implemented neuromorphic network can be effectively trained without any knowledge of its mathematical model. More detailed implementation of IPAL is provided in Methods and Supplementary Information Section 2.2. Experimental verification of intrinsic physics-adaptive learning We experimentally verified the validity of IPAL on a customized hardware system (Fig. 2a), which contains an end-to-end fully analogue neuromorphic network implemented by alternately connecting analogue in-memory computing (AIMC) chips and analogue activation units (AUs). The AIMC chips are employed as electrical synapses to perform parallel vector-matrix multiplications (VMMs) in analogue domain, and the AUs function as electrical neurons to realize nonlinear functions in analogue domain. Each AIMC chip contains 34×32 AIMC cells, supporting a 34-dimensional input vector and a 32-dimensional output vector (Extended Data Fig. 1a). Using the differential scheme, an AIMC chip represents a 34×16 connection matrix with positive and negative weight values. Due to the parallel architecture of the AIMC chip, we can construct a larger connection weight matrix (68×32) by combining four AIMC chips to perform parallel vector-matrix multiplications. Each AU is a nonlinear amplification circuit with a differential pair of two input signals, thereby realizing both positive and negative weights (Extended Data Fig. 1d). To implement IPAL, other peripheral circuits are also included in the hardware system, as illustrated in the schematic diagram in Fig. 2b. The analogue-to-digital converters (ADCs) and multiplexers (MUX) are used to measure the output signals of AUs, digital-to-analogue converters (DACs) are used to convert the handwritten digit images into analogue input signals of the first-layer AIMC arrays, and the MCU is used as the controller of the system. For more details on the hardware, please refer to Methods. As a proof of concept, we trained a fully connected neuromorphic network (Fig. 2c) and used handwritten digits recognition task (Optdigits dataset) to benchmark the accuracy performance of IPAL. The results (Fig. 2d, e) demonstrate that the classification accuracy exceeded 90% within the first 5 epochs. After 200 epochs of training, the classification accuracy reached 98.69% on the training set and 96.16% on the test set. Meanwhile, the loss value decreased by two orders of magnitude. Figure 2e shows the confusion matrix of measured classification accuracy on the test set, and Extended Data Fig. 2a exhibits the evolution of the weight distributions in AIMC arrays. Moreover, the IPAL-trained analogue neuromorphic network demonstrates a closer alignment in accuracy performance between the training and test sets than that in the BP-trained mathematical model. This suggests that our approach may mitigate the overfitting issue. As a result, our fully analogue hardware achieves a higher accuracy on the test set that a mathematical neural network implemented in software (Extended Data Fig. 3). In addition to the fully connected neuromorphic networks, IPAL demonstrates its effectiveness for other network structures. We expanded the analogue hardware system by adding a sub-board to construct a fully analogue neuromorphic network with a ResNet-like structure (Fig. 2f). The additional analogue AIMC arrays connect the nodes at two non-adjacent layers by sharing input voltages and adding output currents. Note that this shortcut connection is not a simple identity mapping like that in ResNets, but rather a trainable mapping. This extra shortcut connection in the analogue neuromorphic networks can tackle the degradation problem raised by increasing depth of the network. We used IPAL to train all connections in this analogue neuromorphic network. The results shown in Fig. 2g demonstrate a classification accuracy of 99.14% on the training set and 96.49% on the test set, both of which are higher than those achieved by the fully connected neuromorphic network (Fig. 2d). Furthermore, we used IPAL to successfully train a single-layer analogue neuromorphic network for the XOR classification task (Supplementary Information Section 3.1 and Extended Data Fig. 4), further demonstrating the universal use of IPAL for different network structures. Highly fault-tolerant neuromorphic hardware networks IPAL exhibits great adaptability even when unpredictable hardware variations and internal dynamic changes occur in analogue hardware systems. This adaptability can help to build highly fault-tolerant analogue neuromorphic hardware networks. To demonstrate this advantage, we used IPAL to train a fully analogue neuromorphic hardware network with unknown activation functions, since the behaviours of analogue hardware-implemented activation units are unavoidably impacted by mismatch effects, voltage offset, material defects and fabrication variations 8 . In the experimental demonstration, analogue CMOS chips with 16-channel reconfigurable nonlinear amplification circuits are used to serve as AUs (see Fig. 3a). Each AU’s amplification could be reconfigured into different activation functions (see Fig. 3b). We initialized the fully analogue neuromorphic network by randomly setting each AU, so the specific activation behaviour of each AU was unknown during the training process, simulating the unpredictable variations encountered in practical analogue hardware systems. We then employed IPAL to train the analogue neuromorphic network, and achieved a recognition accuracy of up to 97.93% and 95.16% on the training set and test set, respectively (see Fig. 3c). Notably, IPAL can also be used to train hardware-defective analogue neuromorphic networks, successfully restoring the functionality of impaired analogue neuromorphic networks (see Fig. 4a). To experimentally demonstrate the self-restoring capability, we randomly caused the failure of 60% of the electrical synapses and/or neurons, and locations of these damaged components are unknown during the training process. The corresponding training results of different hardware-defective neuromorphic networks are shown in Fig. 4b–d. For hardware-intact neuromorphic networks, a high recognition accuracy can be achieved within the first 15 epochs. Subsequently, when a part of the hardware, including AIMC cells and AUs, randomly fails to work, as shown in the insets of Fig. 4b–d, the classification accuracy drastically decreases. Despite this circumstance, IPAL can be employed to continuously train the defective hardware. Eventually, the trained hardware-defective analogue neuromorphic network exhibits a classification accuracy close to that of the hardware-intact neuromorphic networks. It is surprising that the recognition accuracy of the hardware-defective neuromorphic network can still retain 93.38% even when 60% of the synapses fail to work. We further conducted experiments to evaluate how the accuracy depends on the impairment ratio of electrical synapses and neurons, and the corresponding results are shown in Supplementary Information Section 3.3. Interestingly, during the first few epochs of the restoration process, the recognition accuracy increases at a faster rate compared to the training process of a randomly initialized neuromorphic network. The successful restoration of the recognition accuracy strongly indicates that IPAL can adapt to the dynamic hardware changes in the analogue neuromorphic networks, and enable the hardware systems to be hardware-fault-tolerant. Besides, the recognition accuracy of the defective analogue neuromorphic network can be improved to exceed that of the intact network by using a compensation-healing scheme, as schematically shown in Fig. 4e, in which a new hardware is added to the defective network to form a bypass connection. The newly formed neuromorphic network was entirely trained by IPAL and the corresponding experimental results are presented in the Fig. 4f, Extended Data Fig. 8 and 9. With the aid of the bypass network, the classification accuracy exceeds that of the original network. This advantage enables the construction of an analogue AI hardware system in a Lego-like assembly manner (Supplementary Information Section 2.1.3), where the analogue AI can be enhanced by adding new neuromorphic building blocks 57 . Moreover, IPAL can be used to drastically enhance the robustness of analogue neuromorphic networks based on memristive devices (Fig. 5a). Despite its great promise in analogue neuromorphic computing, the practical deployment of memristors is suffering from some issues associated with yield, variability, and endurance. Due to its dynamic adaptivity, IPAL can prevent the functionality of the analogue neuromorphic networks based on memristive devices from being impacted by these issues, making the system highly robust. For proof-of-concept demonstration, we randomly made some of memristors fail to work by using excessive voltage, to mimic memristor crossbar arrays that have undergone stochastic device degradations. We then used IPAL to train the memristive analogue neuromorphic network with different defect rates, with the corresponding results shown in Fig. 5c and Extended Data Fig. 10. Remarkably, we note that the recognition accuracy at different defect rates is much higher than that without using IPAL, and the high accuracy can be nearly immune to the increasing number of defective devices. This strongly indicates that using IPAL for training memristive device-based neuromorphic networks can make their recognition functionalities highly robust. We analyze the conductance states of all memristors after training by IPAL (Fig. 5d), and reveal that the robust recognition functionality arises from the establishment of alternative analogue signal pathways through the surviving memristors. Such ability can unlock the full potential of analogue neuromorphic hardware, making IPAL also suitable for the analogue neuromorphic networks based on other emerging memory devices, such as phase change memory 23 , ferroelectric memory 58 , and magnetoresistive random access memory 35 . Conclusions In conclusion, our work reports a model-free approach that can effectively train neuromorphic networks based on analogue hardware. By leveraging two-step physical operations to obtain the actual gradients of the practical physical system, IPAL eliminates the need for mathematical modelling, offering a significant advantage in training analogue systems. Through experimentation on different neuromorphic networks comprising analogue in-memory computing arrays and activation units, we demonstrate the effectiveness of IPAL despite unpredictable hardware variations or dynamic hardware changes. Remarkably, our approach showcases the ability to restore the recognition accuracy of analogue neuromorphic networks even after many electrical synapses and neurons fail to work. This self-restoring capability, like that of the brain 55 , is crucial for enhancing the robustness of the emerging memristor-based analogue neuromorphic systems. This work validates the feasibility of training fully analogue neuromorphic networks under real-world hardware constraints, and pushes the analogue neuromorphic computing hardware based on emerging memristive devices to practical deployment. Methods Experimental implementation of IPAL Unlike the traditional approach, which aims to train analogue neuromorphic networks based on a mathematical model, IPAL represents a new paradigm that leverages the inherent physical characteristics of these networks for training. Therefore, the implementation of IPAL involves a series of physical operations, such as perturbing and measuring the physical system. In contrast, previous works focused on aligning the analogue hardware system with its mathematical description, requiring the construction of a precise analogue computing system or the development of an accurate mathematical model. Figure 1c illustrates the simplified implementation procedure for one iteration, consisting of three major phases. In the first phase, the training data is inputted into the analogue neuromorphic network using DACs, and the node states are then measured using MUXs and ADCs (multiple ADCs work in parallel). In the second phase, a current perturbation signal is injected into a node using MUXs and a DAC, the output of the last layer in the network is measured by ADCs, and the associated loss is obtained. The gradient of the loss with respect to the current node can then be calculated using the forward difference method. In the third phase, the gradient of loss with respect to the weight and bias is calculated. The MCU on the main-board is employed to control these components and perform simple numerical computations. While the above-mentioned procedure of IPAL is based on the forward difference method, it's worth noting that the central difference method (Supplementary Information Section 1.4) is also applicable, and both methods have been experimentally examined. In the experimental demonstrations shown in Fig. 2–5, we used IPAL based on the central difference method, and a detailed implementation procedure is provided in Supplementary Information Section 2.2. The procedure is described in the form of pseudocode, illustrating the implementation of IPAL-based mini-batch gradient descent on a dataset. It is worth noting that all demonstration experiments in this article were repeated at least three times, demonstrating the reliability and robustness of IPAL. The entire Optdigits dataset including training set (3823 images) and test set (1797 images) is used for the experimental demonstrations of IPAL. Hardware system for IPAL demonstration To demonstrate IPAL, a printed circuit board (PCB) system was built. The system mainly consists of DACs, input drivers, AIMC arrays, activation modules, ADCs, a sub-board for shortcut connection, and an auxiliary controller. The controller is located beneath the AIMC arrays but is not marked in the photo. In the PCB system, a fully analogue neuromorphic network is constructed by connecting AIMC arrays and activation modules alternately. The AIMC arrays are manufactured using standard CMOS technology and are further explained in Extended Data Fig. 1. The activation module is a sub-board that mainly contains a customized analogue chip for achieving multi-channel nonlinear amplification. The DAC used is the DAC7678 produced by TI, which has 8 channels in a single chip. To convert the 8×8 handwritten digits into analogue signals, 8 DACs were used in parallel to provide 64-channel input signals to the first-layer AIMC arrays. An additional DAC was used to provide a constant analogue input, which is connected to the AIMC cells representing the biases in all layers. The ADC used is the ADS131M08 produced by TI, which is used to observe the amplitude of output signals of AUs. Multiple ADCs are used to work in parallel. It should be noted that ADCs are not required to observe hidden nodes during the inference process, as our hardware-based neuromorphic network is an end-to-end analogue system, and the forward propagation process is implemented in one shot. The current perturbation signal is generated by a DAC and an operational amplifier circuit, and is subsequently controlled by the multiplexer (MUX) to add/subtract current into/from the specific node according to Kirchhoff's current law. Additionally, the system controller is the STM32F407, which performs auxiliary functions to control ADCs, DACs, MUXs, activation modules, as well as the read/write operation of the AIMC arrays. Analogue in-memory computing array chip The AIMC array chip is designed and manufactured using 180 nm CMOS technology. It integrates 34×32 AIMC cells, with each AIMC cell containing 8 SRAM cells that store 8-bit weights for analogue multiplication. By sharing the same analogue input in the input column and using Kirchhoff's law to sum the currents to the output row (see Extended Data Fig. 1a), the chip can perform analogue vector-by-matrix multiplication (VMM) in parallel, supporting 34-dimensional analogue input channels and 32-dimensional analogue output channels. The original experimental results of the VMM test are illustrated in Extended Data Fig. 1b, without any correction or calibration. Despite the computing errors due to the non-ideal properties of analogue hardware, IPAL can still train the neuromorphic network to achieve high accuracy performance equivalent to or better than that of a BP-trained digital system (Extended Data Fig. 3), demonstrating its effectiveness and adaptability of IPAL. Analogue activation module The activation module is a sub-PCB that transfers signals from the upstream AIMC array to the downstream AIMC array or the output nodes. The core component of the activation module is a customized analogue chip designed and manufactured using 180 nm CMOS technology. This analogue chip contains 16 activation units, functioning as reconfigurable nonlinear amplification in the analogue neuromorphic network (Extended Data Fig. 1c). As shown in Extended Data Fig. 1d, each AU receives a differential pair of current signals, which are processed by a subtractor circuit and subsequently by a non-linear amplification circuit. The nonlinearity in the circuit stems from the transfer characteristic of the diodes. Moreover, by turning on/off the switches in the circuit, the AU can be reconfigured to exhibit different nonlinear behaviours ( e.g. , like a Sigmoid or ReLU function). Additionally, the chip includes an integrated MUX that allows for the introduction of positive/negative current perturbation into the positive/negative input channel of AU. Training an analogue neuromorphic network with shortcut connection In the experiment (Fig. 2f), inspired by the structure of ResNet, we added a shortcut connection to our analogue neuromorphic network. To implement this, we utilized two additional AIMC arrays representing the shortcut connection skipping the hidden layer. The shortcut connection shares the same input with that of fully connected layer 1 (FC1), and its output is added to the output of FC2 before being fed into the subsequent AUs. The dimensions of FC1, FC2, and the shortcut connection are 65×32, 33×10, and 65×10, respectively. Since we used a differential pair of AIMC cells to realize positive and negative weights, we employed 65×64 AIMC cells for FC1, 33×20 AIMC cells for FC2, and 65×20 AIMC cells for the shortcut connection. All weight connections were updated during the training process. It is important to note that the same perturbation signal was used to train both FC2 and the shortcut connection. We successfully trained the analogue neuromorphic network using IPAL, achieving high accuracy performance on both the training and test sets. This result highlights the universality of IPAL. Training analogue neuromorphic networks with unknown internal variations IPAL has the capability to adapt the intrinsic physical characteristics of analogue hardware, regardless of its mathematical models. We demonstrated this advantage of hardware-fault-tolerance by utilizing IPAL to train neuromorphic networks, without any prior knowledge of the behaviours of AUs (as shown in Fig. 3 and Supplementary Information Section 3.2). In these experiments, the analogue neuromorphic network was initialized by individually setting each AU into a random variant, where different variants respond to input signals with different behaviours. It is important to note that the types of AU remain unknown throughout the whole training process, thus demonstrating that prior knowledge of the AUs is not required for IPAL. Furthermore, our additional experiments revealed that IPAL can also adapt to other non-ideal factors in hardware, such as mismatch effects, voltage offsets, varying component parameters, and parasitic effects. Self-restoring neuromorphic network experiments The analogue neuromorphic network hardware, once manufactured, becomes a dynamic system where its components may experience degradation, impairment, or even failure. Specifically, for neuromorphic networks based on emerging non-volatile memory, the lifespan or endurance of the electrical synapse is inherently limited. Using IPAL to adaptively train the dynamic system is a potential solution to restore the functionality of the analogue neuromorphic networks. In our experimental demonstration, we show that even if analogue neuromorphic networks have undergone some hardware impairments, we can restore their functionality through a re-training process. During the experimental demonstrations, a failed AIMC cell does not output a signal, which is realized with the AIMC cell whose weight always sticks to zero. A failed AU generates a constant output amplitude at the neutral point and does not respond to any input, which is realized by turning off the switch connecting the input of the AU. Note that the failed AUs are hidden layer neurons. In the experiments shown in Fig. 4 and Supplementary Information Section 3.3, we first trained an intact analogue neuromorphic network for the first 15 epochs and then randomly disabled some AIMC cells, AUs, or both. These components remained failed during the subsequent training process. When we employed IPAL to train the defective analogue neuromorphic networks after the 16 th epoch, the failed components did not effectively propagate signals, including the perturbation signals. Hence, despite the changed internal structure, IPAL still adaptively provided the actual gradients for effectively training the impaired analogue neuromorphic networks, thereby enhancing the robustness of the neuromorphic hardware systems. Compensation-healing neuromorphic networks experiments Inspired by the compensation concept in the biological nervous system, we propose a compensation-healing scheme to enhance the performance of analogue neuromorphic networks when the number of surviving components is insufficient to achieve high accuracy. The compensation-healing scheme introduces additional hardware into the impaired neuromorphic network to restore and even enhance its functionality. Due to space limitations, we only show the evolution of recognition accuracy in the main text, and more results for this experiment can be found in Extended Data Fig. 8. In our experiments, we trained the neuromorphic network with 16 hidden neurons within the first 15 epochs. At the 16 th epoch, 60% of the AIMC cells and AUs failed to work. We then added a bypass neuromorphic network with 16 hidden neurons to compensate for the impaired neuromorphic network. The input of the compensation network was connected to the input of the impaired network, sharing the same input signal. The output current of the compensation network was added to the output current of the impaired network using Kirchhoff's current law. Subsequently, we used IPAL to train the rebuilt analogue neuromorphic network with the new structure, achieving improved accuracy performance compared to the original system. To compare the self-restoring scheme with the compensation-healing scheme, we conducted an additional experiment, as shown in Extended Data Fig. 9. This experiment consists of two stages. The first stage (0-66 epochs) of the experiment is similar to the one shown in Fig. 4f, showing that the recognition accuracy increases but does not surpass the accuracy before the hardware impairment. In the second stage (67-117 epochs), we introduce a compensatory neuromorphic network into the impaired one and continuously train the entire neuromorphic network with the new structure, ultimately achieving an enhancement in accuracy. Fabrication and integration of 1T1R memristor chips To produce our 1T1R chips, the CMOS circuits were fabricated by a commercial semiconductor manufacturer, and the memristors were fabricated in our university lab. We integrated the memristors with the top vias on CMOS chips. We deposited Ta/Au/Pd as the bottom electrodes, HfO 2 as the switching layer, and Ta/Pd/Au as the top electrodes. The Au and Pd metals were deposited by electron beam evaporation, the Ta metal was deposited by sputtering, and the HfO 2 was obtained through atomic layer deposition. The top and bottom electrodes were patterned using the photolithography and liftoff processes, where negative photoresist (NR9-1500PY) was used. Patterning of the switching layer was carried out through photolithography and reactive ion etching (RIE). Extended Data Fig. 1e and f shows the architecture of the 1T1R chip, as well as the results of parallel analogue VMM test. Experimental demonstration using memristive devices As an emerging AIMC device, memristors suffer from yield issues during fabrication and stochastic degradation during operation. These problems make some of the memristors fail to switch, impacting the normal functionality of memristor-based neuromorphic networks. IPAL automatically adapts to diverse types of nonidealities that occur in memristors, such as short or open devices, non-linear I-V characteristics, and wire resistance effects. Thus, IPAL can provide the correct gradients in the physical system to update the remaining memristors and unlock the full potential of hardware-defective neuromorphic networks. In the experiments shown in Fig. 5, we first trained memristor-based neuromorphic networks. We then randomly damaged some of the memristors by using excessive voltage, creating memristor crossbar arrays with different degrees of hardware degradation. Subsequently, we used IPAL to re-train the memristor-based neuromorphic networks and realized high recognition accuracy. In sharp contrast, without using IPAL, the accuracy is strongly affected by the defect rate of memristors. In these demonstrations, we also used the full test set in the Optdigits dataset to evaluate the performance of the memristor-based neuromorphic networks. Declarations Acknowledgments This work was supported in part by the National Key R&D Program of China under Grant 2023YFF1203600, the National Natural Science Foundation of China (62122036, 62034004, 61921005, 62305155, 12074176, 12322407), the Strategic Priority Research Program of the Chinese Academy of Sciences (XDB44000000), the Leading-edge Technology Program of Jiangsu Natural Science Foundation (BK20232004), the China Postdoctoral Science Foundation (2023M731582, BX20230153), and the Jiangsu Funding Program for Excellent Postdoctoral Talent (2023ZB079). F.M. would like to acknowledge support from the AIQ Foundation. C.W. would like to acknowledge support from the Jiangsu Funding Program for Excellent Postdoctoral Talent (2023ZB079). The microfabrication center of the National Laboratory of Solid State Microstructures (NLSSM), the Innovation Program for Quantum Science and Technology and the e-Science Center of Collaborative Innovation Center of Advanced Microstructures are acknowledged for their technique support. Author contributions C.W. and Y.Z. equally contributed to this work. C.W., Y.Z., F.M., and S.J.L. conceived the idea and designed the experiments. F.M. and S.J.L. supervised the whole project. Y.Z. and C.W. designed the PCB systems and conducted the experiments. C.W. and Y.Z. analyzed experimental data. C.W. and X.J.Y. designed the AIMC and AU chips. C.W., W.W., Z.Z.Y. fabricated the memristor chips. Z.Z.Y., Y.S., S.D., D.K., X.W., and J.S. helped in the circuit design, assembly, and measurement. P.W., Y.Y., C.P., and B.C. discussed the results. C.W., Y.Z., S.J.L. and F.M. co-wrote the manuscript. Competing interests Authors declare that they have no competing interests. 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Supplementary Files SupplementaryInformation.docx Supplementary_Information SupplementaryVideo1BeforeIPALtraining.mp4 Supplementary_Video_1 SupplementaryVideo2AfterIPALtraining.mp4 Supplementary_Video_2 ExtendedData.docx Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-4651980","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Physical Sciences - Article","associatedPublications":[],"authors":[{"id":324766497,"identity":"e428fe97-9527-4b12-bc78-5dff0ba0c885","order_by":0,"name":"Feng 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University","correspondingAuthor":false,"prefix":"","firstName":"Yuekun","middleName":"","lastName":"Yang","suffix":""},{"id":324766510,"identity":"428860f2-a11b-4375-8277-e1e6faf7aed3","order_by":13,"name":"Chen Pan","email":"","orcid":"","institution":"Nanjing University of Science and Technology","correspondingAuthor":false,"prefix":"","firstName":"Chen","middleName":"","lastName":"Pan","suffix":""},{"id":324766511,"identity":"54db0f1f-720f-4a47-9768-09597ca4c5a8","order_by":14,"name":"Bin Cheng","email":"","orcid":"https://orcid.org/0000-0002-2932-4370","institution":"Nanjing University of Science and Technology","correspondingAuthor":false,"prefix":"","firstName":"Bin","middleName":"","lastName":"Cheng","suffix":""},{"id":324766512,"identity":"b34ec449-517d-49e0-a6aa-98e360e0bb2f","order_by":15,"name":"Shi-Jun Liang","email":"","orcid":"https://orcid.org/0000-0003-3235-7621","institution":"Nanjing University","correspondingAuthor":false,"prefix":"","firstName":"Shi-Jun","middleName":"","lastName":"Liang","suffix":""}],"badges":[],"createdAt":"2024-06-28 04:25:09","currentVersionCode":1,"declarations":{"humanSubjects":false,"vertebrateSubjects":false,"conflictsOfInterestStatement":false,"humanSubjectEthicalGuidelines":false,"humanSubjectConsent":false,"humanSubjectClinicalTrial":false,"humanSubjectCaseReport":false,"vertebrateSubjectEthicalGuidelines":false},"doi":"10.21203/rs.3.rs-4651980/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-4651980/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":60066935,"identity":"d50974db-cd49-4b18-a2f1-faca2d88480d","added_by":"auto","created_at":"2024-07-11 10:02:56","extension":"png","order_by":1,"title":"Figure 1","display":"","copyAsset":false,"role":"figure","size":1212999,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eIntrinsic physics-adaptive learning. a, \u003c/strong\u003eLimitation of model-based training approach for fully analogue neuromorphic networks. Fully analogue hardware system can hardly be described with an exact mathematical model due to some inevitable and unknown non-ideal factors such as device degradations, fabrication variations, and parasitic effects.\u003cstrong\u003e b, \u003c/strong\u003eIntrinsic physics-adaptive learning (IPAL) is used to train analogue neuromorphic networks containing non-ideal hardware. \u003cstrong\u003ec,\u003c/strong\u003e Core idea of intrinsic physics-adaptive learning. By applying perturbation signals and observing the resulting response of the hardware system, IPAL can obtain the actual gradients with respect to the associated physical parameters and update the weights accordingly.\u003c/p\u003e","description":"","filename":"1.png","url":"https://assets-eu.researchsquare.com/files/rs-4651980/v1/2e9a9718db85cb7730346aff.png"},{"id":60067663,"identity":"515e81ab-74b9-4d40-96c4-98e42dc9f7ec","added_by":"auto","created_at":"2024-07-11 10:10:56","extension":"png","order_by":2,"title":"Figure 2","display":"","copyAsset":false,"role":"figure","size":1803563,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eExperimental demonstration of IPAL. a, \u003c/strong\u003ePhotograph of the hardware system. \u003cstrong\u003eb, \u003c/strong\u003eSchematic diagram of the system. We connect the analogue in-memory computing (AIMC) arrays and analogue activation units (AUs) alternately to realize an end-to-end analogue neuromorphic network, which can perform an image recognition in one shot. Other circuits assist in the implementation of IPAL. \u003cstrong\u003ec,\u003c/strong\u003e Structure of the fully analogue neuromorphic network for handwritten digit classification. Each weight value is represented by a differential pair of AIMC cells. \u003cstrong\u003ed,\u003c/strong\u003e Classification accuracy increases up to 98.69% and 96.16% on the training and test sets, respectively. The loss value decreases by two orders of magnitude. \u003cstrong\u003ee,\u003c/strong\u003e Confusion matrix of the measured classification results on the test set. \u003cstrong\u003ef, \u003c/strong\u003eWe add an extra sub-board containing two AIMC arrays to realize an additional shortcut connection that skips two layers. Note that this shortcut connection is a trainable mapping. \u003cstrong\u003eg, \u003c/strong\u003eIPAL demonstrates its effectiveness on this structure with the higher recognition accuracy. The shortcut connection and the 2\u003csup\u003end\u003c/sup\u003e fully connected layer are trained concurrently by applying the identical perturbation.\u003c/p\u003e","description":"","filename":"2.png","url":"https://assets-eu.researchsquare.com/files/rs-4651980/v1/586dc308cc555ce5dbbf1ab4.png"},{"id":60067664,"identity":"ec7dbed3-b8a5-4b37-a459-2c848b1d9e1b","added_by":"auto","created_at":"2024-07-11 10:10:56","extension":"png","order_by":3,"title":"Figure 3","display":"","copyAsset":false,"role":"figure","size":569197,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eAdaptability to unknown hardware variations. a, \u003c/strong\u003eThe analogue chip consists of 16-channel reconfigurable nonlinear amplification circuits as analogue AUs. \u003cstrong\u003eb\u003c/strong\u003e,\u003cstrong\u003e \u003c/strong\u003eThe AUs can be reconfigured into diverse variants exhibiting different behaviours. \u003cstrong\u003ec, \u003c/strong\u003eIPAL can effectively train a fully analogue neuromorphic network with unknown hardware variations. In this experiment, the types of AUs are randomly set, and their behaviours remain unknown throughout the training process.\u003c/p\u003e","description":"","filename":"3.png","url":"https://assets-eu.researchsquare.com/files/rs-4651980/v1/0428ad9536b2f5193ef963e0.png"},{"id":60066936,"identity":"f902def6-59fa-4aed-94f0-7a0f1ebad4d0","added_by":"auto","created_at":"2024-07-11 10:02:56","extension":"png","order_by":4,"title":"Figure 4","display":"","copyAsset":false,"role":"figure","size":1690275,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eExperimental demonstration of self-restoring ability. a, \u003c/strong\u003eThe schematic of realizing a self-restoring analogue neuromorphic network by using IPAL. A defective analogue neuromorphic network can still retain a high recognition accuracy, as IPAL can adapt to the dynamic changes in hardware structure during training process. \u003cstrong\u003eb-d, \u003c/strong\u003eThe defective analogue neuromorphic networks can be trained to accurately recognize digit images even when 60% of electrical synapses and/or neurons fail to work, as shown in the insets. \u003cstrong\u003ee, \u003c/strong\u003eThe compensation-healing scheme of the hardware-impaired analogue neuromorphic network, in which the compensation hardware is added to form a new analogue neuromorphic network. \u003cstrong\u003ef, \u003c/strong\u003eExperimental demonstration of the compensation-healing scheme. The scheme further enhances the accuracy performance of the hardware-impaired analogue neuromorphic network.\u003c/p\u003e","description":"","filename":"4.png","url":"https://assets-eu.researchsquare.com/files/rs-4651980/v1/3d2e684cd4a06b2e05f0f230.png"},{"id":60066939,"identity":"1ade6521-f340-4fe3-91a8-54cecf0d1e2e","added_by":"auto","created_at":"2024-07-11 10:02:56","extension":"png","order_by":5,"title":"Figure 5","display":"","copyAsset":false,"role":"figure","size":1591535,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eExperimental demonstration of IPAL on memristive crossbar arrays. a,\u003c/strong\u003e Optical image of the fabricated 1T1R memristive crossbar array. \u003cstrong\u003eb, \u003c/strong\u003eIPAL is used to train analogue neuromorphic networks based on memristive crossbar arrays that have undergone stochastic device degradations. FC layer, fully connected layer. \u003cstrong\u003ec,\u003c/strong\u003e Recognition accuracy comparison of the defective analogue memristor-based neuromorphic networks with and without IPAL. \u003cstrong\u003ed,\u003c/strong\u003e Conductance matrices after training with IPAL. IPAL provides actual gradients in the defective hardware, effectively updating the weights of the defective memristive hardware.\u003c/p\u003e","description":"","filename":"5.png","url":"https://assets-eu.researchsquare.com/files/rs-4651980/v1/a86ec94c560a1e9fda301f14.png"},{"id":104397617,"identity":"e54d05d4-2335-470f-9392-1f2233b93f90","added_by":"auto","created_at":"2026-03-11 11:53:03","extension":"pdf","order_by":0,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":8879364,"visible":true,"origin":"","legend":"","description":"","filename":"manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-4651980/v1/2fa4cbb3-95cc-44a4-aeed-b80e00f924e4.pdf"},{"id":60066940,"identity":"d20e7192-6769-471a-9403-538921b2e75c","added_by":"auto","created_at":"2024-07-11 10:02:56","extension":"docx","order_by":1,"title":"","display":"","copyAsset":false,"role":"supplement","size":29956805,"visible":true,"origin":"","legend":"Supplementary_Information","description":"","filename":"SupplementaryInformation.docx","url":"https://assets-eu.researchsquare.com/files/rs-4651980/v1/b0dd09c309553d04de64cec4.docx"},{"id":60066942,"identity":"4b640917-784c-4791-9dfa-3557f7a336a8","added_by":"auto","created_at":"2024-07-11 10:02:57","extension":"mp4","order_by":2,"title":"","display":"","copyAsset":false,"role":"supplement","size":34086331,"visible":true,"origin":"","legend":"Supplementary_Video_1","description":"","filename":"SupplementaryVideo1BeforeIPALtraining.mp4","url":"https://assets-eu.researchsquare.com/files/rs-4651980/v1/b3b12d79c74930f7d0cde0da.mp4"},{"id":60066943,"identity":"b296b37c-511f-4111-bbd7-9b3c9b0325e6","added_by":"auto","created_at":"2024-07-11 10:02:57","extension":"mp4","order_by":3,"title":"","display":"","copyAsset":false,"role":"supplement","size":34044987,"visible":true,"origin":"","legend":"Supplementary_Video_2","description":"","filename":"SupplementaryVideo2AfterIPALtraining.mp4","url":"https://assets-eu.researchsquare.com/files/rs-4651980/v1/c0ff719a5f1bb264c73699ac.mp4"},{"id":60066941,"identity":"8c19e424-ce10-4208-af32-31563a412e41","added_by":"auto","created_at":"2024-07-11 10:02:57","extension":"docx","order_by":4,"title":"","display":"","copyAsset":false,"role":"supplement","size":15338065,"visible":true,"origin":"","legend":"","description":"","filename":"ExtendedData.docx","url":"https://assets-eu.researchsquare.com/files/rs-4651980/v1/7751432d5f1e5ad5355fd534.docx"}],"financialInterests":"There is \u003cb\u003eNO\u003c/b\u003e Competing Interest.","formattedTitle":"Robust analogue neuromorphic hardware networks using intrinsic physics-adaptive learning","fulltext":[{"header":"Main","content":"\u003cp\u003eThe hardware implementation of fully analogue neuromorphic networks\u003csup\u003e10-19\u003c/sup\u003e, achieved by tiling multiple in-memory computing arrays and analogue nonlinear units\u003csup\u003e20-25\u003c/sup\u003e, can significantly enhance the energy efficiency of artificial intelligence\u003csup\u003e26-31\u003c/sup\u003e. This is because analogue hardware systems, such as electrical and optical systems, can utilize the intrinsic physical characteristics of materials and devices to perform energy-efficient computations\u003csup\u003e32-48\u003c/sup\u003e. However, the practical deployment of such analogue hardware systems remains challenging\u003csup\u003e9, 49\u003c/sup\u003e. One primary issue is\u0026nbsp;that\u0026nbsp;the fundamental physical characteristics\u0026nbsp;are sensitive to\u0026nbsp;variations in material compositions and physical dimensions of analogue devices\u003csup\u003e40\u003c/sup\u003e, but it is impossible to achieve\u0026nbsp;absolute precision in the manufacturing process\u003csup\u003e50\u003c/sup\u003e. The sensitivity, along with resulting variations in hardware behaviours, makes it extremely difficult to use a specific mathematical model to precisely describe these analogue hardware systems\u003csup\u003e46, 47\u003c/sup\u003e. As a result, modelling errors accumulate in fully analogue multilayer neuromorphic networks, making traditional mathematical model-based training approaches problematic. This explains why existing analogue neuromorphic hardware networks often fall short of their software counterparts in terms of recognition accuracy\u003csup\u003e10, 51, 52\u003c/sup\u003e. Furthermore, during the training process, stochastic degradations of analogue devices in the hardware systems lead to dynamic changes in the internal structure of the network\u003csup\u003e43, 53\u003c/sup\u003e, severely compromising the robustness and reliability of the system\u003csup\u003e54\u003c/sup\u003e. Therefore, there is a pressing need to develop a learning approach capable of accommodating analogue hardware variabilities and dynamic internal structural changes, enabling hardware-fault tolerance in training fully analogue neuromorphic networks.\u003c/p\u003e\n\u003cp\u003eIn this article, we demonstrate a training approach called IPAL to achieve hardware-fault tolerance in analogue hardware-implemented neuromorphic networks. This approach enables a fully analogue neuromorphic network to achieve high\u0026nbsp;recognition accuracy even\u0026nbsp;surpassing that of a mathematical network trained by the backpropagation (BP) algorithm. Moreover, the physical nature of the IPAL approach makes it adaptive to unpredictable internal hardware variations and unknown hardware changes during the\u0026nbsp;training\u0026nbsp;processes of fully analogue neuromorphic networks. This ability further enables a defective\u0026nbsp;neuromorphic network\u0026nbsp;to restore its functionality, and particularly favors\u0026nbsp;emerging memristive devices, as it can prevent the functionality of analogue computing systems from the impacts of device defects and degradations.\u0026nbsp;The demonstrated training approach in our work can greatly enhance the robustness of analogue neuromorphic hardware networks and provide superior fault-tolerant performance\u0026nbsp;like that in the brain\u003csup\u003e55\u003c/sup\u003e.\u003c/p\u003e\n\u003ch2\u003eIntrinsic physics-adaptive learning\u003c/h2\u003e\n\u003cp\u003eTo achieve superior hardware-fault-tolerance in fully analogue neuromorphic networks, it is essential to train these analogue systems by harnessing their intrinsic physical characteristics, without relying on mathematical\u0026nbsp;modelling. Due to considerations of effectiveness and generalizability, the primary objective for training analogue neuromorphic networks is to derive the actual gradients of physical parameters in these physical computing systems\u003csup\u003e56\u003c/sup\u003e. IPAL is such an approach that can utilize physical operations, such as perturbing the physical computing system and observing the resulting response, rather than utilizing mathematical modelling of the physical systems to obtain the actual gradients and train neuromorphic hardware networks.\u003c/p\u003e\n\u003cp\u003eThe core idea of IPAL is introduced in Fig. 1, which illustrates the basic operations to obtain the actual gradient in a fully analogue hardware-implemented neuromorphic network. In this analogue hardware system, \u003cstrong\u003ea\u003c/strong\u003e\u003cem\u003e\u003csup\u003el\u003c/sup\u003e\u003c/em\u003e represents the output signals of the \u003cem\u003el\u003csup\u003eth\u003c/sup\u003e\u003c/em\u003e-layer neurons; \u003cstrong\u003e\u003cem\u003ez\u003c/em\u003e\u003c/strong\u003e\u003cem\u003e\u003csup\u003el\u003c/sup\u003e\u003c/em\u003e represents the input signals of the \u003cem\u003el\u003csup\u003eth\u003c/sup\u003e\u003c/em\u003e-layer neurons and also the output signals of the \u003cem\u003el\u003csup\u003eth\u003c/sup\u003e\u003c/em\u003e-layer synaptic connection; and \u003cstrong\u003eW\u003c/strong\u003e\u003cem\u003e\u003csup\u003el\u003c/sup\u003e\u003c/em\u003e denotes\u003cem\u003e\u003csup\u003e\u0026nbsp;\u003c/sup\u003e\u003c/em\u003ethe weights of the \u003cem\u003el\u003csup\u003eth\u003c/sup\u003e\u003c/em\u003e-layer synaptic connection. The weights in all layers are randomly initialized before training. As shown in Fig. 1c, during the implementation of IPAL, we first feed the analogue signal vector representing the training data \u003cstrong\u003ex\u003c/strong\u003e\u003csub\u003etrain\u003c/sub\u003e into the input layer of the analogue neuromorphic network, denoted by \u003cstrong\u003ea\u003c/strong\u003e\u003csup\u003e0\u003c/sup\u003e. The forward propagation in the hardware system is completed in one shot, and we can measure the results \u003cstrong\u003ey\u003c/strong\u003e at the output layer, which is used for calculating the error value \u003cstrong\u003e\u003cem\u003eLoss\u003c/em\u003e\u003c/strong\u003e in conjunction with the \u003cstrong\u003ey\u003c/strong\u003e\u003csub\u003etrain\u003c/sub\u003e of the training data. We then perturb the hardware system by adding a perturbation signal \u0026Delta;\u003cstrong\u003e\u003cem\u003ez\u0026nbsp;\u003c/em\u003e\u003c/strong\u003eonto the input signal of a selected neuron. The perturbation will propagate forward through the analogue neuromorphic network. Thereby we can measure the perturbed output signals \u003cstrong\u003ey\u003c/strong\u003e\u003cem\u003e\u0026apos;\u003c/em\u003e, resulting in a new error value \u003cstrong\u003e\u003cem\u003eLoss\u003c/em\u003e\u003c/strong\u003e\u003cem\u003e\u0026apos;\u003c/em\u003e. Based on the measured results, the error perturbation is defined as \u0026Delta;\u003cstrong\u003e\u003cem\u003eLoss = Loss\u003c/em\u003e\u003c/strong\u003e\u003cem\u003e\u0026apos;\u003cstrong\u003e\u0026nbsp;\u0026ndash; Loss\u003c/strong\u003e\u003c/em\u003e.\u0026nbsp;According to the finite difference method, the weight gradients\u003cstrong\u003e\u003cem\u003e\u0026nbsp;\u003c/em\u003e\u003c/strong\u003e\u003cstrong\u003e\u0026part;\u003cem\u003eLoss\u003c/em\u003e\u003c/strong\u003e/\u003cstrong\u003e\u0026part;W\u003c/strong\u003e\u003cem\u003e\u003csup\u003el\u003c/sup\u003e\u003cstrong\u003e\u0026nbsp;\u003c/strong\u003e\u003c/em\u003ecan be obtained via \u003cstrong\u003ea\u003c/strong\u003e\u003cem\u003e\u003csup\u003el\u003c/sup\u003e\u003c/em\u003e\u003csup\u003e-1\u003c/sup\u003e\u0026times;\u0026Delta;\u003cstrong\u003e\u003cem\u003eLoss\u003c/em\u003e\u003c/strong\u003e/\u0026Delta;\u003cstrong\u003e\u003cem\u003ez\u003c/em\u003e\u003c/strong\u003e, in which\u003cem\u003e\u0026nbsp;\u003c/em\u003eall the quantities can be experimentally measured. By applying the perturbation into different nodes and traversing a batch of training data, we can collect and accumulate weight gradients of all electrical synapses, and then update the weights according to the weight gradients, following \u003cstrong\u003e\u0026Delta;W\u0026nbsp;\u003c/strong\u003e=\u003cstrong\u003e\u0026nbsp;\u0026Sigma;\u0026nbsp;\u003c/strong\u003e-\u003cem\u003e\u0026eta;\u003c/em\u003e\u0026times;\u003cstrong\u003e\u0026part;\u003cem\u003eLoss\u003c/em\u003e\u003c/strong\u003e/\u003cstrong\u003e\u0026part;W\u003c/strong\u003e,\u003cstrong\u003e\u0026nbsp;\u003c/strong\u003ewhere \u003cem\u003e\u0026eta;\u003c/em\u003e represents the learning rate. In this way, the analogue hardware-implemented neuromorphic network can be effectively trained without any knowledge of its mathematical model. More detailed implementation of IPAL is provided in Methods and Supplementary Information Section 2.2.\u003c/p\u003e\n\u003ch2\u003eExperimental verification of intrinsic physics-adaptive learning\u003c/h2\u003e\n\u003cp\u003eWe experimentally verified the validity of IPAL on a customized hardware system (Fig. 2a), which contains an end-to-end fully analogue neuromorphic network implemented by alternately connecting analogue in-memory computing (AIMC) chips and analogue activation units (AUs). The AIMC chips are employed as electrical synapses to perform parallel vector-matrix multiplications (VMMs) in analogue domain, and the AUs function as electrical neurons to realize nonlinear functions in analogue domain. Each AIMC chip contains 34\u0026times;32 AIMC cells, supporting a 34-dimensional input vector and a 32-dimensional output vector (Extended Data Fig. 1a). Using the differential scheme, an AIMC chip represents a 34\u0026times;16 connection matrix with positive and negative weight values. Due to the parallel architecture of the AIMC chip, we can construct a larger connection weight matrix (68\u0026times;32) by combining four AIMC chips to perform parallel vector-matrix multiplications. Each AU is a nonlinear amplification circuit with a differential pair of two input signals, thereby realizing both positive and negative weights (Extended Data Fig. 1d). To implement IPAL, other peripheral circuits are also included in the hardware system, as illustrated in the schematic diagram in Fig. 2b. The analogue-to-digital converters (ADCs) and multiplexers (MUX) are used to measure the output signals of AUs, digital-to-analogue converters (DACs) are used to convert the handwritten digit images into analogue input signals of the first-layer AIMC arrays, and the MCU is used as the controller of the system. For more details on the hardware, please refer to Methods.\u003c/p\u003e\n\u003cp\u003eAs a proof of concept, we trained a fully connected neuromorphic network (Fig. 2c) and used handwritten digits recognition task (Optdigits dataset) to benchmark the accuracy performance of IPAL. The results (Fig. 2d, e) demonstrate that the classification accuracy exceeded 90% within the first 5 epochs. After 200 epochs of training, the classification accuracy reached 98.69% on the training set and 96.16% on the test set. Meanwhile, the loss value decreased by two orders of magnitude. Figure 2e shows the confusion matrix of measured classification accuracy on the test set, and Extended Data Fig. 2a exhibits the evolution of the weight distributions in AIMC arrays. Moreover, the IPAL-trained analogue neuromorphic network demonstrates a closer alignment in accuracy performance between the training and test sets than that in the BP-trained mathematical model. This suggests that our approach may mitigate the overfitting issue. As a result, our fully analogue hardware achieves a higher accuracy on the test set that a mathematical neural network implemented in software (Extended Data Fig. 3).\u003c/p\u003e\n\u003cp\u003eIn addition to the fully connected neuromorphic networks, IPAL demonstrates its effectiveness for other network structures. We expanded the analogue hardware system by adding a sub-board to construct a fully analogue neuromorphic network with a ResNet-like structure (Fig. 2f). The additional analogue AIMC arrays connect the nodes at two non-adjacent layers by sharing input voltages and adding output currents. Note that this shortcut connection is not a simple identity mapping like that in ResNets, but rather a trainable mapping.\u0026nbsp;This extra shortcut connection in the analogue neuromorphic networks can tackle the degradation problem raised by increasing depth of the network. We used IPAL to train all connections in this analogue neuromorphic network. The results shown in Fig. 2g demonstrate a classification accuracy of 99.14% on the training set and 96.49% on the test set, both of which are higher than those achieved by the fully connected neuromorphic network (Fig. 2d). Furthermore, we used IPAL to successfully train a single-layer analogue neuromorphic network for the XOR classification task (Supplementary Information Section 3.1 and Extended Data Fig. 4), further demonstrating the universal use of IPAL for different network structures.\u003c/p\u003e\n\u003ch2\u003eHighly fault-tolerant neuromorphic hardware networks\u003c/h2\u003e\n\u003cp\u003eIPAL\u0026nbsp;exhibits great\u0026nbsp;adaptability even\u0026nbsp;when\u0026nbsp;unpredictable hardware variations and internal dynamic changes occur\u0026nbsp;in\u0026nbsp;analogue hardware systems. This adaptability can help to build highly fault-tolerant analogue neuromorphic hardware networks. To demonstrate this advantage, we used IPAL to train a fully analogue neuromorphic hardware network with unknown activation functions, since the behaviours of analogue hardware-implemented activation units are unavoidably impacted by mismatch effects, voltage offset, material defects and fabrication variations\u003csup\u003e8\u003c/sup\u003e. In the experimental demonstration, analogue CMOS chips with 16-channel reconfigurable nonlinear amplification circuits are used to serve as AUs (see Fig. 3a). Each AU\u0026rsquo;s amplification could be reconfigured into different activation functions (see Fig. 3b). We initialized the fully analogue neuromorphic network by randomly setting each AU, so the specific activation behaviour of each AU was unknown during the training process, simulating the unpredictable variations encountered in practical analogue hardware systems. We then employed IPAL to train the analogue neuromorphic network, and achieved a recognition accuracy of up to 97.93% and 95.16% on the training set and test set, respectively (see Fig. 3c).\u003c/p\u003e\n\u003cp\u003eNotably, IPAL can also be used to train hardware-defective analogue neuromorphic networks, successfully restoring the functionality of impaired analogue neuromorphic networks (see Fig. 4a). To experimentally demonstrate the self-restoring capability, we randomly caused the failure of 60% of the electrical synapses and/or neurons, and locations of these damaged components are unknown during the training process. The corresponding training results of different hardware-defective neuromorphic networks are shown in Fig. 4b\u0026ndash;d. For hardware-intact neuromorphic networks, a high recognition accuracy can be achieved within the first 15 epochs. Subsequently, when a part of the hardware, including AIMC cells and AUs, randomly fails to work, as shown in the insets of Fig. 4b\u0026ndash;d, the classification accuracy drastically decreases. Despite this circumstance, IPAL can be employed to continuously train the defective hardware. Eventually, the trained hardware-defective analogue neuromorphic network exhibits a classification accuracy close to that of the hardware-intact neuromorphic networks. It is surprising that the recognition accuracy of the hardware-defective neuromorphic network can still retain 93.38% even when 60% of the synapses fail to work. We further conducted experiments to evaluate how the accuracy depends on the impairment ratio of electrical synapses and neurons, and the corresponding results are shown in Supplementary Information Section 3.3. Interestingly, during the first few epochs of the restoration process, the recognition accuracy increases at a faster rate compared to the training process of a randomly initialized neuromorphic network. The successful restoration of the recognition accuracy strongly indicates that IPAL can adapt to the dynamic hardware changes in the analogue neuromorphic networks, and enable the hardware systems to be hardware-fault-tolerant.\u003c/p\u003e\n\u003cp\u003eBesides, the recognition accuracy of the defective analogue neuromorphic network can be improved to exceed that of the intact network by using a compensation-healing scheme, as schematically shown in Fig. 4e, in which a new hardware is added to the defective network to form a bypass connection. The newly formed neuromorphic network was entirely trained by IPAL and the corresponding experimental results are presented in the Fig. 4f, Extended Data Fig. 8 and 9. With the aid of the bypass network, the classification accuracy exceeds that of the original network. This advantage enables the construction of an analogue AI hardware system in a Lego-like assembly manner (Supplementary Information Section 2.1.3), where the analogue AI can be enhanced by adding new neuromorphic building blocks\u003csup\u003e57\u003c/sup\u003e.\u003c/p\u003e\n\u003cp\u003eMoreover, IPAL can be used to drastically enhance the robustness of analogue neuromorphic networks based on memristive devices (Fig. 5a). Despite its great promise in analogue neuromorphic computing, the practical deployment of memristors is suffering from some issues associated with yield, variability, and endurance. Due to its dynamic adaptivity, IPAL can prevent the functionality of the analogue neuromorphic networks based on memristive devices from being impacted by these issues, making the system highly robust.\u0026nbsp;For proof-of-concept demonstration, we randomly made some of memristors fail to work by using excessive voltage, to mimic memristor crossbar arrays that have undergone stochastic device degradations. We then used IPAL to train the memristive analogue neuromorphic network with different defect rates, with the corresponding results shown in Fig. 5c and Extended Data Fig. 10. Remarkably, we note that the recognition accuracy at different defect rates is much higher than that without using IPAL, and the high accuracy can be nearly immune to the increasing number of defective devices. This strongly indicates that using IPAL for training memristive device-based neuromorphic networks can make their recognition functionalities highly robust. We analyze the conductance states of all memristors after training by IPAL (Fig. 5d), and reveal that the robust recognition functionality arises from the establishment of alternative analogue signal pathways through the surviving memristors. Such ability can unlock the full potential of analogue neuromorphic hardware, making IPAL also suitable for the analogue neuromorphic networks based on other emerging memory devices, such as phase change memory\u003csup\u003e23\u003c/sup\u003e, ferroelectric memory\u003csup\u003e58\u003c/sup\u003e, and magnetoresistive random access memory\u003csup\u003e35\u003c/sup\u003e.\u003c/p\u003e"},{"header":"Conclusions","content":"\u003cp\u003eIn conclusion, our work reports a model-free approach that can effectively train neuromorphic networks based on analogue hardware. By leveraging two-step physical operations to obtain the actual gradients of the practical physical system, IPAL eliminates the need for mathematical\u0026nbsp;modelling, offering a significant advantage in training analogue systems. Through experimentation on different neuromorphic networks comprising analogue in-memory computing arrays and activation units, we demonstrate the effectiveness of IPAL despite unpredictable hardware variations or dynamic hardware changes. Remarkably, our approach showcases the ability to restore the recognition accuracy of analogue neuromorphic networks even after many electrical synapses and neurons fail to work.\u0026nbsp;This self-restoring capability, like that of the brain \u003csup\u003e55\u003c/sup\u003e,\u0026nbsp;is crucial for enhancing the robustness of the emerging memristor-based analogue neuromorphic systems. This work validates the feasibility of training fully analogue neuromorphic networks under real-world hardware constraints, and pushes the analogue neuromorphic computing hardware based on emerging memristive devices to practical deployment.\u003c/p\u003e"},{"header":"Methods","content":"\u003cp\u003eExperimental implementation of IPAL\u0026nbsp;\u003c/p\u003e\n\u003cp\u003eUnlike the traditional approach, which aims to train analogue neuromorphic networks based on a mathematical model, IPAL represents a new paradigm that leverages the inherent physical characteristics of these networks for training. Therefore, the implementation of IPAL involves a series of physical operations, such as perturbing and measuring the physical system. In contrast, previous works focused on aligning the analogue hardware system with its mathematical description, requiring the construction of a precise analogue computing system or the development of an accurate mathematical model.\u003c/p\u003e\n\u003cp\u003eFigure 1c illustrates the simplified implementation procedure for one iteration, consisting of three major phases. In the first phase, the training data is inputted into the analogue neuromorphic network using DACs, and the node states are then measured using MUXs and ADCs (multiple ADCs work in parallel). In the second phase, a current perturbation signal is injected into a node using MUXs and a DAC, the output of the last layer in the network is measured by ADCs, and the associated loss is obtained. The gradient of the loss with respect to the current node can then be calculated using the forward difference method. In the third phase, the gradient of loss with respect to the weight and bias is calculated. The MCU on the main-board is employed to control these components and perform simple numerical computations.\u0026nbsp;\u003c/p\u003e\n\u003cp\u003eWhile the above-mentioned procedure of IPAL is based on the forward difference method, it\u0026apos;s worth noting that the central difference method (Supplementary Information Section 1.4) is also applicable, and both methods have been experimentally examined. In the experimental demonstrations shown in Fig. 2\u0026ndash;5, we used IPAL based on the central difference method, and a detailed implementation procedure is provided in Supplementary Information Section 2.2. The procedure is described in the form of pseudocode, illustrating the implementation of IPAL-based mini-batch gradient descent on a dataset. It is worth noting that all demonstration experiments in this article were repeated at least three times, demonstrating the reliability and robustness of IPAL. The entire Optdigits dataset including training set (3823 images) and test set (1797 images) is used for the experimental demonstrations of IPAL.\u003c/p\u003e\n\u003cp\u003eHardware system for IPAL demonstration\u003c/p\u003e\n\u003cp\u003eTo demonstrate IPAL, a printed circuit board (PCB) system was built. The system mainly consists of DACs, input drivers, AIMC arrays, activation modules, ADCs, a sub-board for shortcut connection, and an auxiliary controller. The controller is located beneath the AIMC arrays but is not marked in the photo. In the PCB system, a fully analogue neuromorphic network is constructed by connecting AIMC arrays and activation modules alternately. The AIMC arrays are manufactured using standard CMOS technology and are further explained in Extended Data Fig. 1. The activation module is a sub-board that mainly contains a customized analogue chip for achieving multi-channel nonlinear amplification. The DAC used is the DAC7678 produced by TI, which has 8 channels in a single chip. To convert the 8\u0026times;8 handwritten digits into analogue signals, 8 DACs were used in parallel to provide 64-channel input signals to the first-layer AIMC arrays. An additional DAC was used to provide a constant analogue input, which is connected to the AIMC cells representing the biases in all layers. The ADC used is the ADS131M08 produced by TI, which is used to observe the amplitude of output signals of AUs. Multiple ADCs are used to work in parallel. It should be noted that ADCs are not required to observe hidden nodes during the inference process, as our hardware-based neuromorphic network is an end-to-end analogue system, and the forward propagation process is implemented in one shot. The current perturbation signal is generated by a DAC and an operational amplifier circuit, and is subsequently controlled by the multiplexer (MUX) to add/subtract current into/from the specific node according to Kirchhoff\u0026apos;s current law. Additionally, the system controller is the STM32F407, which performs auxiliary functions to control ADCs, DACs, MUXs, activation modules, as well as the read/write operation of the AIMC arrays.\u003c/p\u003e\n\u003cp\u003eAnalogue in-memory computing array chip\u003c/p\u003e\n\u003cp\u003eThe AIMC array chip is designed and manufactured using 180 nm CMOS technology. It integrates 34\u0026times;32 AIMC cells, with each AIMC cell containing 8 SRAM cells that store 8-bit weights for analogue multiplication. By sharing the same analogue input in the input column and using Kirchhoff\u0026apos;s law to sum the currents to the output row (see Extended Data Fig. 1a), the chip can perform analogue vector-by-matrix multiplication (VMM) in parallel, supporting 34-dimensional analogue input channels and 32-dimensional analogue output channels. The original experimental results of the VMM test are illustrated in Extended Data Fig. 1b, without any correction or calibration. Despite the computing errors due to the non-ideal properties of analogue hardware, IPAL can still train the neuromorphic network to achieve high accuracy performance equivalent to or better than that of a BP-trained digital system (Extended Data Fig. 3), demonstrating its effectiveness and adaptability of IPAL.\u003c/p\u003e\n\u003cp\u003eAnalogue activation module\u003c/p\u003e\n\u003cp\u003eThe activation module is a sub-PCB that transfers signals from the upstream AIMC array to the downstream AIMC array or the output nodes. The core component of the activation module is a customized analogue chip designed and manufactured using 180 nm CMOS technology. This analogue chip contains 16 activation units, functioning as reconfigurable nonlinear amplification in the analogue neuromorphic network (Extended Data Fig. 1c). As shown in\u0026nbsp;Extended Data Fig. 1d, each AU receives a differential pair of current signals, which are processed by a subtractor circuit and subsequently by a non-linear amplification circuit. The nonlinearity in the circuit stems from the transfer characteristic of the diodes. Moreover, by turning on/off the switches in the circuit, the AU can be reconfigured to exhibit different nonlinear behaviours (\u003cem\u003ee.g.\u003c/em\u003e, like a Sigmoid or ReLU function). Additionally, the chip includes an integrated MUX that allows for the introduction of positive/negative current perturbation into the positive/negative input channel of AU.\u003c/p\u003e\n\u003cp\u003eTraining an analogue neuromorphic network with shortcut connection\u003c/p\u003e\n\u003cp\u003eIn the experiment (Fig. 2f), inspired by the structure of ResNet, we added a shortcut connection to our analogue neuromorphic network. To implement this, we utilized two additional AIMC arrays representing the shortcut connection skipping the hidden layer. The shortcut connection shares the same input with that of fully connected layer 1 (FC1), and its output is added to the output of FC2 before being fed into the subsequent AUs. The dimensions of FC1, FC2, and the shortcut connection are 65\u0026times;32, 33\u0026times;10, and 65\u0026times;10, respectively. Since we used a differential pair of AIMC cells to realize positive and negative weights, we employed 65\u0026times;64 AIMC cells for FC1, 33\u0026times;20 AIMC cells for FC2, and 65\u0026times;20 AIMC cells for the shortcut connection. All weight connections were updated during the training process. It is important to note that the same perturbation signal was used to train both FC2 and the shortcut connection. We successfully trained the analogue neuromorphic network using IPAL, achieving high accuracy performance on both the training and test sets. This result highlights the universality of IPAL.\u003c/p\u003e\n\u003cp\u003eTraining analogue neuromorphic networks with unknown internal variations\u003c/p\u003e\n\u003cp\u003eIPAL has the capability to adapt the intrinsic physical characteristics of analogue hardware, regardless of its mathematical models. We demonstrated this advantage of hardware-fault-tolerance by utilizing IPAL to train neuromorphic networks, without any prior knowledge of the behaviours of AUs (as shown in Fig. 3 and Supplementary Information Section 3.2). In these experiments, the analogue neuromorphic network was initialized by individually setting each AU into a random variant, where different variants respond to input signals with different behaviours. It is important to note that the types of AU remain unknown throughout the whole training process, thus demonstrating that prior knowledge of the AUs is not required for IPAL. Furthermore, our additional experiments revealed that IPAL can also adapt to other non-ideal factors in hardware, such as mismatch effects, voltage offsets, varying component parameters, and parasitic effects.\u003c/p\u003e\n\u003cp\u003eSelf-restoring neuromorphic network experiments\u003c/p\u003e\n\u003cp\u003eThe analogue neuromorphic network hardware, once manufactured, becomes a dynamic system where its components may experience degradation, impairment, or even failure. Specifically, for neuromorphic networks based on emerging non-volatile memory, the lifespan or endurance of the electrical synapse is inherently limited. Using IPAL to adaptively train the dynamic system is a potential solution to restore the functionality of the analogue neuromorphic networks.\u003c/p\u003e\n\u003cp\u003eIn our experimental demonstration, we show that even if analogue neuromorphic networks have undergone some hardware impairments, we can restore their functionality through a re-training process. During the experimental demonstrations, a failed AIMC cell does not output a signal, which is realized with the AIMC cell whose weight always sticks to zero. A failed AU generates a constant output amplitude at the neutral point and does not respond to any input, which is realized by turning off the switch connecting the input of the AU. Note that the failed AUs are hidden layer neurons. In the experiments shown in Fig. 4 and Supplementary Information Section 3.3, we first trained an intact analogue neuromorphic network for the first 15 epochs and then randomly disabled some AIMC cells, AUs, or both. These components remained failed during the subsequent training process. When we employed IPAL to train the defective analogue neuromorphic networks after the 16\u003csup\u003eth\u003c/sup\u003e epoch, the failed components did not effectively propagate signals, including the perturbation signals. Hence, despite the changed internal structure, IPAL still adaptively provided the actual gradients for effectively training the impaired analogue neuromorphic networks, thereby enhancing the robustness of the neuromorphic hardware systems.\u003c/p\u003e\n\u003cp\u003eCompensation-healing neuromorphic networks experiments\u003c/p\u003e\n\u003cp\u003eInspired by the compensation concept in the biological nervous system, we propose a compensation-healing scheme to enhance the performance of analogue neuromorphic networks when the number of surviving components is insufficient to achieve high accuracy. The compensation-healing scheme introduces additional hardware into the impaired neuromorphic network to restore and even enhance its functionality. Due to space limitations, we only show the evolution of recognition accuracy in the main text, and more results for this experiment can be found in Extended Data Fig. 8. In our experiments, we trained the neuromorphic network with 16 hidden neurons within the first 15 epochs. At the 16\u003csup\u003eth\u0026nbsp;\u003c/sup\u003eepoch, 60% of the AIMC cells and AUs failed to work. We then added a bypass neuromorphic network with 16 hidden neurons to compensate for the impaired neuromorphic network. The input of the compensation network was connected to the input of the impaired network, sharing the same input signal. The output current of the compensation network was added to the output current of the impaired network using Kirchhoff\u0026apos;s current law. Subsequently, we used IPAL to train the rebuilt analogue neuromorphic network with the new structure, achieving improved accuracy performance compared to the original system.\u003c/p\u003e\n\u003cp\u003eTo compare the self-restoring scheme with the compensation-healing scheme, we conducted an additional experiment, as shown in Extended Data Fig. 9. This experiment consists of two stages. The first stage (0-66 epochs) of the experiment is similar to the one shown in Fig. 4f, showing that the recognition accuracy increases but does not surpass the accuracy before the hardware impairment. In the second stage (67-117 epochs), we introduce a compensatory neuromorphic network into the impaired one and continuously train the entire neuromorphic network with the new structure, ultimately achieving an enhancement in accuracy.\u003c/p\u003e\n\u003cp\u003eFabrication and integration of 1T1R memristor chips\u003c/p\u003e\n\u003cp\u003eTo produce our 1T1R chips, the CMOS circuits were fabricated by a commercial semiconductor manufacturer, and the memristors were fabricated in our university lab. We integrated the memristors with the top vias on CMOS chips. We deposited Ta/Au/Pd as the bottom electrodes, HfO\u003csub\u003e2\u003c/sub\u003e as the switching layer, and Ta/Pd/Au as the top electrodes. The Au and Pd metals were deposited by electron beam evaporation, the Ta metal was deposited by sputtering, and the HfO\u003csub\u003e2\u003c/sub\u003e was obtained through atomic layer deposition. The top and bottom electrodes were patterned using the photolithography and liftoff processes, where negative photoresist (NR9-1500PY) was used. Patterning of the switching layer was carried out through photolithography and reactive ion etching (RIE). Extended Data Fig. 1e and f shows the architecture of the 1T1R chip, as well as the results of parallel analogue VMM test.\u003c/p\u003e\n\u003cp\u003eExperimental demonstration using memristive devices\u003c/p\u003e\n\u003cp\u003eAs an emerging AIMC device, memristors suffer from yield issues during fabrication and stochastic degradation during operation. These problems make some of the memristors fail to switch, impacting the normal functionality of memristor-based neuromorphic networks. IPAL automatically adapts to diverse types of nonidealities that occur in memristors, such as short or open devices, non-linear I-V characteristics, and wire resistance effects. Thus, IPAL can provide the correct gradients in the physical system to update the remaining memristors and unlock the full potential of hardware-defective neuromorphic networks. In the experiments shown in Fig. 5, we first trained memristor-based neuromorphic networks. We then randomly damaged some of the memristors by using excessive voltage, creating memristor crossbar arrays with different degrees of hardware degradation. Subsequently, we used IPAL to re-train the memristor-based neuromorphic networks and realized high recognition accuracy. In sharp contrast, without using IPAL, the accuracy is strongly affected by the defect rate of memristors. In these demonstrations, we also used the full test set in the Optdigits dataset to evaluate the performance of the memristor-based neuromorphic networks.\u003c/p\u003e"},{"header":"Declarations","content":"\u003cp\u003eAcknowledgments\u003c/p\u003e\n\u003cp\u003eThis work was supported in part by the National\u0026nbsp;Key R\u0026amp;D Program of China under Grant 2023YFF1203600, the\u0026nbsp;National Natural Science Foundation of China\u0026nbsp;(62122036,\u0026nbsp;62034004,\u0026nbsp;61921005,\u0026nbsp;62305155,\u0026nbsp;12074176,\u0026nbsp;12322407), the\u0026nbsp;Strategic Priority Research Program of the Chinese Academy of Sciences (XDB44000000), the\u0026nbsp;Leading-edge Technology Program of Jiangsu Natural Science Foundation (BK20232004), the\u0026nbsp;China Postdoctoral Science Foundation\u0026nbsp;(2023M731582,\u0026nbsp;BX20230153), and the\u0026nbsp;Jiangsu Funding Program for Excellent Postdoctoral Talent (2023ZB079). F.M.\u0026nbsp;would like to acknowledge support from the AIQ Foundation. C.W. would like to acknowledge support from the Jiangsu Funding Program for Excellent Postdoctoral Talent (2023ZB079). The microfabrication center of the National Laboratory of Solid State Microstructures (NLSSM), the\u0026nbsp;Innovation Program for Quantum Science and Technology\u0026nbsp;and the\u0026nbsp;e-Science Center of Collaborative Innovation Center of Advanced Microstructures\u0026nbsp;are\u0026nbsp;acknowledged for their technique support.\u003c/p\u003e\n\u003cp\u003eAuthor contributions\u003c/p\u003e\n\u003cp\u003eC.W. and Y.Z. equally contributed to this work. C.W., Y.Z.,\u0026nbsp;F.M., and S.J.L. conceived the idea and designed the experiments. F.M. and S.J.L. supervised the whole project. Y.Z. and C.W.\u0026nbsp;designed the PCB systems and\u0026nbsp;conducted the experiments. C.W. and Y.Z. analyzed experimental data. C.W. and X.J.Y. designed the\u0026nbsp;AIMC and AU\u0026nbsp;chips.\u0026nbsp;C.W., W.W., Z.Z.Y. fabricated the memristor chips.\u0026nbsp;Z.Z.Y., Y.S., S.D.,\u0026nbsp;D.K., X.W.,\u0026nbsp;and\u0026nbsp;J.S. helped in the circuit design, assembly, and measurement.\u0026nbsp;P.W.,\u0026nbsp;Y.Y., C.P., and B.C. discussed the results. C.W.,\u0026nbsp;Y.Z.,\u0026nbsp;S.J.L. and F.M. co-wrote the manuscript.\u003c/p\u003e\n\u003cp\u003eCompeting interests\u003c/p\u003e\n\u003cp\u003eAuthors declare that they have no competing interests.\u003c/p\u003e\n\u003cp\u003eData availability\u003c/p\u003e\n\u003cp\u003eAll data\u0026nbsp;and code are available\u0026nbsp;within the article\u0026nbsp;and the\u0026nbsp;Supplementary\u0026nbsp;Information, and from the corresponding authors upon reasonable request.\u003c/p\u003e"},{"header":" References","content":"\u003col\u003e\n \u003cli\u003eSchuman, C.D. et al. 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However, the robust deployment of these analogue neuromorphic systems is hindered by stochastic variations of analogue devices and dynamic changes in hardware structure\u003csup\u003e8, 9\u003c/sup\u003e. Here, we demonstrate an approach called intrinsic physics-adaptive learning (IPAL) that can effectively train analogue neuromorphic networks based on non-ideal hardware. This approach allows us to obtain gradients of the practical physical system by using two-step physical operations (\u003cem\u003ei.e.\u003c/em\u003e, applying stimuli to the physical system and observing its resulting response), eliminating the need for mathematical modelling of the physical system. Experiments validate the effectiveness of IPAL on a neuromorphic hardware network comprised of analogue in-memory computing arrays and analogue activation units. Furthermore, we demonstrate that the approach can effectively train analogue neuromorphic networks with unpredictable hardware variations or impairments, and restore their recognition accuracy even when 60% of electrical synapses and neurons fail to work. We also show that IPAL can be used for analogue neuromorphic networks based on emerging memristive devices. Our work paves the way for developing analogue neuromorphic computing hardware with superior fault-tolerant performance.\u003c/p\u003e","manuscriptTitle":"Robust analogue neuromorphic hardware networks using intrinsic physics-adaptive learning","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2024-07-11 10:02:51","doi":"10.21203/rs.3.rs-4651980/v1","editorialEvents":[{"type":"communityComments","content":0}],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true}}],"origin":"","ownerIdentity":"3318340f-2299-4c14-a942-2f865d00fcf6","owner":[],"postedDate":"July 11th, 2024","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"posted","subjectAreas":[{"id":34352060,"name":"Physical sciences/Physics/Electronics, photonics and device physics"},{"id":34352061,"name":"Physical sciences/Materials science"}],"tags":[],"updatedAt":"2026-02-26T14:25:07+00:00","versionOfRecord":[],"versionCreatedAt":"2024-07-11 10:02:51","video":"","vorDoi":"","vorDoiUrl":"","workflowStages":[]},"version":"v1","identity":"rs-4651980","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-4651980","identity":"rs-4651980","version":["v1"]},"buildId":"qtupq5eGEP_6zYnWcrvyt","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}