Prospects of Analog In-Memory Computing using Ferroelectric Tunnel Junctions

Abstract Artificial intelligence (AI) is set to disrupt the way businesses and civil society operate, but the large energy usage for training and running AI compute models remains a pressing concern in terms of its sustainability. Analog in-memory computing (AIMC) hardware based on memristor devices is a promising route to significant energy-savings. Among the various memristor technologies, Ferroelectric Tunnel Junctions (FTJs) hold considerable promise for large scale AIMC. Their performance prospects remain to be fully assessed; therefore, we here evaluate the viability of FTJ memristors as compute units for AIMC. Based on the behavior of experimental TiN/HfZrO4/W FTJs we define three operating modes which we apply to standard AI tests and two real-world use cases: Image segmentation (YOLOv8) and natural language processing (BERT). We find that the inherent mechanism behind the analog state in FTJs limits the usable dynamic range and thus enforces strict control of noise. The best overall performance is obtained by constricting the dynamic range further and using ultrashort programming pulses (0.5 ns); on BERT matching the performance of digital hardware. We also present a more accessible approach, combining three FTJs, two of which are operated as binary memories, to achieve similar performance while also relaxing the requirements on data converter precision and level of noise. All in all, we here outline benefits and intrinsic challenges of FTJ-based AIMC systems, providing a blueprint for future experimental implementations.