Floating-point matrix multiplication optimized through the integration of hybrid multiplier techniques

Floating-point matrix multiplication optimized through the integration of hybrid multiplier techniques | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Floating-point matrix multiplication optimized through the integration of hybrid multiplier techniques Y. R.Annie Bessant, A. Chrispin Jiji, J. Grace Jency Gnanammal This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-7629322/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract In order to support high power computing applications, we aimed to design a novel framework for floating point matrix multiplication. In the proposal of matrix multiplication processing elements (PEs), multipliers such as Strassen, Karatsuba and Vedic are utilized to maximize the architecture performance. The Urdhava Tiryabhyam sutra from the Vedic multiplier is one of them that decreases partial products in multiplication while simultaneously speeding up the process. This paper proposes the design of Strassen matrix multiplication algorithm with the combined features of Urdhava Tiryabhyam and Karatsuba multiplier. The Karatsuba algorithm is inefficient at lower orders of multiplication, but it works well at higher orders. Thus, at a lower level, the Urdhava Tiryabhyam Multiplier is applied. A floating-point matrix multiplication architecture was developed using Verilog HDL and implemented on the Virtex-5 FPGA – XC5VSX95T. The design was developed, verified through simulation, and implemented using Xilinx ISE 13.5. Multiplier Processing Element Floating point sub matrices performance Full Text Additional Declarations No competing interests reported. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-7629322","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":542616601,"identity":"bfef72b5-5dfd-486c-8782-10ba26dd1a67","order_by":0,"name":"Y. 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