Parasitic RC Estimation and Defect Prediction for Embedded Memory using Machine Learning

Parasitic RC Estimation and Defect Prediction for Embedded Memory using Machine Learning | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Parasitic RC Estimation and Defect Prediction for Embedded Memory using Machine Learning Venkatesham Maddela, Sanjeet Kumar Sinha, Muddapu Parvathi, Sweta Chander This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-3843032/v1 This work is licensed under a CC BY 4.0 License Status: Published Journal Publication published 12 Jun, 2025 Read the published version in Analog Integrated Circuits and Signal Processing → Version 1 posted 11 You are reading this latest preprint version Abstract In today's rapidly scaling-down technological environment, identifying the best-fit algorithms for evaluating complicated circuits such as SRAMs is a difficult issue. Many fault models have developed, however their flexibility of use is limited by the restrictions and constraints of the provided test environment. The majority of existing fault models have been studied in terms of well-known March algorithms, which simply provide fault detection information. Scaled-down technologies have an impact on parasitic effects as well, resulting in an extra source of defective behavior and making current test algorithms vulnerable to them. Recent work that uses method of parasitic extraction for fault detection have addressed the problem of limitation due to scale down technologies. However, as the circuit complexity increases the estimation of RC would be tedious. Hence in this paper machine learning based parasitic RC extraction is proposed. Also, as an extension to that, proposed ML based fault detection using extracted parasitic RCs as dataset. The proposed machine learning based fault prediction uses extracted parasitic RCs as dataset. The parasitic RC values are extracted for each fault model using technologies of 120nm down to deep submicron 7nm. Regression algorithm is used for modeling the machine for extraction of RCs and observed that 88% of prediction accuracy. Decision tree modeling is used for fault detection and observed 91.7% of accuracy in prediction of fault. 3.1 Effect of open defects in 6T SRAM Cell In this are article we have consider the node to node open/short faults. In Fig 2. We have imposed all possible open defects and then we have analyzed the memory cell for all possible open defects. There are totally 25 open defects are possible as shown in the fig 2. The simulation results and different types faults occurs for all open defects are shown in table 1 Fig2: Fault model for Open Defects in 6T-SRAM Cell Table 1. 6T SRAM Cell open defect list for different technologies Parasitic Extraction Method Open/Short Faults Linear Regression Decision Tree Machine Learning Full Text Additional Declarations No competing interests reported. Cite Share Download PDF Status: Published Journal Publication published 12 Jun, 2025 Read the published version in Analog Integrated Circuits and Signal Processing → Version 1 posted Editorial decision: Revision requested 23 Mar, 2025 Reviews received at journal 21 Mar, 2025 Reviews received at journal 23 Feb, 2025 Reviewers agreed at journal 17 Feb, 2025 Reviewers agreed at journal 17 Feb, 2025 Reviewers agreed at journal 07 Feb, 2025 Reviewers agreed at journal 09 Jan, 2024 Reviewers invited by journal 08 Jan, 2024 Submission checks completed at journal 08 Jan, 2024 Editor assigned by journal 08 Jan, 2024 First submitted to journal 07 Jan, 2024 You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. 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Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-3843032","acceptedTermsAndConditions":true,"allowDirectSubmit":false,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":266053470,"identity":"78fb94b5-f6bb-4b9e-aaff-ce9ba9adc346","order_by":0,"name":"Venkatesham Maddela","email":"","orcid":"","institution":"Lovely Professional University","correspondingAuthor":false,"prefix":"","firstName":"Venkatesham","middleName":"","lastName":"Maddela","suffix":""},{"id":266053471,"identity":"73b6a476-fe4e-4fe6-a109-63275ac18e31","order_by":1,"name":"Sanjeet Kumar Sinha","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAABAklEQVRIiWNgGAWjYJACAzBmZmBjYKgAMpmZG4jRYgDVcgakhZGwFgawFgagFsY2EIeAFvn2swcKPlT8MZZv5z324Oe82mj+dqCWHxXbcBt/Ji/BcMYZAzODw3zphr3bjufOOMzYwNhz5jYef+QYGPO2GdgYMPOYSfBuO5bbANTCzNiGW4t8/xsD47//DGzkm3nMJP/OOZY7n5AWhhtAWxgbDMwYDvOYSfM21ORuIKTF4MYbA8OeY8bGBiAtMscO5G4EajmIzy/y/TlmBj9q5Azn958xk3xTU5c77/zhgw9+VOBxGDA6DJA4h8HkAXzqgYD5ARKnjoDiUTAKRsEoGIkAANE6VukgWXNUAAAAAElFTkSuQmCC","orcid":"","institution":"Lovely Professional University","correspondingAuthor":true,"prefix":"","firstName":"Sanjeet","middleName":"Kumar","lastName":"Sinha","suffix":""},{"id":266053472,"identity":"bec21382-a19c-4328-85ee-e2b8b4d756ab","order_by":2,"name":"Muddapu Parvathi","email":"","orcid":"","institution":"BVRIT HYDERABAD College of Engineering for Women","correspondingAuthor":false,"prefix":"","firstName":"Muddapu","middleName":"","lastName":"Parvathi","suffix":""},{"id":266053473,"identity":"05f7e99b-3ffb-4032-a9fe-e47c0123f7ab","order_by":3,"name":"Sweta Chander","email":"","orcid":"","institution":"Lovely Professional University","correspondingAuthor":false,"prefix":"","firstName":"Sweta","middleName":"","lastName":"Chander","suffix":""}],"badges":[],"createdAt":"2024-01-07 16:44:16","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-3843032/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-3843032/v1","draftVersion":[],"editorialEvents":[{"content":"https://doi.org/10.1007/s10470-025-02438-5","type":"published","date":"2025-06-12T15:57:26+00:00"}],"editorialNote":"","failedWorkflow":false,"files":[{"id":84726503,"identity":"5420ba5f-0e7f-4c2f-bab7-ca1fde25f68c","added_by":"auto","created_at":"2025-06-16 16:06:04","extension":"pdf","order_by":1,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":1397512,"visible":true,"origin":"","legend":"","description":"","filename":"MLPaper.pdf","url":"https://assets-eu.researchsquare.com/files/rs-3843032/v1_covered_08700fda-c0a2-4845-adf7-5a388abd17db.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"Parasitic RC Estimation and Defect Prediction for Embedded Memory using Machine Learning","fulltext":[],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":false,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":false,"highlight":"","institution":"","isAcceptedByJournal":true,"isAuthorSuppliedPdf":true,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":true,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"analog-integrated-circuits-and-signal-processing","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":false,"externalIdentity":"alog","sideBox":"Learn more about [Analog Integrated Circuits and Signal Processing](http://link.springer.com/journal/10470)","snPcode":"10470","submissionUrl":"https://submission.nature.com/new-submission/10470/3","title":"Analog Integrated Circuits and Signal Processing","twitterHandle":"","acdcEnabled":true,"dfaEnabled":true,"editorialSystem":"em","reportingPortfolio":"Springer Hybrid","inReviewEnabled":true,"inReviewRevisionsEnabled":false},"keywords":"Parasitic Extraction Method, Open/Short Faults, Linear Regression, Decision Tree, Machine Learning ","lastPublishedDoi":"10.21203/rs.3.rs-3843032/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-3843032/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"In today's rapidly scaling-down technological environment, identifying the best-fit algorithms for evaluating complicated circuits such as SRAMs is a difficult issue. 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