A 0.064 mm2 16-Channels In-Pixel Neural Front-End With Improved System Common-Mode Rejection Exploiting a Current-Mode Summing Approach

In this work, we introduce the design a 16-channel in-pixel neural analog front-end which employs a current-based summing approach to establish a common-mode feedback loop. The primary aim of this novel structure is to enhance both the system common-mode rejection ratio (SCMRR) and the common-mode interference (CMI) range. Compared to more conventional designs, the hereby proposed front-end utilizes DC-coupled inverter-based main amplifiers, which significantly reduce the occupied on-chip area. Additionally, the current-based implementation of the CMFB loop obviates the need for voltage buffers, replacing them with simple common-gate transistors and in turn decreasing both area occupancy and power consumption. The proposed architecture is further examined from an analytical standpoint, providing a comprehensive evaluation through design equations of its performance in terms of gain, common-mode rejection and noise power. A 50μm×65μm compact layout of the pixel amplifiers that make up the recording channels of the front-end was designd in a 180 nm CMOS process. Simulations conducted in Cadence Virtuoso reveal an SCMRR of 80.5 dB and a PSRR of 72.58 dB, with a differential gain of 44 dB and a bandwidth that fully encompasses the frequency range of the bio-signals that can be theoretically captured by the neural probe. The noise integrated in the range between 1 Hz and 7.5 kHz results in an IRN of 4.04 μVrms. Power consumption is also tested, with a measured value of 3.77 μW per channel, corresponding to an overall consumpution of about 60 μW. To test its robustness with respect to PVT and mismatch variations, the front-end is evaluated by means of extensive parametric simulations and Monte Carlo simulations, revealing favorable results.