Interface Engineering for Substantial Performance Enhancement in Epitaxial All Perovskite Oxide Capacitor

Abstract Capacitors based on ABO3-type perovskite oxides show considerable promise for overcoming the limitations of nanoscale integration for dynamic random access memory (DRAM) devices. Among thermodynamically stable perovskite oxides, titanates (ATiO3) exhibit high dielectric permittivity in metal–insulator–metal (MIM) configurations. However, their ultimate properties remain under scrutiny for mitigating the large leakage current caused by their narrow bandgap (3 eV). Herein, substantially enhanced dielectric properties of an epitaxial SrRuO3/Ba0.5Sr0.5TiO3/SrRuO3 MIM capacitor with a thin dielectric layer (10 nm) are reported. The dielectric/electrode heterointerface was engineered to realize a capacitor with low leakage current and high dielectric permittivity. A pit-free and stoichiometric SrRuO3 bottom electrode with atomically smooth surface was exploited for suppressing defect formation at the heterointerface. The critical roles of oxygen vacancies and substituted transition-metal atoms in determining the leakage current were accessed and a strategy for reducing the leakage current via interface engineering was established. Consequently, a dielectric permittivity of 861 and leakage current density of 5.15 × 10− 6 A/cm2 at 1 V were obtained with the thinnest dielectric layer ever reported. Our work paves the way for the development of perovskite-oxide-based capacitors in next-generation DRAM memories.