A Compact 55–66 GHz Single-Chip FMCW Transceiver Featuring 12-dBm Psat and >11-GHz Tuning Range in 65-nm SOI CMOS

A Compact 55–66 GHz Single-Chip FMCW Transceiver Featuring 12-dBm Psat and >11-GHz Tuning Range in 65-nm SOI CMOS | Authorea try { document.documentElement.classList.add('js'); } catch (e) { } 11-GHz Tuning Range in 65-nm SOI CMOS | Authorea"/> 11-GHz Tuning Range in 65-nm SOI CMOS"> var _gaq = _gaq || []; _gaq.push(['_setAccount', 'G-8VDV14Y67G']); _gaq.push(['_trackPageview']); (function() { var ga = document.createElement('script'); ga.type = 'text/javascript'; ga.async = true; ga.src = ('https:' == document.location.protocol ? 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Data may be preliminary. 23 March 2026 V1 Latest version Share on A Compact 55–66 GHz Single-Chip FMCW Transceiver Featuring 12-dBm Psat and >11-GHz Tuning Range in 65-nm SOI CMOS Authors : Yulong Xu 0009-0005-0849-5911 , Zongming Duan , Jin Xu , Yingsong Li , and Bing Wu [email protected] Authors Info & Affiliations https://doi.org/10.22541/au.177429277.74778339/v1 140 views 125 downloads Contents Abstract Supplementary Material Information & Authors Metrics & Citations View Options References Figures Tables Media Share Abstract This paper presents a fully-integrated frequency-modulated continuous-wave (FMCW) transceiver chip operating from 55 to 66 GHz, fabricated in a 65 nm silicon-on-insulator (SOI) CMOS process. The chip incorporates a wide-tuning-range voltage-controlled oscillator (VCO) with four digitally selectable states, a driver amplifier, a power amplifier, a low-noise amplifier, and passive mixers, providing a compact solution for high-resolution millimeter-wave radar and short-range communication systems. An innovative hybrid digital-analog VCO tuning architecture, combined with co-optimized transmit/receive front-end design, enables robust noise and linearity performance within a small core area. Measurement results demonstrate a transmitter saturated output power of 12 dBm and an output return loss better than 8 dB across the band. The receiver achieves 10 dB of gain, a 9.8 dB noise figure, and an input 1‑dB compression point of ‑18 dBm. The integrated VCO exhibits a phase noise better than –87.71 dBc/Hz at 1 MHz offset. A Compact 55–66 GHz Single-Chip FMCW Transceiver Featuring 12-dBm Psat and >11-GHz Tuning Range in 65-nm SOI CMOS Yulong Xu, Zongming Duan, Jin Xu, Yingsong Li, and Bing Wu Electronic Information Engineering Institute, Anhui University, Hefei 230601, China Email: [email protected] This paper presents a fully-integrated frequency-modulated continuous-wave (FMCW) transceiver chip operating from 55 to 66 GHz, fabricated in a 65 nm silicon-on-insulator (SOI) CMOS process. The chip incorporates a wide-tuning-range voltage-controlled oscillator (VCO) with four digitally selectable states, a driver amplifier, a power amplifier, a low-noise amplifier, and passive mixers, providing a compact solution for high-resolution millimeter-wave radar and short-range communication systems. An innovative hybrid digital-analog VCO tuning architecture, combined with co-optimized transmit/receive front-end design, enables robust noise and linearity performance within a small core area. Measurement results demonstrate a transmitter saturated output power of 12 dBm and an output return loss better than 8 dB across the band. The receiver achieves 10 dB of gain, a 9.8 dB noise figure, and an input 1‑dB compression point of ‑18 dBm. The integrated VCO exhibits a phase noise better than –87.71 dBc/Hz at 1 MHz offset. Introduction: With the rapid advancement of autonomous driving, intelligent sensing, and next-generation wireless communication technologies, the millimeter-wave frequency bands, particularly the unlicensed spectrum around 60 GHz, have garnered significant attention due to their abundant bandwidth resources [1-4]. Frequency-modulated continuous-wave (FMCW) technology, owing to its relatively simple architecture, low power consumption, and ease of achieving high range resolution, has become a mainstream solution for applications such as short-range radar detection, gesture recognition, and high-precision ranging [5-7]. However, designing a fully-integrated silicon-based FMCW transceiver chip poses multiple challenges, including: realizing a voltage-controlled oscillator (VCO) with wide tuning range and low phase noise; achieving a power amplifier (PA) with high output power at millimeter-wave frequencies; designing a receiver front-end with low noise figure and high linearity; and ensuring good isolation between the transmit and receive channels to suppress self-interference. Conventional discrete or modular implementations are often hindered by their large physical size and high cost, which impede meeting the stringent demands of modern radar systems for miniaturization and high integration. Thus, developing high-performance, low-cost, single-chip FMCW transceivers in advanced silicon technologies has become a key research objective. In response to the challenges outlined above, this work introduces an innovative system architecture and circuit design approach. We present a fully-integrated 55–66 GHz FMCW transceiver chip. Through the co-design and optimized integration of core building blocks—including the VCO, PA, LNA, and mixers—the prototype achieves a substantial reduction in both chip area and power consumption, without compromising RF performance. Fig.1 The system architecture of the transceiver Chip architecture: Fig.1 presents the system architecture of the proposed single-chip FMCW transceiver. Based on a direct-conversion topology to minimize complexity and power consumption, the design integrates all key RF front-end blocks. In the transmit path, the FMCW signal generated by an on-chip VCO is amplified by a driver stage and a subsequent two-stage PA before antenna radiation. The receive path begins with an LNA for initial amplification of the echo signal, followed by down-conversion in a passive double-balanced mixer. This mixer uses a coupled output from the TX VCO as the LO, translating the signal to baseband or a low IF for further processing by an IF amplifier. Support for an external LO mode is also included. VCO Design: The VCO employs a complementary cross-coupled structure to reduce power consumption and improve phase noise. The LC resonator is constructed using symmetric spiral inductors and MOS varactors. To extend the tuning range and reduce tuning sensitivity, a non-uniformly distributed switched capacitor array is designed. Fig.2 shows a simplified schematic of the VCO core circuit and its tuning unit. Through careful layout and metal stack optimization, parasitic capacitance is minimized, thereby achieving excellent tuning performance. Post-layout simulation indicates that each sub-band exhibits good tuning linearity across the 1.8 V tuning voltage range. To support wideband frequency sweeping, the VCO implements a hybrid digital-analog tuning mechanism. Two digital control bits (S1, S2) are used to sequentially select one of four coarse-tuning bands by activating corresponding switched capacitor arrays. Within each selected band, continuous fine-tuning is accomplished by varying the analog control voltage (VC) from 0 to 1.8 V across a varactor bank. This architecture facilitates seamless coverage of the full 58–62 GHz operational bandwidth while concurrently optimizing the VCO’s phase noise and tuning linearity. Fig.2 Schematic of the VCO core circuit and its tuning unit Power Amplifier Design: The power amplifier design is based on a three-stage common-source architecture to simultaneously optimize output power and efficiency. To address the challenge of low transistor gain at millimeter-wave frequencies, the driver amplifier employs a two-stage common-source cascade for gain enhancement. The matching network utilizes a transformer-coupled configuration, which concurrently achieves broadband impedance matching, DC biasing, and differential-to-single-ended conversion. Extensive electromagnetic co-simulation and optimization across the entire frequency band ensure stable output power and excellent port matching performance. Low Noise Amplifier Design: The low-noise amplifier employs a two-stage topology, carefully partitioned for noise and gain optimization. The first stage is a noise-optimized common-source amplifier dedicated to achieving the minimum possible noise figure (NF). Its input matching network is co-designed for simultaneous noise and power matching. Through iterative optimization on the Smith chart, an input impedance close to the optimum noise impedance is realized, while ensuring good power transfer. The second common-source stage provides additional gain and enhances reverse isolation. All inductors are fabricated using the top thick-metal layer to maximize their quality factor (Q), thereby minimizing insertion loss and preserving the overall noise performance. Mixer and Isolation Design: A passive double-balanced mixer is adopted in this design, offering high linearity and excellent local-oscillator-to-radio-frequency (LO-RF) isolation. To suppress leakage interference from the transmitter to the receiver chain, multiple isolation measures are implemented at the layout level, including physical spacing, ground shielding structures, and isolated power routing. Furthermore, by separately optimizing the output matching network of the transmitter power amplifier and the input matching network of the receiver low-noise amplifier, the transfer efficiency of the coupling path is further reduced, thereby significantly enhancing the overall isolation between the transmit and receive channels. Fig.3 The chip micrograph Measurement results: The chip was fabricated in a 65-nm SOI process. Fig.3 shows the chip micrograph, with a core area of 1.9 × 1.76 mm². The phase noise performance of the VCO is shown in Fig. 4. The measurement was performed after an on-chip divide-by-2 stage; thus, the plotted data corresponds to a carrier frequency of 9.93 GHz. The equivalent phase noise at the fundamental frequency of 59.58 GHz is -87.71 dBc/Hz at a 1 MHz offset, which is extrapolated from the divided-down measurement. This result meets the stringent phase noise specifications for FMCW system frequency sources. Fig.5 summarizes the measured performance of the transceiver chip. As shown in Fig.5(a), the transmitter output return loss is better than 8 dB across the entire 55–66 GHz band, indicating good output matching, while the receiver input return loss remains better than 10 dB throughout the band, as illustrated in Fig.5(b). Fig.5(c) presents the saturated output power of the transmitter chain, achieving a typical value of 12 dBm across the target frequency range. The receiver chain exhibits a gain of approximately 10 dB in Fig.5(d), with a typical noise figure of 9.8 dB in Fig.5(e). Linearity performance is characterized in Fig.5(f), where the receiver shows an input 1-dB compression point of -18 dBm. Additionally, the LO port return loss is better than 8 dB, as depicted in Fig. 5(g). Finally, the measured isolation between the transmitter and receiver ports is better than 50 dB across the band in Fig. 5(h), demonstrating the effectiveness of the implemented isolation techniques in suppressing self-interference. Table 1 compares the performance of this work with recently published V-band millimeter-wave transceiver or front-end chips. The presented design offers competitive advantages in terms of output power and tuning range, while providing a fully-integrated solution as a complete single-chip transceiver. Fig. 4 VCO phase noise measured after divide-by-2 (b) (d) (e) (f) (g) (h) Fig.5 The measured results. (a) TX return loss; (b)RX return loss; (c)TX Pout; (d)RX Gain; (e)RX NF; (f)RX IP1dB; (g)LO return loss; (h)TX-RX isolation Table 1. comparision of the Performance of transceiver chip process SiGe CMOS SiGe SOI Frequency(GHz) 58-64 56-66 62 55-66 TX Pout(dBm) 6.4 8.1 9 12 RX Gain(dB) 21 24 28 10 RX IP1dB(dBm) -24 -10 / -18 RX NF(dB) 8 10.5 / 9.8 Pdc(W) 0.52 0.062 0.072 0.216 Area(mm 2 ) 1.03 4.13 4.07 3.34 Conclusion: This paper presents the design and experimental validation of a fully-integrated 55–66 GHz CMOS FMCW transceiver chip. By incorporating a hybrid digital-analog VCO tuning architecture, along with optimized power amplifier and low-noise amplifier designs, together with an isolation-aware layout strategy, the proposed transceiver achieves a wide frequency tuning range, competitive output power, low receiver noise figure, and adequate TX-RX isolation. The chip is well-suited for millimeter-wave radar sensing and communication systems that demand compact form factors, low cost, and medium-range detection capabilities. Acknowledgments: This work was supported by Anhui Provincial Science and Technology Innovation Key Project under Grant K120336032  2021 The Authors. Electronics Letters published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and Technology This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited. Received: xx January 2026 Accepted: xx March 2026 doi: 10.1049/ell2.10001 References 1. C. Xu et al., “A packaged 54-to-69-GHz wideband 2T2R FMCW radar transceiver employing cascaded-PLL topology and PTAT-enhanced temperature compensation in 40-nm CMOS,” IEEE J. Solid-State Circuits, vol. 59, no. 10, pp. 3156–3171, Oct. 2024. 2. Y. Li, C. Gu, and J. Mao, “4-D gesture sensing using reconfigurable virtual array based on a 60-GHz FMCW MIMO radar sensor,” IEEE Trans. Microw. Theory Techn., vol. 70, no. 7, pp. 3652–3665, Jul. 2022. 3. K.-I. Oh, G.-H. Ko, G. Sub Kim, J.-G. Kim, and D. Baek, “A 54–64-GHz 4TXs-4RXs CMOS transceiver with 10-GHz bandwidth single chirp for FMCW radar applications,” IEEE Trans. Microw. Theory Techn., vol. 73, no. 3, pp. 1532–1544, Mar. 2025. 4. J. Chen et al., “A 56–65 GHz highly-integrated FMCW radar transceiver with 7.8 dB NF and 8 GHz chirp-bandwidth in 65-nm CMOS,” in Proc.IEEE Radio Freq. Integr. Circuits Symp. (RFIC), Washington, DC, USA,Jun. 2024, pp. 19–22. 5. E. Öztürk et al., “A 60-GHz SiGe BiCMOS monostatic transceiver for FMCW radar applications,” IEEE Trans. Microwave Theory Techn.,vol. 65, no. 12, pp. 5309–5323, Dec. 2017. 6. A. Kankuppe, S. Park, P. T. Renukaswamy, P. Wambacq, and J. Craninckx, “A wideband 62-mW 60-GHz FMCW radar in 28-nm CMOS,” IEEE Trans. Microwave Theory Techn., vol. 69, no. 6, pp. 2921–2935, Jun. 2021. 7. B. Sutbas, H. J. Ng, M. H. Eissa and G. Kahmen, ”A Low-Power V-Band Radar Transceiver Front-End Chip Using 1.5 V Supply in 130-nm SiGe BiCMOS,” in IEEE Transactions on Microwave Theory and Techniques, vol. 71, no. 11, pp. 4855-4868, Nov. 2023 Supplementary Material File (image1.emf) Download 45.61 KB File (image10.emf) Download 313.65 KB File (image11.emf) Download 264.65 KB File (image12.emf) Download 213.31 KB File (image2.emf) Download 209.70 KB File (image3.emf) Download 360.54 KB File (image5.emf) Download 363.61 KB File (image6.emf) Download 346.38 KB File (image7.emf) Download 378.79 KB File (image8.emf) Download 324.20 KB File (image9.emf) Download 378.06 KB Information & Authors Information Version history V1 Version 1 23 March 2026 Copyright This work is licensed under a Non Exclusive No Reuse License. Keywords circuits and systems millimetre wave integrated circuits millimetre wave power amplifiers millimetre wave receivers mmic amplifiers Authors Affiliations Yulong Xu 0009-0005-0849-5911 Anhui University View all articles by this author Zongming Duan Anhui University View all articles by this author Jin Xu Anhui University View all articles by this author Yingsong Li Anhui University View all articles by this author Bing Wu [email protected] Anhui University View all articles by this author Metrics & Citations Metrics Article Usage 140 views 125 downloads .FvxKWukQNSOunydq8rnd { width: 100px; } Citations Download citation Yulong Xu, Zongming Duan, Jin Xu, et al. A Compact 55–66 GHz Single-Chip FMCW Transceiver Featuring 12-dBm Psat and >11-GHz Tuning Range in 65-nm SOI CMOS. Authorea . 23 March 2026. DOI: https://doi.org/10.22541/au.177429277.74778339/v1 If you have the appropriate software installed, you can download article citation data to the citation manager of your choice. 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