Modeling and circuit design for three-terminal memristors

Modeling and circuit design for three-terminal memristors | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Modeling and circuit design for three-terminal memristors Xianyan Kuang, xianglan huan, hongbiao xiao This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-2867669/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract In this paper, a three-terminal memristor model is developed in order to improve the anti-interference performance of the memristor and address the issue that the resistance value of the conventional two-terminal memristor is readily impacted by voltage. In order to simulate and validate the function of the three-terminal memristor, the logic circuit and multiplication circuit are developed using this model in this work using the cadence ic617 program. According to the findings, the three-terminal memristor multiplication circuit uses less energy than the typical conventional multiplier circuit, consuming only 0.335 uW. The memristor offers the benefits of low power consumption, compact size, and great integratability as a nanoscale device. The use of three-terminal memristors can dramatically reduce the number of chip components and improve chip integration when Moore's law approaches a limit. memristor multiplication circuit logic circuit cadence ic617 simulation Full Text Additional Declarations No competing interests reported. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-2867669","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":198391095,"identity":"f466bff9-4387-4eb8-b22e-e7f06112779d","order_by":0,"name":"Xianyan Kuang","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAABGElEQVRIiWNgGAWjYBACCRTqAw9UmAerYixaGGeAlLIRpwUCmMEqCWmRnJH87OHXNgt5c4nkZ49tZA4nzp/fwPjgbRuDvDkOLdISaebGMmckDHfOADJyeNISNxxjYDac28ZguLMBuxY5iQQzaYkKCcYNN4CMHB6bxA1sDGzSvG0MCQYHcGlJ/yYtYSBhv+EGkGHBI5E4v42B/Tc+LdISOWaSHyokEjfcyDGTZgDa0nCMgY0ZnxbJnjdl0gxnJJI3nHlTJtnDk2a84Vhis+SccxKGG3BokTievk3yZ1ud7QYgQ+Jnz2HZ+c2HD354U2Yjj8sWEIBEh0ACMC57QCzGBga0CMMAjD9AJD/I0B94FY6CUTAKRsEIBQD3AlT63ysggQAAAABJRU5ErkJggg==","orcid":"","institution":"Jiangxi University of Science and Technology","correspondingAuthor":true,"submittingAuthor":false,"prefix":"","firstName":"Xianyan","middleName":"","lastName":"Kuang","suffix":""},{"id":198391096,"identity":"e4bfc9a2-181d-4941-93ed-6f461858b6cc","order_by":1,"name":"xianglan huan","email":"","orcid":"","institution":"Jiangxi University of Science and Technology","correspondingAuthor":false,"submittingAuthor":false,"prefix":"","firstName":"xianglan","middleName":"","lastName":"huan","suffix":""},{"id":198391097,"identity":"fe5d5da0-2cb0-4d6c-b9d2-5b9120cf69bc","order_by":2,"name":"hongbiao xiao","email":"","orcid":"","institution":"Jiangxi University of Science and Technology","correspondingAuthor":false,"submittingAuthor":false,"prefix":"","firstName":"hongbiao","middleName":"","lastName":"xiao","suffix":""}],"badges":[],"createdAt":"2023-04-27 08:59:35","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-2867669/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-2867669/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":47909020,"identity":"db239ba8-e633-4c52-93fa-3b0c1d502c40","added_by":"auto","created_at":"2023-12-09 15:37:41","extension":"pdf","order_by":1,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":407915,"visible":true,"origin":"","legend":"","description":"","filename":"Modelingandcircuitdesignforthreeterminalmemristors.pdf","url":"https://assets-eu.researchsquare.com/files/rs-2867669/v1_covered_db5abc50-29db-4d80-869a-9a739d9f4e76.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"Modeling and circuit design for three-terminal memristors","fulltext":[],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":false,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":true,"highlight":"","institution":"","isAcceptedByJournal":false,"isAuthorSuppliedPdf":true,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":true,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"memristor, multiplication circuit, logic circuit, cadence ic617 simulation","lastPublishedDoi":"10.21203/rs.3.rs-2867669/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-2867669/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eIn this paper, a three-terminal memristor model is developed in order to improve the anti-interference performance of the memristor and address the issue that the resistance value of the conventional two-terminal memristor is readily impacted by voltage. In order to simulate and validate the function of the three-terminal memristor, the logic circuit and multiplication circuit are developed using this model in this work using the cadence ic617 program. According to the findings, the three-terminal memristor multiplication circuit uses less energy than the typical conventional multiplier circuit, consuming only 0.335 uW. The memristor offers the benefits of low power consumption, compact size, and great integratability as a nanoscale device. The use of three-terminal memristors can dramatically reduce the number of chip components and improve chip integration when Moore's law approaches a limit.\u003c/p\u003e","manuscriptTitle":"Modeling and circuit design for three-terminal memristors","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2023-05-11 16:54:30","doi":"10.21203/rs.3.rs-2867669/v1","editorialEvents":[{"type":"communityComments","content":0}],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true}}],"origin":"","ownerIdentity":"66026dff-ef94-41a3-9d9f-0dc49040473c","owner":[],"postedDate":"May 11th, 2023","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"posted","subjectAreas":[],"tags":[],"updatedAt":"2023-12-09T15:29:31+00:00","versionOfRecord":[],"versionCreatedAt":"2023-05-11 16:54:30","video":"","vorDoi":"","vorDoiUrl":"","workflowStages":[]},"version":"v1","identity":"rs-2867669","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-2867669","identity":"rs-2867669","version":["v1"]},"buildId":"7rjqhiLT3MXkJMwkYKINL","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}