Design of stable low leakage Power Optimized SRAM Array

Design of stable low leakage Power Optimized SRAM Array | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Article Design of stable low leakage Power Optimized SRAM Array Mahammad Aadil S, Bhargava Rama M, Yashwant K S S, Latha P This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-6625510/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract This paper presents the design and comprehensive analysis of a low-power 2X2 SRAM array using CMOS 90nm technology. The proposed system is targeting energy constrained applications such as mobile and embedded systems. The implemented SRAM architecture incorporates a 10T with stacking cell, optimized word line and bit line schemes, and efficient row and column decoders. Robust read and write functionalities are ensured through the integration of precharge circuits, a differential sense amplifier, and write drivers. To minimize power dissipation, transistor stacking techniques are strategically employed within the memory array. The performance of the designed SRAM is rigorously evaluated through simulations using Cadence Virtuoso and Spectre, focusing on critical parameters including hold stability, read stability, write margin, and power consumption. The simulation results demonstrate significant enhancements in power efficiency, read access time, and noise immunity, highlighting the suitability of this SRAM design for energy-efficient systems. Physical sciences/Engineering/Electrical and electronic engineering Physical sciences/Energy science and technology/Energy storage SRAM CMOS Sense Amplifier Noise Margin Stability Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Introduction Designing low-power memory is crucial in modern electronics, particularly for applications where energy efficiency is key, like mobile devices, IoT sensors, and wearable technology. Among various memory types, SRAM is widely used due to its high-speed performance and ability to retain data without frequent refreshing. However, SRAM can also be a significant source of power consumption, especially in applications that require constant standby operation. To address this, techniques such as the transistor stacking effect have emerged as powerful solutions to reduce SRAM’s leakage power. The stacking effect reduces leakage current by placing transistors in series, raising the effective threshold voltage when multiple transistors are off. This “self-reverse bias” effect minimizes leakage power, especially in standby mode, by inhibiting current flow in inactive paths within the memory cell. Applied to SRAM cells, transistor stacking effectively reduces power dissipation while maintaining data stability. This low-power approach is particularly beneficial in high-density SRAM arrays where leakage current can accumulate significantly. Transistor stacking in SRAM not only saves power but also enhances the stability of stored data. By isolating critical storage nodes from bit lines during operations, stacking improves the Static Noise Margin (SNM), which measures an SRAM cell’s resistance to external disturbances. This stability is vital for memory reliability, especially in low- power designs where lower operating voltages can make cells more susceptible to noise. In summary, the use of transistor stacking in SRAM provides a pathway to low-power, reliable memory design. By reducing leakage and boosting stability, this technique makes SRAM better suited for energy-sensitive applications while retaining the speed and robustness that SRAM is known for low power memory. A SRAM cell is a type of memory circuit used to store bits of data in a way that allows for rapid access and low-power retention. Unlike dynamic RAM (DRAM), which requires periodic refreshing to retain data, an SRAM cell can hold data as long as power is supplied, making it both stable and fast1 1 . The basic structure of an SRAM cell consists of two cross-coupled inverters that form a bistable circuit, which can represent binary values (0 or 1). Additional transistors, called access transistors, are connected to control lines known as word lines and bit lines. These access transistors allow the data stored in the cell to be read or written, enabling the high-speed data operations that are characteristic of SRAM cells are commonly used in cache memory and other high-performance applications due to their speed and reliability 2 . The SRAM cell includes two cross-coupled inverters that form the core of the memory cell, maintaining the bit in a stable state as either a 0 or a 1. Each inverter comprises a PMOS and an NMOS transistor, which together create a bi stable circuit, holding the data as long as power is supplied to the cell 3 . In addition to the four transistors forming the inverters, two NMOS transistors function as access transistors. These access transistors connect the cell to external data lines, known as bit lines (BL and BLB), which are used to read data from and write data into the cell. The access transistors are controlled by a word line (WL), which enables access to the cell during read or write operations by switching these transistors on or off 4 . During a write operation, the word line is activated, allowing data from the bit lines to be stored at the internal nodes. For reading, the bit lines are precharged, and the word line enables the access transistors to sense the stored data without disrupting it. The simple and efficient 6T SRAM architecture allows for high-speed operation and reliable data storage, making it widely used in applications that require rapid memory access, such as processor caches and embedded systems. The SRAM cells can be implemented in 6, 7, 8, 10 transistors 5 . A 10T SRAM cell is an advanced static random access memory design with ten transistors, aimed at significantly enhancing data stability, power efficiency, and noise tolerance. This architecture extends the conventional 6T SRAM design by adding four additional transistors to improve isolation between read and write operations, providing a dedicated read path that fully separates it from the write mechanism [5]. This separation is essential for applications where frequent read operations are performed, as it prevents read disturbing issues that can occur in traditional 6T cells, where reading data can unintentionally disrupt the stored bit. The dedicated read port in a 10T SRAM cell ensures that data re- mains undisturbed during access, even at low supply voltages, which is crucial for low-power applications. By incorporating additional transistors, the 10T cell reduces leakage currents and improves retention during idle states, thus decreasing standby power consumption. This low-voltage operation is a key benefit for energy-constrained environments, where maintaining data stability at minimal power is a priority. While the 10T SRAM cell requires a larger area than simpler designs, resulting in slightly reduced memory density, the trade-offs are justified in scenarios that demand both power efficiency and robustness against noise and data loss. The improved noise margins, stable read and write operations, and minimized leakage make 10T SRAM cells shown in Fig. 1 is an optimal choice for modern applications that require consistent performance in energy sensitive contexts 6 . The stacking effect in SRAM cells is a key technique for reducing leakage power, making it essential for low- power memory applications. As device dimensions shrink and threshold voltages decrease, leakage power caused by sub threshold currents in transistors even when they are “off” has become a major design concern. The stacking effect, also known as the” self-reverse bias effect,” tackles this issue by arranging multiple transistors in series within the cell. This configuration increases the effective threshold voltage and reduces sub-threshold leakage current, resulting in significant power savings 7 . In an SRAM cell that uses stacking, transistors are connected in series, which changes their electrical properties. When two or more transistors are placed in a stack, the source of the upper transistor is at a slightly raised voltage compared to the ground level of the lower transistor. This difference creates a reverse-bias effect on the transistors below, effectively increasing their threshold voltage and making it harder for leakage current to flow, even when these transistors are technically” off”. The stacking effect also minimizes drain- induced barrier lowering (DIBL), a phenomenon where high drain voltage lowers the threshold voltage, increasing leakage. By connecting transistors in series, DIBL is reduced, thus conserving power. Beyond lowering power consumption, the stacking effect also improves SRAM stability, particularly during read and write operations. The stacking effect also benefits write operations by further reducing leakage, supporting low power applications that require frequent idle or standby modes. Despite its advantages, the stacking effect has some tradeoffs. Increased resistance in the current path can slightly impact read and write speeds, and the additional transistors may slightly increase cell area, reducing memory density. However, these are minor drawbacks compared to the substantial gains in power efficiency, stability, and noise immunity, making the stacking effect a valuable technique for modern SRAM design, particularly in low-power and energy-sensitive applications 89 . 1 PROPOSED METHODOLOGY The proposed design aims to balance power, performance, and area (PPA) trade-offs to meet the stringent requirements of modern low- power applications, including IoT devices, mobile processors, and high-density memory array. Simulations conducted on 6T, 8T and 10T SRAM cells reveals that the stacking effect in SRAM cells is a key technique to enhance stability and reduces leakage power. A sense amplifier in an SRAM array is a crucial component used during read operations to detect and amplify small voltage differences on the bit-lines and convert them into a full logic level (0 or 1). Since SRAM bit lines are heavily loaded due to large capacitance, the voltage difference generated by a memory cell is small, making amplification necessary for reliable data retrieval. 1.1 10T SRAM with Stacking effect A 10T SRAM cell with stacking effect is a robust memory cell design that focuses on minimizing leakage power and enhancing stability, making it suitable for ultra-low-power applications. The 10T cell design incorporates additional transistors to create fully separate read and write paths, which eliminates the risk of read disturbance and enhances data integrity during access. In addition to leakage reduction, the stacking effect within the 10T SRAM cell improves data stability by isolating storage nodes from fluctuations on the bit lines. This isolation is particularly advantageous for systems that operate at low voltages, as it enhances noise immunity and ensures reliable data retention 10 . While the 10T configuration with stacking requires more chip area and can introduce slightly higher resistance in the current path, these trade-offs are minor compared to the gains in power efficiency and stability 11 . This makes the 10T SRAM cell with stacking effect ideal for power-sensitive applications are low power and high reliability are essential. Figure 1 shows the circuit of a 10 transistor SRAM cell with stacking effect which has additional transistors added in to the 10 transistors to perform the stacking effect 1.1.1 SRAM array The 2x2 SRAM array shown in Fig. 2 consists of 1 to 2 row decoder, 1 to 2 column decoder, writer driver, precharge circuit, 4 SRAM cell (2x2) and sense amplifier circuits. Decoder are used to select data selection in the memory. Write driver is used to write the data in memory all through the write enable signal is high. The voltage latch sense amplifier is used to attain low power intake rather than of current latch sense amplifier. SRAM array has many components, AND gate that can be used to control the activation of the word line (WL) based on multiple enabling signals. It helps to determine whether a read or write operation should occur based on control signals. Inverters during write operation data is written into the SRAM cell, the cross-coupled inverters quickly switch states to store the new value during read operation, the bitline voltages are sensed by the sense amplifier. The inverters ensure that the stored data is not altered due to small voltage fluctuations. The decoder translates the binary address input into a unique memory row/column selection signal. It ensures that only one word line (WL) or bitline (BL) is activated at a time, preventing conflicts and errors 10 .Isolation ensures signal integrity, power efficiency, and stability during read and write operations and help in preventing unwanted disturbances to stored data and reducing leakage currents. Recharge is essential for preparing the bitlines before a read or write operation. It ensures fast, reliable, and power-efficient memory access.Sense amplifier is responsible for quickly and accurately detecting stored data during a read operation. It amplifies the signals into full logic levels (0 or 1), ensuring fast and power-efficient memory access. Writer drivers in SRAM enable efficient memory operations by controlling word lines, bitlines, sense amplifiers, and precharge circuits. They help reduce access time, improve stability, and enhance power efficiency, making them essential components in SRAM design. 1.2 Amplification Phase The sense amplifier detects the small difference and quickly pulls one line to VDD and the other to GND .This amplifies the weak signal to a full logic level (0 or 1). Differential Sense Amplifier (DSA) shown in Fig. 3 is a widely used circuit in SRAM arrays for detecting and amplifying small voltage differences between complementary bit-lines (BL and BL¯) during read operations. It ensures fast, power efficient, and noise-resistant data retrieval 12 .We Use a Differential Sense Amplifier as it amplifies small signals quickly.The SRAM cell generates a small voltage difference ( 100mV) on BL and BL¯ .The sense amplifier amplifiesthis difference to full logic levels (0 or 1). It enhances read speed, the differential approach speeds up sensing by triggering when a small thresh- old difference is reached.And minimizes power consumption instead of fully discharging bit-lines, it detects small changes early, reducing unnecessary power usage,improves noise immunity 13 .Since it relies on the difference between BL and BL¯, common- mode noise has minimal effect. Latch Sense Amplifier shown in Fig. 4 is a commonly used circuit in SRAM read operations. It operates using positive feed back from cross coupled inverters, making it fast, power efficient, and highly sensitive to small voltage differences between bit-lines (BL and BL¯). In precharge phase before reading, both BL and BL¯ are precharged to VDD using a precharge circuit. In discharge phase when a wordline (WL) is activated, the SRAM cell weakly pulls one bit-line lower, creating a small voltage difference ( 100mV) 14 . Latch Activation (Amplification Phase), the sense amplifier enable signal activates the cross-coupled inverters. Positive feedback forces one side to VDD (logic 1) and the other to GND (logic 0), amplifying the small bit-line difference to a full logic level. 2 RESULTS AND DISCUSSIONS The 2×2 SRAM array is a fundamental building block in memory design, used for high-speed and low-power data storage. It consists of SRAM cells arranged in rows and columns, controlled by row and column decoders to enable efficient read and write operations. Key components such as bitlines, wordlines, precharge circuits, sense amplifiers, and write drivers ensure reliable data access. Stability and power efficiency are crucial factors, influenced by techniques like gated VDD, stacking, and MTCMOS for leakage power reduction. Performance metrics such as read/write delay, static noise margin (SNM), and power consumption determine the efficiency of the design.. The value of the Stability is obtained by the largest square that could fit in the butterfly graph as shown in the figure. 5, as the butterfly graph came from the Q vs Q bar and Q bar vs Q both in single window which makes both the X and Y axes are voltages of Q or Q bar vice versa 13 . The SNM analysis of 6T SRAM cell from which the stability is the value of the side of a square which fit in the butterfly graph in voltages and for 6T it is 255mV and by following the same process we obtain stability values for 7T as 159mV, for the 8T it is 270mV and for the 10T SRAM cell it is 273mV. In the SNM analysis the greater the value the stable it is so the value it is called stability of the SRAM cell 2.1 Write and Read Operation Analysis The write operation in a 2×2 SRAM array involves storing data to the memory cells without any error. The Fig. 6 shows the Write and read circuit schematic. The Fig. 7 shows transient analysis of write operation respectively. For writing ”0” logic into the SRAM which in turn emphasises the need for stronger access transistors 15 . Consider a logic ”0” to a cell that has stored a logic.”1”. The write driver makes BL = 0V and BL’= VDD as logic ’0’ is written into the cell. The write driver circuit provides the required voltage to BL and BL’ ( For write 0, BL = 0, BL’ = 1 and for write 1, BL = 1, BL’ = 0). Now the address line is enabled by the decoder circuit which makes WL = 1. The word line is made high and hence bit lines BL and BL’ are connected to SRAM cell through the access transistors. The corresponding data is written into the cell ( Q = 0 for write logic 0 and Q = 1 for write logic 1. Q’ side of the cell cant be pulled high enough to make the writing of ’1’ due to the sizing constraint imposed by the read stability. It makes that voltage is below 0.4V. Hence the new value must be written through the transistor M6. Data ’0’ will be written into the cell if node Q is pulled down, below the threshold of M1 to turn it OFF. The read operation shown in Fig. 8 involves retrieving stored data from the memory cells without altering their contents. This process requires coordinated actions from wordlines (WL), bit-lines (BL and BL¯), sense amplifiers, and precharge circuits to ensure accurate and efficient data retrieval. Precharging the Bit-lines, before reading the bit lines are precharged to a reference voltage (usually VDD/2 or VDD) using a precharge circuit to ensure a proper voltage difference during sensing16. Activating the Wordline, the row decoder selects the corresponding memory row by enabling the appropriate wordline (WL). This connects the SRAM cell to the bit-lines. Discharging the Bit-lines depending on the stored data (0 or 1), the internal pull-down transistors of the SRAM cell pull one bit-line slightly lower, creating a small voltage difference between BL and BL¯. Sensing the Voltage Difference, sense amplifier detects the small voltage difference between BL and BL¯ and amplifies it to a full logic level (0 or 1).Data Read Successfully, the output of the sense amplifier represents the stored bit, which is then sent to the output buffer. 2.2 SRAM cell Stability Stability in an SRAM cell is crucial to ensure data retention, reliable read/write operations, and noise tolerance. It is typically analyzed using Static Noise Margin (SNM) and influenced by various design parameters such as transistor sizing, bit-line capacitance, and supply voltage variations. Static Noise Margin (SNM): SNM is the highest noise voltage that can be tolerated by an SRAM cell before flipping its stored value. It is typically measured using butterfly curves by plotting the voltage transfer characteristics (VTC) of the cross-coupled inverters in the SRAM cell 16 .Higher SNM values indicate better stability. Read ,Write and Hold Stability: During a read operation, one bitline remains precharged, while the other begins to discharge. If the access transistor is too strong, it may disturb the stored value, leading to read failure. Increasing cell ratio (CR = Pull-down NMOS/Access NMOS) improves read stability.During a write operation, the bit-lines force the internal node of the SRAM cell to switch. If the pull-up PMOS is too strong, it may resist the switching process, causing a write failure. Increasing pull-up ratio (PR = Access NMOS/Pull-up PMOS) improves write stability.Hold stability in an SRAM 2×2 array refers to the capacity of an SRAM cell to retain its stored data when no read or write operations are performed. SNM in hold mode is a key metric used to evaluate the stability of an SRAM cell under process variations, voltage fluctuations, and leakage currents. Key Factors Affecting Hold Stability.In Hold Mode: SNM defines the maximum allowable noise voltage that an SRAM cell can tolerate before its state flips. In hold mode, the wordline (WL) is inactive (0V), isolating the SRAM cell from the bit-lines. The cross-coupled inverters of the SRAM cell must maintain a strong latch behavior to retain stored data.Lowering VDD reduces power consumption but also decreases SNM, making the SRAM more vulnerable to noise and data loss. Higher VDD improves hold stability but increases leakage power 17 .An optimal trade-off is necessary to balance power and stability. In deep submicron technologies (e.g., 90nm, 45nm), subthreshold leakage and gate leakage can degrade hold stability. Techniques like stack- ing transistors, gated VDD, and reverse body biasing help reduce leakage currents, improving hold stability 8 . Table 1 Comparison between 6T and 10T SRAM Cells with and without Stacking Features 6 Transistors Stacked 6 Transistors 10 Transistors Stacked 10 Transistors write SNM(mV) 390 425 510 584 Read stability analysis(mV) 249 324 102 167 SNM(mV) 255.2 319.6 263 298 Delay(ns) 536 475 98 35 Total Power( µW ) 147.6 83.64 190.1 161.9 Table 1 shows the comparison between 6T and 10T SRAM cells with and without stacking in CMOS 90nm technology with a supply voltage of 1.8V. It can be inferred that stacked SRAM cells significantly enhance energy efficiency by reducing leakage currents. Compared to 6T SRAM cells, 10T SRAM cells provide better noise margins and faster access time. 2.3 Writer Driver Circuit Analysis The write driver circuit to ensuring efficient and reliable data writing to the memory cells shown in Fig. 9 and its transient analysis is shown in Fig. 10 . It is responsible for driving the bit-lines to the required voltage levels during a write operation while ensuring minimal power dissipation and delay 18 . Proper design of the write driver enhances the write stability and speed, which are essential for high-performance SRAM arrays. Function of the Write Driver Circuit forces the Bit-Lines to Desired Values. The write driver pulls one bit-line to VDD and the other to GND to ensure successful data storage in the SRAM cell. The SRAM cell is a cross-coupled inverter structure, which inherently holds its previous state. The write driver must be strong enough to override the existing stored value without excessive power consumption 19 . The duration for which the wordline (WL) is activated determines the success of the write operation. The write driver must deliver enough current within this period to ensure data is reliably stored. 2.4 Precharge Circuit Analysis The precharge circuit (PCH) is shown in Fig. 11 used to ensure that the bit-lines are precharged to stable voltage before every read or write operation 20 . In a 2×2 SRAM array, the PCH circuit plays a crucial role in maintaining low power consumption, reducing access time, improving read stability.Uncontrolled bit- line fluctuations lead to unnecessary power dissipation. The PCH circuit reduces dynamic power loss by minimizing bit- line voltage swings. Variations in bit-line voltages can lead to incorrect reads or slower sensing. The precharge circuit equalizes BL and BL¯ to prevent bias during operations ? . 2.5 Sense Amplifier Analysis Table 2 presents a comparative analysis of three types of sense amplifiers: Differential Sense Amplifier, Basic Latched Sense Amplifier, and Basic Sense Amplifier. The parameters considered include the supply voltage, the number of transistors used, Table 2 Average Power Consumption of Sense Amplifiers Sense Amplifier Design Type Number of transistors Average Power Consumption in mWatts Differential Sense Amplifier 4 179.94 Basic Latched Sense Amplifier 6 80.713 Basic Sense Amplifier 5 80 mW and the average power consumption. The Differential Sense Amplifier exhibits the highest power consumption of 179.94 mW, as it requires four transistors. Despite its higher power usage, it provides superior signal amplification and noise immunity, making it an optimal choice for high- performance SRAM designs 21 . The Basic Latched Sense Amplifier, using six transistors, achieves a balance between power consumption (80.713 mW) and signal amplification, benefiting from latching mechanisms that enhance stability. The Basic Sense Amplifier consumes the least power (80 mW) while requiring five transistors. However, it may not provide the same noise immunity and speed as the differential design. The transient analysis graph shown in Fig. 12 ,represents the sensing operation of a 2×2 SRAM array’s sense amplifier, showing how it detects and amplifies a small voltage difference between bitlines.The voltage remains stable at approximately 1.46V, indicating that the bitlines are precharged to a high voltage level before the sensing operation begins 22 . This precharged state ensures that the sense amplifier can quickly detect small differences in voltage when a read operation occurs. At around 6.25 ns, the voltage begins to decrease, marking the activation of the sense amplifier. The circuit took 250 ps to sense a 200 mV difference, indicating that the sense amplifier successfully detected the stored bit in one of the SRAM cells. This transition occurs due to the slight difference in bitline voltages, which the sense amplifier amplifies rapidly. After the sensing phase, the voltage drops exponentially as the sense amplifier fully resolves the bitline difference and drives the output to a stable logic level. This behavior reflects the discharging of bitlines through the sense amplifier circuitry. Conclusion The proposed 2×2 SRAM architecture demonstrates notable advancements in power efficiency, speed, and reliability, positioning it as a promising candidate for contemporary low-power, high-performance applications including IoT devices, mobile processors, and embedded systems. Through comparative analysis of 6T, 8T, and 10T SRAM cells—with and without transistor stacking—the 10T cell with stacking was selected for integration due to its superior stability and reduced power consumption. The implemented 10T SRAM cell effectively minimizes leakage power, contributing to a total power consumption of 200 µW for the complete architecture. The design also exhibits high-speed read operations, achieving a sensing delay of 250 ps for a 200 mV input. Furthermore, the architecture ensures robust operational stability, demonstrated by a read static noise margin (RSNM) of 167 mV and a write static noise margin (WSNM) of 584 mV. Future work may explore optimization using advanced device technologies such as FinFETs or Gate-All-Around FETs to further enhance leakage reduction and scalability. Declarations Additional information The authors declare no conflict of interest. Funding Declaration No Funding Received. Author Contribution S. Mahammad Aadil, M. Bhargava Rama, and K. S. S. Yashwant are B.Tech students who conducted research on this topic. P. Latha is the corresponding author who supervised the work and guided the drafting of this journal article Acknowledgement The authors gratefully acknowledge Vellore Institute of Technology ,Chennai for providing the necessary facilities and support to carry out this research work Data Availability No datasets were generated or analysed during the current study. References Rao, S., Bhat, M., Anchan, P. G., Shetty, N. & Rodrigues, L. M. 8 × 8 sram cell array for low-power applications. In 2024 International Conference on Innovation and Novelty in Engineering and Technology (INNOVA) , vol. 1, 1–6 (IEEE, 2024). Liu, Z. & Kursun, V. Characterization of a novel nine-transistor sram cell. Very Large Scale Integration (VLSI) Syst. IEEE Transactions on 16 , 488 – 492, DOI: 10.1109/TVLSI.2007.915499 (2008). Asthana, P. & Mangesh, S. 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University","correspondingAuthor":false,"prefix":"","firstName":"Bhargava","middleName":"Rama","lastName":"M","suffix":""},{"id":469953029,"identity":"55998ab8-6f7c-49b1-a0a0-30da92d083df","order_by":2,"name":"Yashwant K S S","email":"","orcid":"","institution":"Vellore Institute of Technology University","correspondingAuthor":false,"prefix":"","firstName":"Yashwant","middleName":"K S","lastName":"S","suffix":""},{"id":469953030,"identity":"573fef6b-3930-4a51-80a0-d5d57376da63","order_by":3,"name":"Latha P","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAAAyUlEQVRIiWNgGAWjYFAC5gYGxgYGOQZmCJeHCC1A9QcbGIwZmJlJ1JLYALOGIDBnYGz8/HGHXfqG4/wHGH7UMMiYE9Ji2cDYLHHwTHLuhsPMDIw9xxh4LBsIaDE4wNggcbCNOXdmM9BhvA0MPAYHCGtp/nGwrT5dEqiF8S+RWtqAthxO4AeGGDNRtlg2M7ZZnG07btjPzGxwWOaYBGEt5uzNh29UtlXLs/EffPjwTY2NPWGHIccGULEEAfUgLYSVjIJRMApGwYgHAAqTOjnxQIuRAAAAAElFTkSuQmCC","orcid":"","institution":"Vellore Institute of Technology University","correspondingAuthor":true,"prefix":"","firstName":"Latha","middleName":"","lastName":"P","suffix":""}],"badges":[],"createdAt":"2025-05-09 06:23:10","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-6625510/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-6625510/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":84472528,"identity":"f56ad904-aa01-459c-9a72-c8b4444e6420","added_by":"auto","created_at":"2025-06-12 10:42:14","extension":"jpeg","order_by":1,"title":"Figure 1","display":"","copyAsset":false,"role":"figure","size":409027,"visible":true,"origin":"","legend":"\u003cp\u003e10T stacking-SRAM\u003c/p\u003e","description":"","filename":"floatimage1.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-6625510/v1/0537d1d2f76c404c58c6f160.jpeg"},{"id":84472527,"identity":"0df16651-efac-4387-b214-4786f5f03c63","added_by":"auto","created_at":"2025-06-12 10:42:14","extension":"png","order_by":2,"title":"Figure 2","display":"","copyAsset":false,"role":"figure","size":74944,"visible":true,"origin":"","legend":"\u003cp\u003e2X2 SRAM Array\u003c/p\u003e","description":"","filename":"floatimage2.png","url":"https://assets-eu.researchsquare.com/files/rs-6625510/v1/1fcfdac8fd7242be5b2d0025.png"},{"id":84472530,"identity":"890180e2-05de-494f-a40e-85a694f53adf","added_by":"auto","created_at":"2025-06-12 10:42:14","extension":"png","order_by":3,"title":"Figure 3","display":"","copyAsset":false,"role":"figure","size":129833,"visible":true,"origin":"","legend":"\u003cp\u003eDifferential Sense amplifier\u003c/p\u003e","description":"","filename":"floatimage3.png","url":"https://assets-eu.researchsquare.com/files/rs-6625510/v1/31522da7c464f6c7a94eb60d.png"},{"id":84472534,"identity":"a34f9eb3-a855-4106-8e2a-5c862e36cf71","added_by":"auto","created_at":"2025-06-12 10:42:15","extension":"jpeg","order_by":4,"title":"Figure 4","display":"","copyAsset":false,"role":"figure","size":332987,"visible":true,"origin":"","legend":"\u003cp\u003eLatch Sense Amplifier\u003c/p\u003e","description":"","filename":"floatimage4.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-6625510/v1/72b58e6bd16eba31b71addac.jpeg"},{"id":84472532,"identity":"f5d90645-438a-46a0-9d18-aab6c3a133e3","added_by":"auto","created_at":"2025-06-12 10:42:14","extension":"jpeg","order_by":5,"title":"Figure 5","display":"","copyAsset":false,"role":"figure","size":226198,"visible":true,"origin":"","legend":"\u003cp\u003e6T-SNM Analysis\u003c/p\u003e","description":"","filename":"floatimage5.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-6625510/v1/c995ce9f7ad7b4533d04814c.jpeg"},{"id":84472536,"identity":"7dde2397-02f4-4428-b14b-f5cba56926b9","added_by":"auto","created_at":"2025-06-12 10:42:15","extension":"jpeg","order_by":6,"title":"Figure 6","display":"","copyAsset":false,"role":"figure","size":180339,"visible":true,"origin":"","legend":"\u003cp\u003eWrite Read Operation Circuit\u003c/p\u003e","description":"","filename":"floatimage6.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-6625510/v1/9305a68886a3b0ba2f8ab360.jpeg"},{"id":84472551,"identity":"7890f0be-f342-4c79-ba3b-c3633b8e3061","added_by":"auto","created_at":"2025-06-12 10:42:15","extension":"jpeg","order_by":7,"title":"Figure 7","display":"","copyAsset":false,"role":"figure","size":429439,"visible":true,"origin":"","legend":"\u003cp\u003eWrite operation Transient Analysis\u003c/p\u003e","description":"","filename":"floatimage7.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-6625510/v1/c807ffb65bcc788ea7cf56a6.jpeg"},{"id":84472808,"identity":"c8649cea-ca33-41d9-86d9-14ac1e02ca68","added_by":"auto","created_at":"2025-06-12 10:50:15","extension":"jpeg","order_by":8,"title":"Figure 8","display":"","copyAsset":false,"role":"figure","size":317336,"visible":true,"origin":"","legend":"\u003cp\u003eRead operation Transient Analysis\u003c/p\u003e","description":"","filename":"floatimage8.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-6625510/v1/934b97895f4d8ed3df9f487c.jpeg"},{"id":84472547,"identity":"4f2556c2-efde-460e-a30b-d92136b10f4e","added_by":"auto","created_at":"2025-06-12 10:42:15","extension":"jpeg","order_by":9,"title":"Figure 9","display":"","copyAsset":false,"role":"figure","size":473584,"visible":true,"origin":"","legend":"\u003cp\u003eWrite Driver Circuit\u003c/p\u003e","description":"","filename":"floatimage9.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-6625510/v1/bf57c12617d2b2c5b5b43897.jpeg"},{"id":84472811,"identity":"22b943ec-e355-45ca-aab1-2dfca39bf99e","added_by":"auto","created_at":"2025-06-12 10:50:15","extension":"jpeg","order_by":10,"title":"Figure 10","display":"","copyAsset":false,"role":"figure","size":922971,"visible":true,"origin":"","legend":"\u003cp\u003eWrite Driver Circuit Transient analysis\u003c/p\u003e","description":"","filename":"floatimage10.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-6625510/v1/7e62576e7aa7a20aa639c3d5.jpeg"},{"id":84473985,"identity":"2a94c567-e7c3-44e4-843a-5bdfb9c60303","added_by":"auto","created_at":"2025-06-12 10:58:15","extension":"png","order_by":11,"title":"Figure 11","display":"","copyAsset":false,"role":"figure","size":15346,"visible":true,"origin":"","legend":"\u003cp\u003ePrecharge Circuit\u003c/p\u003e","description":"","filename":"floatimage11.png","url":"https://assets-eu.researchsquare.com/files/rs-6625510/v1/ff1d96ae1dd95b6c40868f29.png"},{"id":84472554,"identity":"179a589b-596d-47b3-9e6b-22466771591c","added_by":"auto","created_at":"2025-06-12 10:42:15","extension":"jpeg","order_by":12,"title":"Figure 12","display":"","copyAsset":false,"role":"figure","size":258360,"visible":true,"origin":"","legend":"\u003cp\u003eSense Margin\u003c/p\u003e","description":"","filename":"floatimage12.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-6625510/v1/a660c8e0c8a5aaddc47ee8a2.jpeg"},{"id":85192824,"identity":"20131b49-1e01-4f36-bc0c-b6729d1cca5f","added_by":"auto","created_at":"2025-06-23 09:02:26","extension":"pdf","order_by":0,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":4374086,"visible":true,"origin":"","legend":"","description":"","filename":"manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-6625510/v1/24a3e35c-3f4b-40e1-92d6-5172aaaf7149.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"Design of stable low leakage Power Optimized SRAM Array","fulltext":[{"header":"Introduction","content":"\u003cp\u003eDesigning low-power memory is crucial in modern electronics, particularly for applications where energy efficiency is key, like mobile devices, IoT sensors, and wearable technology. Among various memory types, SRAM is widely used due to its high-speed performance and ability to retain data without frequent refreshing. However, SRAM can also be a significant source of power consumption, especially in applications that require constant standby operation. To address this, techniques such as the transistor stacking effect have emerged as powerful solutions to reduce SRAM\u0026rsquo;s leakage power. The stacking effect reduces leakage current by placing transistors in series, raising the effective threshold voltage when multiple transistors are off. This \u0026ldquo;self-reverse bias\u0026rdquo; effect minimizes leakage power, especially in standby mode, by inhibiting current flow in inactive paths within the memory cell. Applied to SRAM cells, transistor stacking effectively reduces power dissipation while maintaining data stability. This low-power approach is particularly beneficial in high-density SRAM arrays where leakage current can accumulate significantly.\u003c/p\u003e \u003cp\u003eTransistor stacking in SRAM not only saves power but also enhances the stability of stored data. By isolating critical storage nodes from bit lines during operations, stacking improves the Static Noise Margin (SNM), which measures an SRAM cell\u0026rsquo;s resistance to external disturbances. This stability is vital for memory reliability, especially in low- power designs where lower operating voltages can make cells more susceptible to noise. In summary, the use of transistor stacking in SRAM provides a pathway to low-power, reliable memory design. By reducing leakage and boosting stability, this technique makes SRAM better suited for energy-sensitive applications while retaining the speed and robustness that SRAM is known for low power memory. A SRAM cell is a type of memory circuit used to store bits of data in a way that allows for rapid access and low-power retention. Unlike dynamic RAM (DRAM), which requires periodic refreshing to retain data, an SRAM cell can hold data as long as power is supplied, making it both stable and fast1\u003csup\u003e1\u003c/sup\u003e. The basic structure of an SRAM cell consists of two cross-coupled inverters that form a bistable circuit, which can represent binary values (0 or 1). Additional transistors, called access transistors, are connected to control lines known as word lines and bit lines. These access transistors allow the data stored in the cell to be read or written, enabling the high-speed data operations that are characteristic of SRAM cells are commonly used in cache memory and other high-performance applications due to their speed and reliability\u003csup\u003e\u003cspan citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e\u003c/sup\u003e. The SRAM cell includes two cross-coupled inverters that form the core of the memory cell, maintaining the bit in a stable state as either a 0 or a\u003c/p\u003e \u003cp\u003e1. Each inverter comprises a PMOS and an NMOS transistor, which together create a bi stable circuit, holding the data as long as power is supplied to the cell\u003csup\u003e\u003cspan citationid=\"CR3\" class=\"CitationRef\"\u003e3\u003c/span\u003e\u003c/sup\u003e. In addition to the four transistors forming the inverters, two NMOS transistors function as access transistors. These access transistors connect the cell to external data lines, known as bit lines (BL and BLB), which are used to read data from and write data into the cell. The access transistors are controlled by a word line (WL), which enables\u003c/p\u003e \u003cp\u003eaccess to the cell during read or write operations by switching these transistors on or off\u003csup\u003e\u003cspan citationid=\"CR4\" class=\"CitationRef\"\u003e4\u003c/span\u003e\u003c/sup\u003e. During a write operation, the word line is activated, allowing data from the bit lines to be stored at the internal nodes.\u003c/p\u003e \u003cp\u003eFor reading, the bit lines are precharged, and the word line enables the access transistors to sense the stored data without disrupting it. The simple and efficient 6T SRAM architecture allows for high-speed operation and reliable data storage, making it widely used in applications that require rapid memory access, such as processor caches and embedded systems. The SRAM cells can be implemented in 6, 7, 8, 10 transistors\u003csup\u003e\u003cspan citationid=\"CR5\" class=\"CitationRef\"\u003e5\u003c/span\u003e\u003c/sup\u003e. A 10T SRAM cell is an advanced static random access memory design with ten transistors, aimed at significantly enhancing data stability, power efficiency, and noise tolerance. This architecture extends the conventional 6T SRAM design by adding four additional transistors to improve isolation between read and write operations, providing a dedicated read path that fully separates it from the write mechanism [5]. This separation is essential for applications where frequent read operations are performed, as it prevents read disturbing issues that can occur in traditional 6T cells, where reading data can unintentionally disrupt the stored bit. The dedicated read port in a 10T SRAM cell ensures that data re- mains undisturbed during access, even at low supply voltages, which is crucial for low-power applications. By incorporating additional transistors, the 10T cell reduces leakage currents and improves retention during idle states, thus decreasing standby power consumption. This low-voltage operation is a key benefit for energy-constrained environments, where maintaining data stability at minimal power is a priority. While the 10T SRAM cell requires a larger area than simpler designs, resulting in slightly reduced memory density, the trade-offs are justified in scenarios that demand both power efficiency and robustness against noise and data loss. The improved noise margins, stable read and write operations, and minimized leakage make 10T SRAM cells shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003e is an optimal choice for modern applications that require consistent performance in energy sensitive contexts\u003csup\u003e\u003cspan citationid=\"CR6\" class=\"CitationRef\"\u003e6\u003c/span\u003e\u003c/sup\u003e.\u003c/p\u003e \u003cp\u003eThe stacking effect in SRAM cells is a key technique for reducing leakage power, making it essential for low- power memory applications. As device dimensions shrink and threshold voltages decrease, leakage power caused by sub threshold currents in transistors even when they are \u0026ldquo;off\u0026rdquo; has become a major design concern. The stacking effect, also known as the\u0026rdquo; self-reverse bias effect,\u0026rdquo; tackles this issue by arranging multiple transistors in series within the cell. This configuration increases the effective threshold voltage and reduces sub-threshold leakage current, resulting in significant power savings\u003csup\u003e\u003cspan citationid=\"CR7\" class=\"CitationRef\"\u003e7\u003c/span\u003e\u003c/sup\u003e. In an SRAM cell that uses stacking, transistors are connected in series, which changes their electrical properties. When two or more transistors are placed in a stack, the source of the upper transistor is at a slightly raised voltage compared to the ground level of the lower transistor. This difference creates a reverse-bias effect on the transistors below, effectively increasing their threshold voltage and making it harder for leakage current to flow, even when these transistors are technically\u0026rdquo; off\u0026rdquo;. The stacking effect also minimizes drain- induced barrier lowering (DIBL), a phenomenon where high drain voltage lowers the threshold voltage, increasing leakage. By connecting transistors in series, DIBL is reduced, thus conserving power. Beyond lowering power consumption, the stacking effect also improves SRAM stability, particularly during read and write operations. The stacking effect also benefits write operations by further reducing leakage, supporting low power applications that require frequent idle or standby modes. Despite its advantages, the stacking effect has some tradeoffs. Increased resistance in the current path can slightly impact read and write speeds, and the additional transistors may slightly increase cell area, reducing memory density. However, these are minor drawbacks compared to the substantial gains in power efficiency, stability, and noise immunity, making the stacking effect a valuable technique for modern SRAM design, particularly in low-power and energy-sensitive applications\u003csup\u003e89\u003c/sup\u003e.\u003c/p\u003e"},{"header":"1 PROPOSED METHODOLOGY","content":"\u003cp\u003eThe proposed design aims to balance power, performance, and area (PPA) trade-offs to meet the stringent requirements of modern low- power applications, including IoT devices, mobile processors, and high-density memory array.\u003c/p\u003e\n\u003cul\u003e\n \u003cli\u003e\n \u003cp\u003eSimulations conducted on 6T, 8T and 10T SRAM cells reveals that the stacking effect in SRAM cells is a key technique to enhance stability and reduces leakage power.\u003c/p\u003e\n \u003c/li\u003e\n \u003cli\u003e\n \u003cp\u003eA sense amplifier in an SRAM array is a crucial component used during read operations to detect and amplify small voltage differences on the bit-lines and convert them into a full logic level (0 or 1). Since SRAM bit lines are heavily loaded due to large capacitance, the voltage difference generated by a memory cell is small, making amplification necessary for reliable data retrieval.\u003c/p\u003e\n \u003c/li\u003e\n\u003c/ul\u003e\n\u003cdiv id=\"Sec3\" class=\"Section2\"\u003e\n \u003ch2\u003e1.1 10T SRAM with Stacking effect\u003c/h2\u003e\n \u003cp\u003eA 10T SRAM cell with stacking effect is a robust memory cell design that focuses on minimizing leakage power and enhancing stability, making it suitable for ultra-low-power applications. The 10T cell design incorporates additional transistors to create fully separate read and write paths, which eliminates the risk of read disturbance and enhances data integrity during access. In addition to leakage reduction, the stacking effect within the 10T SRAM cell improves data stability by isolating storage nodes from fluctuations on the bit lines. This isolation is particularly advantageous for systems that operate at low voltages, as it enhances noise immunity and ensures reliable data retention\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e10\u003c/span\u003e\u003c/sup\u003e. While the 10T configuration with stacking requires more chip area and can introduce slightly higher resistance in the current path, these trade-offs are minor compared to the gains in power efficiency and stability\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e11\u003c/span\u003e\u003c/sup\u003e. This makes the 10T SRAM cell with stacking effect ideal for power-sensitive applications are low power and high reliability are essential. Figure \u003cspan class=\"InternalRef\"\u003e1\u003c/span\u003e shows the circuit of a 10 transistor SRAM cell with stacking effect which has additional transistors added in to the 10 transistors to perform the stacking effect\u003c/p\u003e\n\u003c/div\u003e\n\u003ch3\u003e1.1.1 SRAM array\u003c/h3\u003e\n\u003cp\u003eThe 2x2 SRAM array shown in Fig.\u0026nbsp;\u003cspan class=\"InternalRef\"\u003e2\u003c/span\u003e consists of 1 to 2 row decoder, 1 to 2 column decoder, writer driver, precharge circuit, 4 SRAM cell (2x2) and sense amplifier circuits. Decoder are used to select data selection in the memory. Write driver is used to write the data in memory all through the write enable signal is high. The voltage latch sense amplifier is used to attain low power intake rather than of current latch sense amplifier. SRAM array has many components, AND gate that can be used to control the activation of the word line (WL) based on multiple enabling signals. It helps to determine whether a read or write operation should occur based on control signals. Inverters during write operation data is written into the SRAM cell, the cross-coupled inverters quickly switch states to store the new value during read operation, the bitline voltages are sensed by the sense amplifier. The inverters ensure that the stored data is not altered due to small voltage fluctuations. The decoder translates the binary address input into a unique memory row/column selection signal. It ensures that only one word line (WL) or bitline (BL) is activated at a time, preventing conflicts and errors\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e10\u003c/span\u003e\u003c/sup\u003e.Isolation ensures signal integrity, power efficiency, and stability during read and write operations and help in preventing unwanted disturbances to stored data and reducing leakage currents. Recharge is essential for preparing the bitlines before a read or write operation. It ensures fast, reliable, and power-efficient memory access.Sense amplifier is responsible for quickly and accurately detecting stored data during a read operation. It amplifies the signals into full logic levels (0 or 1), ensuring fast and power-efficient memory access. Writer drivers in SRAM enable efficient memory operations by controlling word lines, bitlines, sense amplifiers, and precharge circuits. They help reduce access time, improve stability, and enhance power efficiency, making them essential components in SRAM design.\u003c/p\u003e\n\u003ch3\u003e1.2 Amplification Phase\u003c/h3\u003e\n\u003cp\u003eThe sense amplifier detects the small difference and quickly pulls one line to VDD and the other to GND .This amplifies the weak signal to a full logic level (0 or 1). Differential Sense Amplifier (DSA) shown in Fig. \u003cspan class=\"InternalRef\"\u003e3\u003c/span\u003e is a widely used circuit in SRAM arrays for detecting and amplifying small voltage differences between complementary bit-lines (BL and BL\u0026macr;) during read operations. It ensures fast, power efficient, and noise-resistant data retrieval\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e12\u003c/span\u003e\u003c/sup\u003e.We Use a Differential Sense Amplifier as it amplifies small signals quickly.The SRAM cell generates a small voltage difference ( 100mV) on BL and BL\u0026macr; .The sense amplifier amplifiesthis difference to full logic levels (0 or 1). It enhances read speed, the differential approach speeds up sensing by triggering when a small thresh- old difference is reached.And minimizes power consumption instead of fully discharging bit-lines, it detects small changes early, reducing unnecessary power usage,improves noise immunity\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e13\u003c/span\u003e\u003c/sup\u003e.Since it relies on the difference between BL and BL\u0026macr;, common- mode noise has minimal effect.\u003c/p\u003e\n\u003cp\u003eLatch Sense Amplifier shown in Fig. \u003cspan class=\"InternalRef\"\u003e4\u003c/span\u003e is a commonly used circuit in SRAM read operations. It operates using positive feed back from cross coupled inverters, making it fast, power efficient, and highly sensitive to small voltage differences between bit-lines (BL and BL\u0026macr;). In precharge phase before reading, both BL and BL\u0026macr; are precharged to VDD using a precharge circuit. In discharge phase when a wordline (WL) is activated, the SRAM cell weakly pulls one bit-line lower, creating a small voltage difference ( 100mV)\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e14\u003c/span\u003e\u003c/sup\u003e. Latch Activation (Amplification Phase), the sense amplifier enable signal activates the cross-coupled inverters. Positive feedback forces one side to VDD (logic 1) and the other to GND (logic 0), amplifying the small bit-line difference to a full logic level.\u003c/p\u003e"},{"header":"2 RESULTS AND DISCUSSIONS","content":"\u003cp\u003eThe 2\u0026times;2 SRAM array is a fundamental building block in memory design, used for high-speed and low-power data storage. It consists of SRAM cells arranged in rows and columns, controlled by row and column decoders to enable efficient read and write operations. Key components such as bitlines, wordlines, precharge circuits, sense amplifiers, and write drivers ensure reliable data access. Stability and power efficiency are crucial factors, influenced by techniques like gated VDD, stacking, and MTCMOS for leakage power reduction. Performance metrics such as read/write delay, static noise margin (SNM), and power consumption determine the efficiency of the design.. The value of the Stability is obtained by the largest square that could fit in the butterfly graph as shown in the figure. 5, as the butterfly graph came from the Q vs Q bar and Q bar vs Q both in single window which makes both the X and Y axes are voltages of Q or Q bar vice versa\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e13\u003c/span\u003e\u003c/sup\u003e. The SNM analysis of 6T SRAM cell from which the stability is the value of the side of a square which fit in the butterfly graph in voltages and for 6T it is 255mV and by following the same process we obtain stability values for 7T as 159mV, for the 8T it is 270mV and for the 10T SRAM cell it is 273mV. In the SNM analysis the greater the value the stable it is so the value it is called stability of the SRAM cell\u003c/p\u003e\n\u003ch3\u003e2.1 Write and Read Operation Analysis\u003c/h3\u003e\n\u003cp\u003eThe write operation in a 2\u0026times;2 SRAM array involves storing data to the memory cells without any error. The Fig. \u003cspan class=\"InternalRef\"\u003e6\u003c/span\u003e shows the Write and read circuit schematic. The Fig. \u003cspan class=\"InternalRef\"\u003e7\u003c/span\u003e shows transient analysis of write operation respectively. For writing \u0026rdquo;0\u0026rdquo; logic into the SRAM which in turn emphasises the need for stronger access transistors\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e15\u003c/span\u003e\u003c/sup\u003e. Consider a logic \u0026rdquo;0\u0026rdquo; to a cell that has stored a logic.\u0026rdquo;1\u0026rdquo;. The write driver makes BL\u0026thinsp;=\u0026thinsp;0V and BL\u0026rsquo;= VDD as logic \u0026rsquo;0\u0026rsquo; is written into the cell. The write driver circuit provides the required voltage to BL and BL\u0026rsquo; ( For write 0, BL\u0026thinsp;=\u0026thinsp;0, BL\u0026rsquo; = 1 and for write 1, BL\u0026thinsp;=\u0026thinsp;1, BL\u0026rsquo; = 0). Now the address line is enabled by the decoder circuit which makes WL\u0026thinsp;=\u0026thinsp;1. The word line is made high and hence bit lines BL and BL\u0026rsquo; are connected to SRAM cell through the access transistors. The corresponding data is written into the cell ( Q\u0026thinsp;=\u0026thinsp;0 for write logic 0 and Q\u0026thinsp;=\u0026thinsp;1 for write logic 1. Q\u0026rsquo; side of the cell cant be pulled high enough to make the writing of \u0026rsquo;1\u0026rsquo; due to the sizing constraint imposed by the read stability. It makes that voltage is below 0.4V. Hence the new value must be written through the transistor M6. Data \u0026rsquo;0\u0026rsquo; will be written into the cell if node Q is pulled down, below the threshold of M1 to turn it OFF.\u003c/p\u003e\n\u003cp\u003eThe read operation shown in Fig. \u003cspan class=\"InternalRef\"\u003e8\u003c/span\u003e involves retrieving stored data from the memory cells without altering their contents. This process requires coordinated actions from wordlines (WL), bit-lines (BL and BL\u0026macr;), sense amplifiers, and precharge circuits to ensure accurate and efficient data retrieval. Precharging the Bit-lines, before reading the bit lines are precharged to a reference voltage (usually VDD/2 or VDD) using a precharge circuit to ensure a proper voltage difference during sensing16. Activating the Wordline, the row decoder selects the corresponding memory row by enabling the appropriate wordline (WL). This connects the SRAM cell to the bit-lines. Discharging the Bit-lines depending on the stored data (0 or 1), the internal pull-down transistors of the SRAM cell pull one bit-line slightly lower, creating a small voltage difference between BL and BL\u0026macr;. Sensing the Voltage Difference, sense amplifier detects the small voltage difference between BL and BL\u0026macr; and amplifies it to a full logic level (0 or 1).Data Read Successfully, the output of the sense amplifier represents the stored bit, which is then sent to the output buffer.\u003c/p\u003e\n\u003cdiv id=\"Sec8\" class=\"Section2\"\u003e\n \u003ch2\u003e2.2 SRAM cell Stability\u003c/h2\u003e\n \u003cp\u003eStability in an SRAM cell is crucial to ensure data retention, reliable read/write operations, and noise tolerance. It is typically analyzed using Static Noise Margin (SNM) and influenced by various design parameters such as transistor sizing, bit-line capacitance, and supply voltage variations.\u003c/p\u003e\n \u003cul\u003e\n \u003cli\u003e\n \u003cp\u003eStatic Noise Margin (SNM): SNM is the highest noise voltage that can be tolerated by an SRAM cell before flipping its stored value. It is typically measured using butterfly curves by plotting the voltage transfer characteristics (VTC) of the cross-coupled inverters in the SRAM cell\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e16\u003c/span\u003e\u003c/sup\u003e.Higher SNM values indicate better stability.\u003c/p\u003e\n \u003c/li\u003e\n \u003cli\u003e\n \u003cp\u003eRead ,Write and Hold Stability: During a read operation, one bitline remains precharged, while the other begins to discharge. If the access transistor is too strong, it may disturb the stored value, leading to read failure. Increasing cell ratio (CR\u0026thinsp;=\u0026thinsp;Pull-down NMOS/Access NMOS) improves read stability.During a write operation, the bit-lines force the internal node of the SRAM cell to switch. If the pull-up PMOS is too strong, it may resist the switching process, causing a write failure. Increasing pull-up ratio (PR\u0026thinsp;=\u0026thinsp;Access NMOS/Pull-up PMOS) improves write stability.Hold stability in an SRAM 2\u0026times;2 array refers to the capacity of an SRAM cell to retain its stored data when no read or write operations are performed. SNM in hold mode is a key metric used to evaluate the stability of an SRAM cell under process variations, voltage fluctuations, and leakage currents. Key Factors Affecting Hold Stability.In Hold Mode: SNM defines the maximum allowable noise voltage that an SRAM cell can tolerate before its state flips. In hold mode, the wordline (WL) is inactive (0V), isolating the SRAM cell from the bit-lines. The cross-coupled inverters of the SRAM cell must maintain a strong latch behavior to retain stored data.Lowering VDD reduces power consumption but also decreases SNM, making the SRAM more vulnerable to noise and data loss. Higher VDD improves hold stability but increases leakage power\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e17\u003c/span\u003e\u003c/sup\u003e.An optimal trade-off is necessary to balance power and stability. In deep submicron technologies (e.g., 90nm, 45nm), subthreshold leakage and gate leakage can degrade hold stability. Techniques like stack- ing transistors, gated VDD, and reverse body biasing help reduce leakage currents, improving hold stability\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e8\u003c/span\u003e\u003c/sup\u003e.\u003c/p\u003e\n \u003c/li\u003e\n \u003c/ul\u003e\n \u003cdiv class=\"gridtable\"\u003e\n \u003cdiv align=\"\" class=\"colspec\"\u003e\u003cbr\u003e\u003c/div\u003e\u0026nbsp;\u003ctable id=\"Tab1\" border=\"1\"\u003e\n \u003ccaption language=\"En\"\u003e\n \u003cdiv class=\"CaptionNumber\"\u003eTable 1\u003c/div\u003e\n \u003cdiv class=\"CaptionContent\"\u003e\n \u003cp\u003eComparison between 6T and 10T SRAM Cells with and without Stacking\u003c/p\u003e\n \u003c/div\u003e\n \u003c/caption\u003e\n \u003cthead\u003e\n \u003ctr\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eFeatures\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e6 Transistors\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eStacked 6 Transistors\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e10 Transistors\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eStacked 10 Transistors\u003c/p\u003e\n \u003c/th\u003e\n \u003c/tr\u003e\n \u003c/thead\u003e\n \u003ctbody\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003ewrite SNM(mV)\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e390\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e425\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e510\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e584\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eRead stability analysis(mV)\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e249\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e324\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e102\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e167\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eSNM(mV)\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e255.2\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e319.6\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e263\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e298\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eDelay(ns)\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e536\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e475\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e98\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e35\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eTotal Power(\u003cem\u003e\u0026micro;W\u003c/em\u003e )\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e147.6\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e83.64\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e190.1\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e161.9\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003c/tbody\u003e\n \u003c/table\u003e\n \u003c/div\u003e\n \u003cp\u003eTable \u003cspan class=\"InternalRef\"\u003e1\u003c/span\u003e shows the comparison between 6T and 10T SRAM cells with and without stacking in CMOS 90nm technology with a supply voltage of 1.8V. It can be inferred that stacked SRAM cells significantly enhance energy efficiency by reducing leakage currents. Compared to 6T SRAM cells, 10T SRAM cells provide better noise margins and faster access time.\u003c/p\u003e\n\u003c/div\u003e\n\u003ch3\u003e2.3 Writer Driver Circuit Analysis\u003c/h3\u003e\n\u003cp\u003eThe write driver circuit to ensuring efficient and reliable data writing to the memory cells shown in Fig.\u0026nbsp;\u003cspan class=\"InternalRef\"\u003e9\u003c/span\u003e and its transient analysis is shown in Fig.\u0026nbsp;\u003cspan class=\"InternalRef\"\u003e10\u003c/span\u003e. It is responsible for driving the bit-lines to the required voltage levels during a write operation while ensuring minimal power dissipation and delay\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e18\u003c/span\u003e\u003c/sup\u003e. Proper design of the write driver enhances the write stability and speed, which are essential for high-performance SRAM arrays. Function of the Write Driver Circuit forces the Bit-Lines to Desired Values. The write driver pulls one bit-line to VDD and the other to GND to ensure successful data storage in the SRAM cell. The SRAM cell is a cross-coupled inverter structure, which inherently holds its previous state. The write driver must be strong enough to override the existing stored value without excessive power consumption\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e19\u003c/span\u003e\u003c/sup\u003e. The duration for which the wordline (WL) is activated determines the success of the write operation. The write driver must deliver enough current within this period to ensure data is reliably stored.\u003c/p\u003e\n\u003ch3\u003e2.4 Precharge Circuit Analysis\u003c/h3\u003e\n\u003cp\u003eThe precharge circuit (PCH) is shown in Fig.\u0026nbsp;\u003cspan class=\"InternalRef\"\u003e11\u003c/span\u003e used to ensure that the bit-lines are precharged to stable voltage before every read or write operation\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e20\u003c/span\u003e\u003c/sup\u003e. In a 2\u0026times;2 SRAM array, the PCH circuit plays a crucial role in maintaining low power consumption, reducing access time, improving read stability.Uncontrolled bit- line fluctuations lead to unnecessary power dissipation. The PCH circuit reduces dynamic power loss by minimizing bit- line voltage swings. Variations in bit-line voltages can lead to incorrect reads or slower sensing. The precharge circuit equalizes BL and BL\u0026macr; to prevent bias during operations\u003csup\u003e\u003cstrong\u003e?\u003c/strong\u003e\u003c/sup\u003e.\u003c/p\u003e\n\u003cdiv id=\"Sec11\" class=\"Section2\"\u003e\n \u003ch2\u003e2.5 Sense Amplifier Analysis\u003c/h2\u003e\n \u003cp\u003eTable \u003cspan class=\"InternalRef\"\u003e2\u003c/span\u003e presents a comparative analysis of three types of sense amplifiers: Differential Sense Amplifier, Basic Latched Sense Amplifier, and Basic Sense Amplifier. The parameters considered include the supply voltage, the number of transistors used,\u003c/p\u003e\n \u003cp\u003e\u003c/p\u003e\n \u003ctable id=\"Tab2\" border=\"1\"\u003e\n \u003ccaption language=\"En\"\u003e\n \u003cdiv class=\"CaptionNumber\"\u003eTable 2\u003c/div\u003e\n \u003cdiv class=\"CaptionContent\"\u003e\n \u003cp\u003eAverage Power Consumption of Sense Amplifiers\u003c/p\u003e\n \u003c/div\u003e\n \u003c/caption\u003e\n \u003cthead\u003e\n \u003ctr\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eSense Amplifier Design Type\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eNumber of transistors\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eAverage Power Consumption in mWatts\u003c/p\u003e\n \u003c/th\u003e\n \u003c/tr\u003e\n \u003c/thead\u003e\n \u003ctbody\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eDifferential Sense Amplifier\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e4\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e179.94\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eBasic Latched Sense Amplifier\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e6\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e80.713\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eBasic Sense Amplifier\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e5\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e80 mW\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003c/tbody\u003e\n \u003c/table\u003e\n \u003cp\u003e\u003c/p\u003e\n \u003cp\u003eand the average power consumption. The Differential Sense Amplifier exhibits the highest power consumption of 179.94 mW, as it requires four transistors. Despite its higher power usage, it provides superior signal amplification and noise immunity, making it an optimal choice for high- performance SRAM designs\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e21\u003c/span\u003e\u003c/sup\u003e. The Basic Latched Sense Amplifier, using six transistors, achieves a balance between power consumption (80.713 mW) and signal amplification, benefiting from latching mechanisms that enhance stability. The Basic Sense Amplifier consumes the least power (80 mW) while requiring five transistors. However, it may not provide the same noise immunity and speed as the differential design.\u003c/p\u003e\n \u003cp\u003eThe transient analysis graph shown in Fig. \u003cspan class=\"InternalRef\"\u003e12\u003c/span\u003e,represents the sensing operation of a 2\u0026times;2 SRAM array\u0026rsquo;s sense amplifier, showing how it detects and amplifies a small voltage difference between bitlines.The voltage remains stable at approximately 1.46V, indicating that the bitlines are precharged to a high voltage level before the sensing operation begins\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e22\u003c/span\u003e\u003c/sup\u003e. This precharged state ensures that the sense amplifier can quickly detect small differences in voltage when a read operation occurs. At around\u003c/p\u003e\n \u003cp\u003e6.25 ns, the voltage begins to decrease, marking the activation of the sense amplifier. The circuit took 250 ps to sense a 200 mV difference, indicating that the sense amplifier successfully detected the stored bit in one of the SRAM cells. This transition occurs due to the slight difference in bitline voltages, which the sense amplifier amplifies rapidly. After the sensing phase, the voltage drops exponentially as the sense amplifier fully resolves the bitline difference and drives the output to a stable logic level. This behavior reflects the discharging of bitlines through the sense amplifier circuitry.\u003c/p\u003e\n\u003c/div\u003e"},{"header":"Conclusion","content":"\u003cp\u003eThe proposed 2\u0026times;2 SRAM architecture demonstrates notable advancements in power efficiency, speed, and reliability, positioning it as a promising candidate for contemporary low-power, high-performance applications including IoT devices, mobile processors, and embedded systems. Through comparative analysis of 6T, 8T, and 10T SRAM cells\u0026mdash;with and without transistor stacking\u0026mdash;the 10T cell with stacking was selected for integration due to its superior stability and reduced power consumption. The implemented 10T SRAM cell effectively minimizes leakage power, contributing to a total power consumption of 200 \u0026micro;W for the complete architecture. The design also exhibits high-speed read operations, achieving a sensing delay of 250 ps for a 200 mV input.\u003c/p\u003e \u003cp\u003eFurthermore, the architecture ensures robust operational stability, demonstrated by a read static noise margin (RSNM) of 167 mV and a write static noise margin (WSNM) of 584 mV. Future work may explore optimization using advanced device technologies such as FinFETs or Gate-All-Around FETs to further enhance leakage reduction and scalability.\u003c/p\u003e"},{"header":"Declarations","content":"\u003ch2\u003eAdditional information\u003c/h2\u003e\n\u003cp\u003eThe authors declare no conflict of interest.\u003c/p\u003e\n\u003ch2\u003eFunding Declaration\u003c/h2\u003e\n\u003cp\u003eNo Funding Received.\u003c/p\u003e\n\u003ch2\u003eAuthor Contribution\u003c/h2\u003e\n\u003cp\u003eS. Mahammad Aadil, M. Bhargava Rama, and K. S. S. Yashwant are B.Tech students who conducted research on this topic. P. Latha is the corresponding author who supervised the work and guided the drafting of this journal article\u003c/p\u003e\n\u003ch2\u003eAcknowledgement\u003c/h2\u003e\n\u003cp\u003eThe authors gratefully acknowledge Vellore Institute of Technology ,Chennai for providing the necessary facilities and support to carry out this research work\u003c/p\u003e\n\u003ch2\u003eData Availability\u003c/h2\u003e\n\u003cp\u003eNo datasets were generated or analysed during the current study.\u003c/p\u003e"},{"header":"References","content":"\u003col\u003e\n\u003cli\u003eRao, S., Bhat, M., Anchan, P. G., Shetty, N. \u0026amp; Rodrigues, L. M. 8\u003cem\u003e\u0026times; \u003c/em\u003e8 sram cell array for low-power applications. In \u003cem\u003e2024 International Conference on Innovation and Novelty in Engineering and Technology (INNOVA)\u003c/em\u003e, vol. 1, 1\u0026ndash;6 (IEEE, 2024).\u003c/li\u003e\n\u003cli\u003eLiu, Z. \u0026amp; Kursun, V. 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The impact of random device variation on sram cell stability in sub-90-nm cmos technologies. \u003cem\u003eIEEE Transactions on Very Large Scale Integration (VLSI) Syst. \u003c/em\u003e\u003cstrong\u003e16\u003c/strong\u003e, 86\u0026ndash;97 (2007).\u003c/li\u003e\n\u003c/ol\u003e"}],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":true,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":true,"highlight":"","institution":"","isAcceptedByJournal":false,"isAuthorSuppliedPdf":false,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":false,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"SRAM, CMOS, Sense Amplifier, Noise Margin, Stability","lastPublishedDoi":"10.21203/rs.3.rs-6625510/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-6625510/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eThis paper presents the design and comprehensive analysis of a low-power 2X2 SRAM array using CMOS 90nm technology. The proposed system is targeting energy constrained applications such as mobile and embedded systems. The implemented SRAM architecture incorporates a 10T with stacking cell, optimized word line and bit line schemes, and efficient row and column decoders. Robust read and write functionalities are ensured through the integration of precharge circuits, a differential sense amplifier, and write drivers. To minimize power dissipation, transistor stacking techniques are strategically employed within the memory array. The performance of the designed SRAM is rigorously evaluated through simulations using Cadence Virtuoso and Spectre, focusing on critical parameters including hold stability, read stability, write margin, and power consumption. The simulation results demonstrate significant enhancements in power efficiency, read access time, and noise immunity, highlighting the suitability of this SRAM design for energy-efficient systems.\u003c/p\u003e","manuscriptTitle":"Design of stable low leakage Power Optimized SRAM Array","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2025-06-12 10:42:10","doi":"10.21203/rs.3.rs-6625510/v1","editorialEvents":[{"type":"communityComments","content":0}],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true}}],"origin":"","ownerIdentity":"d4730a92-a9d0-4314-b861-90e3a1b8d89d","owner":[],"postedDate":"June 12th, 2025","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"posted","subjectAreas":[{"id":49903670,"name":"Physical sciences/Engineering/Electrical and electronic engineering"},{"id":49903671,"name":"Physical sciences/Energy science and technology/Energy storage"}],"tags":[],"updatedAt":"2025-06-23T08:54:13+00:00","versionOfRecord":[],"versionCreatedAt":"2025-06-12 10:42:10","video":"","vorDoi":"","vorDoiUrl":"","workflowStages":[]},"version":"v1","identity":"rs-6625510","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-6625510","identity":"rs-6625510","version":["v1"]},"buildId":"8U1c8b4HqxoKbykW_rLl7","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}