The Spike Processing Unit (SPU): An IIR Filter Approach to Hardware-Efficient Spiking Neurons

This paper introduces the Spike Processing Unit (SPU), a novel digital spiking neuron model engineered for ultra-efficient hardware implementation. Departing from biologically-plausible models, the SPU prioritizes computational performance by leveraging a discrete-time Infinite Impulse Response (IIR) filter with a key innovation: its coefficients are constrained to powers of two. This design eliminates the need for power-hungry digital multipliers, replacing them with simple bit-shift operations. Information is encoded using the inter-spike interval (ISI) format, which decouples signal representation from numerical precision. This allows the model to operate efficiently with low-precision 6-bit two’s complement integers without introducing representation errors. The model’s functionality is demonstrated through a temporal pattern discrimination task, where a single SPU is trained via a genetic algorithm to distinguish between specific input patterns and suppress noise, generating output spikes at distinct times. This proof-of-concept, validated in Python simulation, confirms the model’s core operational principle. The proposed approach provides a scalable and multiplier-free framework for Spiking Neural Networks, contributing to the advancement of energy-efficient neuromorphic computing.