Advanced Encryption Standard algorithm for Power-Efficient and High-Speed applications

Abstract To implement Advanced Encryption Standard Algorithm that is efficient in terms of its speed, area and power consumption is the major objective of this paper. In the four stages of AES operation, SubByte stage consumes more area, time and power on comparing with the other stages. To design an efficient AES, it is necessary to design an efficient SubByte stage for AES encryption and decryption process. In this research, a modified version of the SubByte stage is proposed and the results are compared with the SubByte stage proposed by Rijndael. Propagation delay, Area and Power Consumption of the proposed architecture are calculated in this research article. This proposed AES structure is implemented in FPGAs Virtex 6 and Spartan 6. Implementation result shows the improvement in Speed, Area and Power Consumption of the proposed architecture than the conventional architecture.