High-Speed SHDAC Design for Hybrid ADCs by Integrating 3-bit Flash and 8-bit Sigma-Delta for Improved Resolution

High-Speed SHDAC Design for Hybrid ADCs by Integrating 3-bit Flash and 8-bit Sigma-Delta for Improved Resolution | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article High-Speed SHDAC Design for Hybrid ADCs by Integrating 3-bit Flash and 8-bit Sigma-Delta for Improved Resolution Tadigiri Aruna, Ravi Sekhar Yarrabothu This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-5956935/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract In the realm of rapid analog-to-digital conversion, it is not without its challenges to accomplish both high resolution and high sample rates to a satisfactory degree. The purpose of this work is to introduce a novel approach that involves combining a 3-bit Flash analog-to-digital converter (ADC) with an 8-bit Sigma-delta (ΣΔ) ADC. The overall goal of the proposed work is to develop a High-Speed and Sample Hold-Digital-Analog Converter (SHDAC), which can operate on different voltage sampled ranges from 4 to 32 scales and generate sample frequencies ranging from 3 giga-samples per second (Gsps) to 14 Gsps. The collaborative approach to two types of ADCs heavily relies on the 3-bit Flash ADC for high-speed designs with rapid conversion rates, and the 8-bit Sigma-Delta ADC for oversampling and enhanced resolution features with reduced noise compatibility. By combining these two methods, the SHDAC is able to achieve a balance between speed and resolution, which is suitable for tasks that need a high level of digital communication and signal processing. The implementation of a digital scaling mechanism that dynamically alters the SHDAC's bit resolution based on the specified scalar, which may be 4, 8, 16, or 32 bits from the beginning, is the key to the design. This versatility enables the SHDAC to meet the requirements of a wide variety of applications, ranging from lower resolution images with faster sampling to higher resolution images with slower sampling. The proposed work with SHDAC implements a novel technique with an integrated design based on a front-end model with Verilog, which provides high-precise functionality of the ADC's with better scalability and adaptability, indicating the efficient power and sampling rates achieved from 3–14 Gbps and a power of 0.01 dynamic power for the SHDAC design, as verified in the Vivado tool. SHDAC Parasitic capacitance SNDR ENOB Full Text Additional Declarations No competing interests reported. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-5956935","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":411892430,"identity":"fb1874c9-fc0f-453b-985f-b69a8e2834c9","order_by":0,"name":"Tadigiri Aruna","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAAA/ElEQVRIiWNgGAWjYHACgwMMBgw8UI4NEDM2HsCnngdNSxpISwNBLcj8w2ASrxZ79sMbD34puCfDwH72mXRBzXm7te2HgbbU2ETjtIUnreCwjEExDwNPupn0jGO3k7edSQRqOZaW24DTYTkGhyUMEoAOTGOT5mG7nWx2AKiFseEwbi38b6Ba+J8Btfw7l2x2/iEBLRI5Bgc/gLRIAG3hbTtgZ3aDkC03nhUcZgBqYZN4xmzN25ecYHYDaEsCHr+w9ydv/vjjT4I9P38a422eb3b2ZufTHz74UGODUwsIMIPikQ3KSQSrTMCjHAQYfyBx7AkoHgWjYBSMghEIALHPWcPR6SFyAAAAAElFTkSuQmCC","orcid":"","institution":"Vignan’s Foundation for Science, Technology \u0026 Research","correspondingAuthor":true,"prefix":"","firstName":"Tadigiri","middleName":"","lastName":"Aruna","suffix":""},{"id":411892431,"identity":"7cef0d4a-491e-4362-b905-78f51f503bbd","order_by":1,"name":"Ravi Sekhar Yarrabothu","email":"","orcid":"","institution":"Vignan’s Foundation for Science, Technology \u0026 Research","correspondingAuthor":false,"prefix":"","firstName":"Ravi","middleName":"Sekhar","lastName":"Yarrabothu","suffix":""}],"badges":[],"createdAt":"2025-02-04 09:53:39","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-5956935/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-5956935/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":78746963,"identity":"c362b390-62f2-46c0-98c5-ca02826984ea","added_by":"auto","created_at":"2025-03-18 10:47:20","extension":"pdf","order_by":1,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":973597,"visible":true,"origin":"","legend":"","description":"","filename":"journalforAnalogintegratedcircuitsCopy.pdf","url":"https://assets-eu.researchsquare.com/files/rs-5956935/v1_covered_fddde61f-1159-42f8-9fc1-93301b5fd098.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"High-Speed SHDAC Design for Hybrid ADCs by Integrating 3-bit Flash and 8-bit Sigma-Delta for Improved Resolution","fulltext":[],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":false,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":true,"highlight":"","institution":"","isAcceptedByJournal":false,"isAuthorSuppliedPdf":true,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":true,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"SHDAC, Parasitic capacitance, SNDR, ENOB","lastPublishedDoi":"10.21203/rs.3.rs-5956935/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-5956935/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eIn the realm of rapid analog-to-digital conversion, it is not without its challenges to accomplish both high resolution and high sample rates to a satisfactory degree. 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