Performance Assessments of Gate Engineered Dopingless Schottky Tunnel MOSFET in presence of Interfacial Trap Charges

Abstract The most notable accumulation of trap charges occurs on the oxide/semiconductor interface of MOS devices and it degrades the device's performance and reliability. In this literature, we proposed a gate-engineered Schottky tunneling MOSFET(GE-ST-MOSFET) for ON state performance improvement, and a detailed analysis of the effects of interface trap charges (ITCs) on the DC characteristics and analog/RF performance metrics have been analyzed. In this device, the electrostatically doping-based dopant segregation layer (DSL) is introduced at the source side in the channel end by the Tunneling Gate (TG). A comparative study between the proposed GE-ST-MOSFET and conventional Schottky tunneling MOSFET(ST-MOSFET) has been carried out in presence of interface trap charges at the HfO2/Si interface. A significant improvement in ION and ION/IOFF ratio has been achieved 563× and 1472× respectively in the GE-ST-MOSFET in comparison with the ST-MOSFET. To analyze the linearity behavior, higher order transconductance parameters are also studied considering the effect of ITCs. Furthermore, the circuit level performances of both devices are analyzed using the Verilog-A based models. The effect of OFF current variation on switching performance has been investigated. It has been found that the average switching delay and Power Delay Product (PDP) have improved by 97% and 81% respectively in comparison to the conventional device-based inverter. The GE-ST-MOSFET-based circuit also shows better immunity to interface trap charges. In addition, the implementation of the electrostatically doping concept for the proposed device could make fabrication very simple.