A High Throughput Parallel Hash Table on FPGA using Reversible XOR-based Memory

Abstract A hash table is a basic data structure for searching and retrieving data quickly. It's an important part of Artificial Intelligence (AI)/Machine Learning (ML) applications and advanced graph analytics. An effective hash function can make hashing effective. Existing hash table implementations either simplify the underlying model by supporting only a subset of hash table operations or use optimizations that result in highly data-dependent performance and, at worst, comparable to a sequential implementation of the problem. A dynamic hash table that supports all hash table queries—search, insert, delete, and update—while also allowing us to provide p parallel queries (p > 1) per clock cycle using p processing engines (PEs) in the worst-case, i.e., data agnostic performance. Our design is scalable up to 128PEs and supports throughput of up to 8000 Million Operations per Second (MOPS) at 325 MHz using state-of-the-art FPGAs. It supports the same set of operations as the hash table and achieves speeds up to 42.1× speedup. Using RXOR-based parallel hash tables, we achieve high throughput, low latency, and low power consumption.