Design and Analysis of Multi-Level Voltage Generator for NAND Flash Operations Using a reference voltage Controlled Charge Pump

Design and Analysis of Multi-Level Voltage Generator for NAND Flash Operations Using a reference voltage Controlled Charge Pump | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Design and Analysis of Multi-Level Voltage Generator for NAND Flash Operations Using a reference voltage Controlled Charge Pump Jamuna.S, Aditya Kiran Pawaskar, Kishore Kumar K This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-6867812/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract Efficient and precise voltage control must be pro- vided to ensure the reliable operation of memory cells. This paper presents a circuit for the generation and control of high voltage, specifically targeted for NAND Flash memory applica- tions. NAND Flash memory is a form of non-volatile memory where data is stored in a matrix of memory cells consisting of floating-gate transistors. Its widespread adoption in embedded systems, solid-state drives, and portable storage is attributed to its high density and rapid access speed. NAND Flash operation needs precise voltage levels in various operating modes: high voltages are required for erase and programming operations, while moderate voltages are required for reading operations. To achieve this, a dual-phase clocking scheme is coordinated with a voltage reference divider and a feedback comparator to dynamically regulate the output based on the selected memory mode. A positive level shifter converts low-voltage control signals to high-voltage levels necessary for word-line and bit-line control of NAND arrays. The proposed charge pump, integrated with a configurable reference voltage generator and operating with a 20pF load, eliminates the need for multiple taps or stage-specific control signals. It generates target voltages of 19V for erase, 15V for program (write), and 5V for read operations. In the absence of regulation, it achieves up to 26V with an efficiency of 72% and a peak-to-peak ripple of 0 mV. Electrical Engineering NAND Flash memory high voltage generation charge pump program/erase/read voltage voltage regulation level shifter Full Text Additional Declarations The authors declare no competing interests. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. 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Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-6867812","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":469558338,"identity":"2b3f19f7-6955-4e36-8a6a-0585303b812a","order_by":0,"name":"Jamuna.S","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAABN0lEQVRIiWNgGAWjYBACxgY4k/mABJRlABeTYMAESFrYEojTggR4DIjTwtx+Ok26oIZBjr+95+ONn212efyzmzd+/FFTK2/ewHzwNg8Wh/XkbpOecYzBWOLM2c2WvW3JxRJ3jhVL8xw7bjjnAFuyNTYtDUAtPGz/EzdI5G6T4G1jTmy4kWMgzcB2jHEGA4+ZNDYt/W+BWv4x1G+Qf/NM8m9bfeL8GznGP3/8O2Y/g4H/G1YtM4C28LYxJBhI8LABGYcTN9zIMQNaV5MItIUNu5a3m615+xgMZ5xJM7aWOXc8ceONtDKgyIHkGcxsxpZzMLUY9uduvM3zjUGev/3ww5tvyqoT591I3nzzx7c62xnszQ9vvMGipQHFTjY48zAwAjCVg4A8KvcPnFWHXf0oGAWjYBSMRAAAPLZoqgvDuWYAAAAASUVORK5CYII=","orcid":"https://orcid.org/0000-0002-6564-1883","institution":"Dayananda Sagar College of Engineering","correspondingAuthor":true,"prefix":"","firstName":"","middleName":"","lastName":"Jamuna.S","suffix":""},{"id":469558339,"identity":"d7cdb392-2ce0-4675-be9b-263a896fa3d5","order_by":1,"name":"Aditya Kiran Pawaskar","email":"","orcid":"","institution":"Dayananda Sagar College of Engineering","correspondingAuthor":false,"prefix":"","firstName":"Aditya","middleName":"Kiran","lastName":"Pawaskar","suffix":""},{"id":469558340,"identity":"e0e414c6-164c-4343-8fd3-6c5969882dd1","order_by":2,"name":"Kishore Kumar K","email":"","orcid":"","institution":"Dayananda Sagar College of Engineering","correspondingAuthor":false,"prefix":"","firstName":"Kishore","middleName":"Kumar","lastName":"K","suffix":""}],"badges":[],"createdAt":"2025-06-11 04:38:54","currentVersionCode":1,"declarations":{"humanSubjects":false,"vertebrateSubjects":false,"conflictsOfInterestStatement":false,"humanSubjectEthicalGuidelines":false,"humanSubjectConsent":false,"humanSubjectClinicalTrial":false,"humanSubjectCaseReport":false,"vertebrateSubjectEthicalGuidelines":false},"doi":"10.21203/rs.3.rs-6867812/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-6867812/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":84403754,"identity":"1756606b-a42f-415f-9d26-1de4e4bb7854","added_by":"auto","created_at":"2025-06-11 14:01:08","extension":"pdf","order_by":1,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":613025,"visible":true,"origin":"","legend":"","description":"","filename":"xktqzwbqfswbmmgbhbhfmpknbpzvnttd.pdf","url":"https://assets-eu.researchsquare.com/files/rs-6867812/v1_covered_9fb3dffe-f874-469d-8df3-5f99afecdb64.pdf"}],"financialInterests":"The authors declare no competing interests.","formattedTitle":"\u003cp\u003eDesign and Analysis of Multi-Level Voltage Generator for NAND Flash Operations Using a reference voltage Controlled Charge Pump\u003c/p\u003e","fulltext":[],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":false,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":true,"hideJournal":true,"highlight":"","institution":"","isAcceptedByJournal":false,"isAuthorSuppliedPdf":true,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":true,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"NAND Flash memory, high voltage generation, charge pump, program/erase/read voltage, voltage regulation, level shifter","lastPublishedDoi":"10.21203/rs.3.rs-6867812/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-6867812/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003e\u003cstrong\u003eEfficient and precise voltage control must be pro- vided to ensure the reliable operation of memory cells. This paper presents a circuit for the generation and control of high voltage, specifically targeted for NAND Flash memory applica- tions. NAND Flash memory is a form of non-volatile memory where data is stored in a matrix of memory cells consisting of floating-gate transistors. Its widespread adoption in embedded systems, solid-state drives, and portable storage is attributed to its high density and rapid access speed. NAND Flash operation needs precise voltage levels in various operating modes: high voltages are required for erase and programming operations, while moderate voltages are required for reading operations. To achieve this, a dual-phase clocking scheme is coordinated with a voltage reference divider and a feedback comparator to dynamically regulate the output based on the selected memory mode. A positive level shifter converts low-voltage control signals to high-voltage levels necessary for word-line and bit-line control of NAND arrays. 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