Dynamic Key Generation With LSTM: A Robust Defence Against DPA Attacks on FPGA-based AES Cryptosystems

Dynamic Key Generation With LSTM: A Robust Defence Against DPA Attacks on FPGA-based AES Cryptosystems | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Article Dynamic Key Generation With LSTM: A Robust Defence Against DPA Attacks on FPGA-based AES Cryptosystems Khalil M. Abdelnaby, Mohammed A. F. Al-Husainy, Mohammad O. Alhawarat, and 2 more This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-9006459/v1 This work is licensed under a CC BY 4.0 License Status: Under Review Version 1 posted 9 You are reading this latest preprint version Abstract This research presents a new, hardware-efficient cryptosystem that integrates a Long Short-Term Memory (LSTM) network with the Advanced Encryption Standard (AES) on an FPGA to create a strong first line of defense against Differential Power Analysis (DPA) attacks. The key innovation is a dynamic key generation scheme that uses an on-chip NIOS II processor to run a pre-trained LSTM model to create non-deterministic, session-specific round keys in real-time, breaking the statistical relationships that side-channel attackers exploit to create their attacks. The system is implemented in a Cyclone IV DE2-115 FPGA, and was thoroughly tested using functional simulation and physical synthesis. The architecture has an impressive throughput of 989.94 Mbps, at a maximum clock speed of 400.198 MHz, indicating that it is possible to have a high level of security without sacrificing performance. The comprehensive side-channel analysis, including correlation power analysis and Test Vector Leakage Assessment (TVLA) t-tests, has validated that there is nothing that can be used to create DPA attacks, showing that there was no usable leakage of data after > 100,000 power traces were recorded. The consumption of 12.5% of slice registers and 14.5% of LUTs, although a burden for the design to include the neural key scheduler and soft-core processor, is justified, and the dynamic power consumption of the design is only 0.5 mW. Thus, this work provides a new direction for designing DPA-resistant cryptographic accelerators, proving that the use of machine learning-generated dynamic keys can significantly increase the security of these systems. Physical sciences/Energy science and technology Physical sciences/Engineering Physical sciences/Mathematics and computing FPGA Smart grids Dynamic Key generation AES data encryption LSTM network Cryptographic Accelerator Side-Channel Attacks DPA attacks Plain text Cipher text Full Text Additional Declarations No competing interests reported. Cite Share Download PDF Status: Under Review Version 1 posted Reviews received at journal 29 Mar, 2026 Reviews received at journal 28 Mar, 2026 Reviewers agreed at journal 20 Mar, 2026 Reviewers agreed at journal 10 Mar, 2026 Reviewers invited by journal 05 Mar, 2026 Editor invited by journal 05 Mar, 2026 Editor assigned by journal 03 Mar, 2026 Submission checks completed at journal 03 Mar, 2026 First submitted to journal 02 Mar, 2026 You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-9006459","acceptedTermsAndConditions":true,"allowDirectSubmit":false,"archivedVersions":[],"articleType":"Article","associatedPublications":[],"authors":[{"id":602523924,"identity":"7f54c6e2-18ab-459e-8aa1-62d58a3df93e","order_by":0,"name":"Khalil M. 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The key innovation is a dynamic key generation scheme that uses an on-chip NIOS II processor to run a pre-trained LSTM model to create non-deterministic, session-specific round keys in real-time, breaking the statistical relationships that side-channel attackers exploit to create their attacks. The system is implemented in a Cyclone IV DE2-115 FPGA, and was thoroughly tested using functional simulation and physical synthesis. The architecture has an impressive throughput of 989.94 Mbps, at a maximum clock speed of 400.198 MHz, indicating that it is possible to have a high level of security without sacrificing performance. The comprehensive side-channel analysis, including correlation power analysis and Test Vector Leakage Assessment (TVLA) t-tests, has validated that there is nothing that can be used to create DPA attacks, showing that there was no usable leakage of data after \u0026gt;\u0026thinsp;100,000 power traces were recorded. The consumption of 12.5% of slice registers and 14.5% of LUTs, although a burden for the design to include the neural key scheduler and soft-core processor, is justified, and the dynamic power consumption of the design is only 0.5 mW. Thus, this work provides a new direction for designing DPA-resistant cryptographic accelerators, proving that the use of machine learning-generated dynamic keys can significantly increase the security of these systems.\u003c/p\u003e","manuscriptTitle":"Dynamic Key Generation With LSTM: A Robust Defence Against DPA Attacks on FPGA-based AES Cryptosystems","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2026-03-10 12:12:51","doi":"10.21203/rs.3.rs-9006459/v1","editorialEvents":[{"type":"communityComments","content":0},{"type":"editorInvitedReview","content":"","date":"2026-03-29T22:07:32+00:00","index":"hide","fulltext":""},{"type":"editorInvitedReview","content":"","date":"2026-03-29T01:21:14+00:00","index":"hide","fulltext":""},{"type":"reviewerAgreed","content":"113983021561310311368415947786859293679","date":"2026-03-20T22:21:49+00:00","index":"hide","fulltext":""},{"type":"reviewerAgreed","content":"160046683195206574662410800598597496003","date":"2026-03-10T13:23:57+00:00","index":"hide","fulltext":""},{"type":"reviewersInvited","content":"","date":"2026-03-05T12:49:30+00:00","index":"","fulltext":""},{"type":"editorInvited","content":"","date":"2026-03-05T10:42:48+00:00","index":"","fulltext":""},{"type":"editorAssigned","content":"","date":"2026-03-04T01:32:49+00:00","index":"","fulltext":""},{"type":"checksComplete","content":"","date":"2026-03-04T01:30:38+00:00","index":"","fulltext":""},{"type":"submitted","content":"Scientific Reports","date":"2026-03-02T06:33:50+00:00","index":"","fulltext":""}],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"scientific-reports","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":false,"externalIdentity":"scirep","sideBox":"Learn more about [Scientific Reports](http://www.nature.com/srep/)","snPcode":"","submissionUrl":"","title":"Scientific Reports","twitterHandle":"","acdcEnabled":true,"dfaEnabled":true,"editorialSystem":"stoa","reportingPortfolio":"Scientific Reports","inReviewEnabled":true,"inReviewRevisionsEnabled":true}}],"origin":"","ownerIdentity":"96648027-1cf2-496d-b08a-cc11be814949","owner":[],"postedDate":"March 10th, 2026","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"under-review","subjectAreas":[{"id":64247795,"name":"Physical sciences/Energy science and technology"},{"id":64247796,"name":"Physical sciences/Engineering"},{"id":64247797,"name":"Physical sciences/Mathematics and computing"}],"tags":[],"updatedAt":"2026-03-10T12:12:51+00:00","versionOfRecord":[],"versionCreatedAt":"2026-03-10 12:12:51","video":"","vorDoi":"","vorDoiUrl":"","workflowStages":[]},"version":"v1","identity":"rs-9006459","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-9006459","identity":"rs-9006459","version":["v1"]},"buildId":"XKTyCvWXoU3ODBz1xrDgd","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}