The performance of LaAlO x gate dielectric films prepared by sol-gel method at different temperatures of annealing

The performance of LaAlO x gate dielectric films prepared by sol-gel method at different temperatures of annealing | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article The performance of LaAlO x gate dielectric films prepared by sol-gel method at different temperatures of annealing Zhenhua Huang, Kamale Tuokedaerhan, Linyu Yang, Chaozhong Guo, and 3 more This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-4984081/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract In recent years, there has been growing interest in the exploration of rare earth oxides for their potential as high-k gate dielectrics. Lanthanum oxide (La 2 O 3 ) has emerged as a particularly noteworthy candidate due to its impressive dielectric properties, wide bandgap, strong thermodynamic stability, and remarkable compatibility with silicon substrates. However, La 2 O 3 has a significant problem for MOS device applications due to its hygroscopicity and low crystallization temperature, making it unsuitable for high-temperature treatment during fabrication. To improve its oxide quality, it can be doped. Al-doped La 2 O 3 (LaAlO x ) thin films annealed at different temperatures were prepared on n-type Si substrates by sol-gel method and the effect of temperature variation on LaAlOx thin films as gate dielectrics were investigated in terms of root-mean-square, interfacial properties, and electrical properties. The findings indicate that the introduction of Al doping raises the crystallization temperature of La 2 O 3 . Additionally, it was observed that the root-mean-square roughness of the LaAlOx films decreases from 0.919 nm to 0.320 nm with an increase in annealing temperature from 500 to 700°C. XPS has the capability to assess the interfacial characteristics of LaAlO x . It is evident that elevated temperatures promote the formation of M-O bonds, diminish film defects, and enhance the overall interfacial quality of the film. In addition, analyzed the electrical properties of the Al/ LaAlO x /Si/Al metal-oxide-semiconductor capacitors The findings indicate that the samples annealed at 700°C exhibit favorable electrical characteristics, demonstrating a dielectric constant of 20.91 under a gate voltage of 1 V and a leakage current density of 3.54×10 − 3 A/cm 2 . La2O3 sol-gel method gate dielectric thin films MOS capacitors Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Highlights Prepared LaAlO x thin films by sol-gel method and the effects of different annealing temperatures on the interface structure of the films were analyzed by XRD、AFM、XPS and so on. Fabraicated the Al/LaAlO x /Si/Al metal-oxide-semiconductor capacitors by RF magnetron sputtering, and the effects of different annealing temperatures on the electrical properties. Annealed at 700 ℃, the RMS of the LaAlO x film reaches a minimum of 0.320 nm and the content of M-O bond is higher. The lowest leakage current density of 3.54×10 -3 A/cm 2 is also reached at 700 °C. 1 Introduction Metal Oxide Semiconductor Field Effect Transistors (MOSFETS) are one of the core components of integrated circuits (ICs) because of their small size, high efficiency and low power consumption [ 1 , 2 ]. It acts as a switch or amplifier in electronic devices, making digital logic operations possible. Advances in MOSFET technology have driven miniaturization and performance improvements in ICs, which have driven the development of robust and efficient electronic devices. Almost all electronic devices, from microprocessors to memory chips, use MOSFETs in ICs [ 3 – 5 ]. However, with the ongoing reduction in the size of MOSFETs, it becomes necessary to decrease the thickness of traditional silicon oxide (SiO₂) used as a gate dielectric in order to uphold adequate gate capacitance due to its low dielectric constant [ 6 – 8 ]. However, the thickness of SiO 2 gate medium can not be too thin. When the thickness of SiO 2 gate dielectric decreases to a certain value, the leakage current increases dramatically, and the performance of MOS devices deteriorates or even breakdown [ 9 , 10 ]. Therefore, finding a material with a higher dielectric constant was necessary to replace the traditional SiO 2 . In 2007, at the 45-nm technology node, Intel Corporation was the first to realize the use of HfO₂, a material with superior dielectric properties and exceptional stability, to replace SiO₂ as the gate dielectric material[ 2 , 10 ]. However, although HfO 2 has been applied in practice, there is a need to explore alternative high-k materials to replace it due to its evident limitations [ 5 , 11 ]. Lately, there has been a growing fascination with the utilization of rare earth oxides in high-k gate dielectrics. La 2 O 3 has garnered significant interest as an exemplar of this. Due to its high-dielectric constant, lanthanum oxide also has a sufficiently large bandgap and higher conduction band offset, good thermodynamic stability, and excellent stability on Si substrates [ 12 – 14 ]. Therefore, La 2 O 3 emerges as a top contender for the next era of high-k gate dielectrics. But La 2 O 3 is unsuitable for high-temperature treatment during fabrication because of its low crystallization temperature, and its hygroscopicity is also a major problem for its MOS device applications. To improve its oxide quality, it has to be doped [ 15 – 17 ]. Some literature shows that Al doping of La 2 O 3 to increase its crystallization temperature can effectively reduce the hygroscopicity of La₂O₃, improve its stability in air, and enhance its electrical properties [ 18 – 20 ]. Introducing Al-doped La 2 O 3 has been shown to effectively enhance interface characteristics and improve the majority of desired high k properties [ 21 – 23 ]. At present, the sol-gel method can also produce high quality metal oxide semiconductors (MOS). This method is used in this paper because it is lower cost and easier to control the composition of the film. However, using sol-gel method to prepare the film also has its shortcomings, the quality of the film is affected by many factors such as temperature. To enhance the quality of the thin film, it is crucial to consider the annealing temperature [ 24 , 25 ]. Currently, there is limited existing literature discussing the impact of annealing temperature on the structural and electrical characteristics of LaAlO x gate dielectrics. This study involves the application of the sol-gel method to spin-coat high-k gate dielectric LaAlO x thin films onto silicon substrates. The structural and dielectric properties of the samples were investigated at different annealing temperatures. AFM analyzed the LaAlOx films' root-mean-square (RMS), and the films' interfacial properties were analyzed by XPS core energy level spectroscopy. Furthermore, a thorough analysis was conducted on the capacitance-voltage (C-V) and leakage current-density-voltage (I-V) characteristics at high frequencies. 2 Experimental procedure 2.1 Preparation of precursor solution A mixture of lanthanum nitrate and aluminum nitrate was dissolved in 2-methoxyethanol (C 3 H 8 O 2 ) solution (AR) with a La/Al molar ratio of 1:1, And added the same molar ratio of citric acid. The solution is heated and stirred for several hours to obtain a clear and transparent solution. It was aged at 25 ℃ for 48 hours. 2.2 Deposition and annealing of thin films In the ultrasonic cleaning instrument, the N-type Si (100) substrate was cleaned with acetone, ethanol, 1% diluted hydrofluoric acid solution and ion cleaning machine at 25℃ in order to ensure Si substrate surface was clean and hydrophilic. The LaAlO x solution was added to the Si substrate in drops, and then the substrate was placed on the spinning coating machine for spinning coating, the selected speed was 3000r/mim, and the spinning coating time was 30s. The spin-coated Si substrate is then placed on a heating table to bake the cured film and remove the solvent residue. Finally, the substrates were placed in a muffle furnace and annealed at 500, 600, 700, and 800°C for one hour. XRD compared the prepared lanthanum oxide films and lanthanum aluminate films. The surface of the films was analyzed, and their thickness was estimated using SEM. AFM analyzed the RMS of the films. The chemical states of each element in LaAlO x thin film were analyzed by XPS, and then the structural changes of LaAlO x thin film were studied. The charge correction was performed by C1s peak binding energy (284.8eV). 2.3 Fabrication and Characterization of MOS Devices Al gate electrodes were deposited onto LaAlO x films by magnetron sputtering using the shadow mask method to fabraicate the Al/LaAlO x /Si/Al MOS capacitors. The semiconductor device analyzer was utilized to measure the high frequency capacitance-voltage (C-V) and leakage current density-voltage (I-V) characteristics of Al/LaAlO x /Si/Al MOS capacitors. 3 Analysis 3.1 Microstructure analysis Figure 2 shows the XRD of La 2 O 3 and LaAlO x thin films deposited on Si substrate at 700°C. Based on some references, the La 2 O 3 film is amorphous at 500°C. Its weak diffraction peaks will appear at 600°C at 2θ equal to 29.96° and 39.53° [ 14 ]. According to reports, high-k gate dielectrics featuring an amorphous structure are considered more appropriate for CMOS device applications due to the fact that polycrystalline materials with grain gaps tend to create current pathways leading to increased leakage currents and reduced device reliability [ 26 ]. A comparison of La 2 O 3 and LaAlO x films annealed at 700°C reveals that the LaAlO x films do not show any obvious diffraction peaks, which indicates that aluminum doping does increase the crystallization temperature of La 2 O 3 , which is conducive to enhancing the dielectric properties of Al/LaAlO x /Si/Al MOS capacitors at high-temperature states [ 27 , 28 ]. The morphology of the thin film samples was examined using a scanning electron microscope (SEM) to analyze both their surface and cross-section. Figure 3 illustrates the SEM images of the cross-sectional views of LaAlO x thin films following exposure to various heat treatment temperatures. The film thickness reduces from 40 nm initially to 35 nm as the annealing temperature increases. This could be attributed to the transformation of hydroxyl groups into oxides in the films fabricated using the sol-gel technique and the evaporation of organic solvents involved in the films [ 14 ]. As seen from the Mapping diagram of the LaAlO x film, the La, Al, and O elements are consistent throughout the film. The surface morphology of LaAlO x thin films was analyzed using AFM. The images in Fig. 4 (a) and (b) depict the 2D and 3D AFM representations of the thin film samples, respectively. The RMS of the LaAlOx film after annealing at 500°C is measured to be 0.919 nm, and it decreases to a minimum of 0.320 nm when annealed at 700°C. Subsequently, the RMS increases to 0.539 nm when the annealing temperature reaches 800°C. This investigation replicates previous research, demonstrating that the annealing temperature significantly impacts surface roughness and grain size. A smoother gate dielectric layer resulting from a lower annealing temperature can effectively reduce interface trap density and enhance device performance The decrease in the RMS of LaAlO x films from 500°C to 700°C may be because the films are initially disordered, and as the temperature increases, the films tend to be ordered, and the roughness decreases. The rise in the RMS of the films between 700°C and 800°C may be due to the tendency of the films to crystallize [ 19 ]. The chemistry at the interface is crucial for high-k/Si gate stacks, and precise identification of interfacial details will establish guidelines for choosing appropriate high-k gate dielectric materials for CMOS devices. The variation patterns of Si 2p, O 1s, La 3d, and Al 2p spectra of LaAlO x /Si gate stacks with annealing temperature were determined by XPS measurements. Figure 5 shows the XPS measurement spectra of LaAlO x thin films. XPS experiments were conducted on the film specimens under varying annealing temperatures. C 1s (284.8 eV) in amorphous carbon was selected for the core calibration, and it can be observed in the figure that five elements, namely, La, Al, O, C, and Si, were detected in the full XPS spectrum of the LaAlO x film. It can be found that no peaks of other elements are detected except those of La, Si, Al, C, and O elements, indicating that Al has been doped into La 2 O 3 . Figure 6 depicts the O1s core energy level spectra of LaAlO x gate-dielectric thin films with Si gate stacks, illustrating variations in response to annealing temperature. At 530.15 and 531.31 eV, all O1s peaks are deconvoluted into two subpeaks. In the film the first one comes from the bond between M and O in the film, while the second one comes from the bond between M and OH [ 29 ]. The existence of M-OH in gate dielectric films typically results in the generation of trap and defect states within the film's band gap, which can cause a rise in leakage current and a reduction in breakdown voltage for electrical devices. Meanwhile, forming a higher percentage of M-O bonds can lead to better dielectric properties for the device. Based on the data in Fig. 6 (e), it is evident that the concentration of M-O bonds rises as the annealing temperature increases. The presence of M-OH bonds diminishes as the annealing temperature rises, as indicated in Table 1 . This phenomenon can be attributed to the increase in temperature leading to thermal condensation within the La-OH and Al-OH bond films, gradually transforming them into La -O and Al-O bonds. Consequently, this results in an increased coordination number of metal ions, thereby facilitating the bonding of metal ions with oxygen ions. It can also be seen that as the annealing temperature increases to 800°C, the fitted O1s peak shifts to the direction of high binding energy, indicating that LaAlO x is fully oxidized and more silicate layers are formed, which will adversely affect the dielectric properties of Al/LaAlO x /Si/Al MOS capacitors. Figure 6 (f) illustrates the La 3d spectra of LaAlOx thin films at various annealing temperatures. The spectra display a central peak (La 3d 5/2 ) and a spin-splitting peak (La 3d 3/2 ), with energy differences of approximately 16.80, 16.80, 16.90, and 17.00 eV from 500 to 800°C. Based on the available literature, it has been observed that the splitting energies of La3d 3/2 and La3d 5/2 are approximately 16.80 eV, indicating the presence of the La + state. [ 30 ]. At 700°C, the movement of the peaks towards lower binding energies suggests the existence of O-La-O bonds within the LaAlO x films. However, with an increase in temperature to 800°C, there is a shift in binding energy towards higher values due to the close proximity of the La silicate layer to the interface with the Si substrate [ 14 ]. Table 1 Corresponding peak positions, half-height widths, and content percentages of each component of LaAlO x gate dielectric films O 1s Temperature M-O Vo Peak position (eV) FWHM (eV) Content percentage Peak position (eV) FWHM (eV) Content percentage 500℃ 529.97 2.29 74.6% 531.32 1.77 25.4% 600℃ 530.03 2.18 78.7% 531.46 1.68 21.3% 700℃ 529.47 2.51 83.3% 531.04 2.02 16.7% 800℃ 529.89 2.5 87.7% 531.57 2.24 12.3% MOS capacitors were fabricated using Al/LaAlO x /Si/Al structure, where Al top electrodes with an area of 7.068×10 − 4 cm 2 were deposited on the LaAlO x gate dielectric film via magnetron sputtering under shadowing, and Al back electrodes with the same thickness were applied to the backside of the silicon substrate. Figure 7 shows the variation curves of high-frequency (1 MHz) capacitance-voltage (C-V) with annealing temperature for the LaAlO x gate-dielectric MOS capacitor with double-sweeping in the range of ± 8 V gate voltage. It is evident that the accumulated capacitance \(\:{\text{C}}_{\text{o}\text{x}}\) exhibits a clear pattern of change as the annealing temperature increases. Initially, it rises with the annealing temperature, peaks at 700°C, and subsequently declines. The accumulated capacitances of LaAlO x are 245.01, 332.31, 365.82, and 353.27 pF, respectively. By Eq. [ 31 ]: $$\:\text{k}=\frac{{\text{C}}_{\text{o}\text{x}}\text{d}}{{{\epsilon\:}}_{0}\text{A}}$$ Where \(\:{\text{C}}_{\text{o}\text{x}}\) is the accumulated capacitance, d is the film thickness, \(\:{{\epsilon\:}}_{0}\) is the vacuum dielectric constant ( \(\:{{\epsilon\:}}_{0}\) =8.854×10 − 12 F/m). The dielectric constants (k) of the samples annealed at 500°C, 600°C, 700°C, and 800°C were determined to be 15.73, 21.35, 20.91, and 20.79 respectively based on the area of the Al top electrode (A). The findings indicate that the effective dielectric constant (k) of the LaAlOx gate dielectric shifts from 15.73 for the annealed sample at 500°C to 20.79 for the annealed sample at 800°C, potentially attributed to the rise in annealing temperature. According to the XPS analysis, it is apparent that elevating the annealing temperature improves the interface quality and suppresses the expansion of low-k SiO x interlayer [ 32 ]. Furthermore, the flat-band capacitance ( \(\:{\text{C}}_{\text{f}\text{b}}\) ) of the sample was used to calculate the \(\:{\text{V}}_{\text{f}\text{b}}\) , the EOT, the \(\:{\text{Q}}_{\text{o}\text{x}}\) and the electrical parameters such as the \(\:\varDelta\:{\text{V}}_{\text{f}\text{b}}\) , and the \(\:{\text{N}}_{\text{b}\text{t}}\) in Table 2 . The \(\:{\text{V}}_{\text{f}\text{b}}\) is associated with the oxide charge density, while the hysteresis is linked to the boundary-trap oxide charge density. Table 2 Electrical properties derived from C-V and I-V characteristics Annealing Temperature k \(\:EOT\left(nm\right)\) \(\:{C}_{ox}\left(pF\right)\) \(\:{C}_{fb}\left(pF\right)\) \(\:{V}_{fb}\) \(\:\varDelta\:{V}_{fb}\) \(\:{Q}_{ox}\left({cm}^{-2}\right)\) \(\:{N}_{bt}\left({cm}^{-2}\right)\) \(\:{J}_{g}\left({A/cm}^{2}\right)\) 500℃ 15.74 9.96 245.01 61.09 -0.32 1.28 1.04×10 12 2.77×10 12 1.39×10 − 1 600℃ 21.35 7.34 332.31 49.23 -0.72 0.32 2.35×10 11 9.40×10 11 2.17×10 − 2 700℃ 20.91 6.67 365.82 44.88 -0.24 0.16 1.81×10 12 5.17×10 11 3.54×10 − 3 800℃ 20.79 6.91 353.27 40.84 -0.08 0.16 2.29×10 12 4.99×10 11 8.84×10 − 3 The absolute value of \(\:{\text{V}}_{\text{f}\text{b}}\) decreases as the annealing temperature increases. Films annealed at high temperatures exhibit reduced defects and traps, resulting in improved interface quality compared to films annealed at low temperatures. It is clear from Fig. 7 and Table 2 that the LaAlO x films annealed at 700°C have less hysteresis. It can be inferred that the hysteresis phenomenon is connected to the trapping of oxygen charges at the boundary, which indicates that the interface properties of the doped lanthanum alumina thin film have been enhanced with the increase of annealing temperature. At a gate voltage of 1 V the I-V characteristics depicted in Fig. 8 indicate that the LaAlO x films annealed at 700°C exhibit a minimum leakage current density of 3.54 × 10 − 3 A/cm 2 . Raising the annealing temperature results in a higher surface density of the samples and improved adhesion of the film surface, leading to effectively reduced interfacial density of states and traps. The increase in \(\:{\text{Q}}_{\text{o}\text{x}}\) values with rising annealing temperature may be attributed to the generation of oxygen vacancies in the film caused by higher annealing temperatures. The \(\:{\text{N}}_{\text{b}\text{t}}\) values of samples annealed at higher temperatures appear to be relatively smaller compared to those annealed at 500°C. This could be attributed to the enhanced formation of denser gate dielectric films and higher-quality interfaces facilitated by the elevated annealing temperatures [ 20 ]. Nevertheless, as the annealing temperature was raised to 800°C, there was a noticeable rise in the leakage current density of the films. The findings suggest the electrical performances of LaAlO x films are optimal when annealed at 700°C. 4 Conclusion In brief, we conducted a systematic investigation into the impact of varying annealing temperatures on the RMS, interfacial and electrical properties of LaAlO x high-k gate dielectric thin films prepared using the solution method. At 700°C, the RMS was minimized and the film's surface exhibited smoothness. XPS analysis reveals that the bonding between metal and oxygen increases while the bonding between metal and hydroxyl decreases with increasing annealing temperature. This suggests that the introduction of Al effectively suppresses the moisture absorption of La 2 O 3 , thereby preventing the formation of low-k SiO x and enhancing the interface quality between the dielectric film and Si substrate. At the same time, this enhances the dielectric properties of the Al/LaAlO x /Si/Al MOS capacitors. A semiconductor device analyzer found that higher annealing temperatures lead to an increase in the accumulated capacitance \(\:{\text{C}}_{\text{o}\text{x}}\) , resulting in a higher k value. Additionally, as the annealing temperature increases, the \(\:{N}_{bt}\) value decreases progressively due to the facilitation of denser gate dielectric film formation and improved interface quality. Raising the annealing temperature also leads to a decrease in leakage current density, with the lowest recorded value of 3.54×10 − 3 A/cm 2 observed at 700°C. In general, LaAlO x films annealed at 700°C demonstrate outstanding characteristics attributed to enhanced interfacial chemistry and electrical properties, positioning them as potential choices for upcoming high-k gate dielectrics. Declarations Funding This research was supported by the Natural Science Foundation of Xinjiang Uygur Autonomous Region (2021D01C035) Author Contribution Zhenhua Huang:A Kamale Tuokedaerhan: B Linyu Yang:C Chaozhong Guo:D Zhengang Cai:E Margulan Ibraimov:F Serikbek Sailanbek: GA: Writing – review & editing, Writing – original draft, Methodology, Investigation, Data curation. B:Supervision, Resources, Funding acquisition, Conceptualization.C: Supervision, Resources. D and E: Methodology, Formal analysis. F adn G: Resources.All authors reviewed the manuscript. Acknowledgments This research was supported by the Natural Science Foundation of Xinjiang Uygur Autonomous Region (2021D01C035) References Prakash, P., K. Mohana Sundaram, and M. Anto Bennet, A review on carbon nanotube field effect transistors (CNTFETs) for ultra-low power applications . Renewable and Sustainable Energy Reviews, 2018. 89: p. 194–203. https://doi.org/10.1016/j.rser.2018.03.021 He, G., X. Chen, and Z. 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Sun, Microstructure, optical and electrical properties of sputtered HfTiO high-k gate dielectric thin films . Ceramics International, 2016. 42(10): p. 11640–11649. https://doi.org/10.1016/j.ceramint.2016.04.067 Wong, H., B.L. Yang, K. Kakushima, P. Ahmet, and H. Iwai, Effects of aluminum doping on lanthanum oxide gate dielectric films . Vacuum, 2012. 86(7): p. 929–932. https://doi.org/10.1016/j.vacuum.2011.06.023 Li, W.D., G. He, C.Y. Zheng, S. Liang, L. Zhu, and S.S. Jiang, Solution-processed HfGdO gate dielectric thin films for CMOS application: Effect of annealing temperature . Journal of Alloys and Compounds, 2018. 731: p. 150–155. https://doi.org/10.1016/j.jallcom.2017.10.019 Yadav, A.A., A.C. Lokhande, R.B. Pujari, J.H. Kim, and C.D. Lokhande, The synthesis of multifunctional porous honey comb-like La(2)O(3) thin film for supercapacitor and gas sensor applications . J Colloid Interface Sci, 2016. 484: p. 51–59. https://doi.org/10.1016/j.jcis.2016.08.056 Jin, P., G. He, P.H. Wang, M. Liu, D.Q. Xiao, J. Gao, H.S. Chen, X.S. Chen, Z.Q. Sun, M. Zhang, J.G. Lv, and Y.M. Liu, Baking-temperature-modulated optical and electrical properties of HfTiOx gate dielectrics via sol-gel method . Journal of Alloys and Compounds, 2016. 688: p. 925–932. https://doi.org/10.1016/j.jallcom.2016.07.261 Xiao, D.Q., G. He, J.G. Lv, P.H. Wang, M. Liu, J. Gao, P. Jin, S.S. Jiang, W.D. Li, and Z.Q. Sun, Interfacial modulation and electrical properties improvement of solution-processed ZrO 2 gate dielectrics upon Gd incorporation . Journal of Alloys and Compounds, 2017. 699: p. 415–420. https://doi.org/10.1016/j.jallcom.2016.12.376 Additional Declarations No competing interests reported. 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Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-4984081","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":359248068,"identity":"a3765a7b-4b63-417b-99f9-78f0900a738d","order_by":0,"name":"Zhenhua Huang","email":"","orcid":"","institution":"Xinjiang University","correspondingAuthor":false,"prefix":"","firstName":"Zhenhua","middleName":"","lastName":"Huang","suffix":""},{"id":359248070,"identity":"5f8a1dc1-1b22-4289-a9d9-ee385821cff9","order_by":1,"name":"Kamale Tuokedaerhan","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAAA2klEQVRIiWNgGAWjYBACCRDxgMGGh1/+8IEDH34QqyWBIU1OcgZb4sGZPcRrOWxscIPH+DAHGxFaJNtPJ35IqDic2HC758NhBh4GeX6xA/i1SPPkbpZIOJOe2Djn7IbDBRYMhjNnJ+DXIseQu0Eisc06sRnIODyDhyHB4DYhLfxvN/9I/Mec2MaQ8+AwDxsRWqQlcrdJJDY4G/NI5DAQp0VyxtttFgnH0uQkeI4ZAANZgrBfJM7nbr7xocaGx/548+MPH37YyPNLE9CCYQRpykfBKBgFo2AUYAcALDVKFwLGrqkAAAAASUVORK5CYII=","orcid":"","institution":"Xinjiang University","correspondingAuthor":true,"prefix":"","firstName":"Kamale","middleName":"","lastName":"Tuokedaerhan","suffix":""},{"id":359248071,"identity":"8928a0e1-70fd-48b3-966c-5f94fca309fa","order_by":2,"name":"Linyu Yang","email":"","orcid":"","institution":"Xinjiang University","correspondingAuthor":false,"prefix":"","firstName":"Linyu","middleName":"","lastName":"Yang","suffix":""},{"id":359248072,"identity":"979cba7c-282c-4627-a71d-b291054aa457","order_by":3,"name":"Chaozhong Guo","email":"","orcid":"","institution":"Xinjiang University","correspondingAuthor":false,"prefix":"","firstName":"Chaozhong","middleName":"","lastName":"Guo","suffix":""},{"id":359248075,"identity":"dc8142e1-7485-4ede-a910-fd6f69a2a166","order_by":4,"name":"Zhengang Cai","email":"","orcid":"","institution":"Xinjiang University","correspondingAuthor":false,"prefix":"","firstName":"Zhengang","middleName":"","lastName":"Cai","suffix":""},{"id":359248076,"identity":"ebb33781-7522-447d-85cc-43c47d3d4b7e","order_by":5,"name":"Margulan Ibraimov","email":"","orcid":"","institution":"AL-Farabi Kazakh National University","correspondingAuthor":false,"prefix":"","firstName":"Margulan","middleName":"","lastName":"Ibraimov","suffix":""},{"id":359248077,"identity":"3ebcffec-e619-4614-b840-3a6b5fac67b8","order_by":6,"name":"Serikbek Sailanbek","email":"","orcid":"","institution":"AL-Farabi Kazakh National University","correspondingAuthor":false,"prefix":"","firstName":"Serikbek","middleName":"","lastName":"Sailanbek","suffix":""}],"badges":[],"createdAt":"2024-08-27 11:22:28","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-4984081/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-4984081/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":65600821,"identity":"ffbf5cc8-3bba-4509-abf8-57d5b1e9bcc9","added_by":"auto","created_at":"2024-09-30 11:54:08","extension":"jpg","order_by":1,"title":"Figure 1","display":"","copyAsset":false,"role":"figure","size":93091,"visible":true,"origin":"","legend":"\u003cp\u003eFabrication flow chart of Al/LaAlO\u003csub\u003ex\u003c/sub\u003e/Si/Al MOS capacitors\u003c/p\u003e","description":"","filename":"Picture1.jpg","url":"https://assets-eu.researchsquare.com/files/rs-4984081/v1/77c61d3fb4212164ba6c433c.jpg"},{"id":65602154,"identity":"a76040b9-de65-45c9-a3db-d44485850d11","added_by":"auto","created_at":"2024-09-30 12:02:08","extension":"jpg","order_by":2,"title":"Figure 2","display":"","copyAsset":false,"role":"figure","size":173713,"visible":true,"origin":"","legend":"\u003cp\u003eXRD plots of pure phase La\u003csub\u003e2\u003c/sub\u003eO\u003csub\u003e3\u003c/sub\u003e films and LaAlO\u003csub\u003ex \u003c/sub\u003efilms\u003c/p\u003e","description":"","filename":"Picture2.jpg","url":"https://assets-eu.researchsquare.com/files/rs-4984081/v1/dc265a0e97806d09a2d0dcfa.jpg"},{"id":65600823,"identity":"0b1920d1-7bca-408a-8325-4fb4240d4339","added_by":"auto","created_at":"2024-09-30 11:54:08","extension":"jpg","order_by":3,"title":"Figure 3","display":"","copyAsset":false,"role":"figure","size":1651766,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003e(a-d) \u003c/strong\u003eThe cross-sectional SEM images of the LaAlO\u003csub\u003ex\u003c/sub\u003e film \u003cstrong\u003e(e-h) \u003c/strong\u003eSEM mapping of the samples\u003c/p\u003e","description":"","filename":"Picture3.jpg","url":"https://assets-eu.researchsquare.com/files/rs-4984081/v1/76c666f9fb919d8fb1839a87.jpg"},{"id":65600820,"identity":"f78f9351-646a-4068-8292-559f262cd9cb","added_by":"auto","created_at":"2024-09-30 11:54:08","extension":"jpg","order_by":4,"title":"Figure 4","display":"","copyAsset":false,"role":"figure","size":1820555,"visible":true,"origin":"","legend":"\u003cp\u003e(a-b) shows the AFM 2D and 3D images of the LaAlO\u003csub\u003ex\u003c/sub\u003e thin film\u003c/p\u003e","description":"","filename":"Picture4.jpg","url":"https://assets-eu.researchsquare.com/files/rs-4984081/v1/f4a55f9179189653ad6f383f.jpg"},{"id":65602153,"identity":"45ea0038-0846-40d6-8439-ab7f66156f01","added_by":"auto","created_at":"2024-09-30 12:02:08","extension":"jpg","order_by":5,"title":"Figure 5","display":"","copyAsset":false,"role":"figure","size":239324,"visible":true,"origin":"","legend":"\u003cp\u003eXPS full spectrum of LaAlO\u003csub\u003ex\u003c/sub\u003e thin films at annealing temperatures of 500-800°C\u003c/p\u003e","description":"","filename":"Picture5.jpg","url":"https://assets-eu.researchsquare.com/files/rs-4984081/v1/fc61525002f134c456d8c6c7.jpg"},{"id":65600827,"identity":"49e3095d-ec36-4426-bcf2-e2c808ace8a3","added_by":"auto","created_at":"2024-09-30 11:54:08","extension":"jpg","order_by":6,"title":"Figure 6","display":"","copyAsset":false,"role":"figure","size":535601,"visible":true,"origin":"","legend":"\u003cp\u003exps O 1s spectra of thin films made from LaAlO\u003csub\u003ex\u003c/sub\u003e under various annealing temperatures\u003c/p\u003e","description":"","filename":"Picture6.jpg","url":"https://assets-eu.researchsquare.com/files/rs-4984081/v1/f47ed4100ba55c36d96a2adf.jpg"},{"id":65600826,"identity":"a175134a-d793-408a-a79a-b69c161189bd","added_by":"auto","created_at":"2024-09-30 11:54:08","extension":"jpg","order_by":7,"title":"Figure 7","display":"","copyAsset":false,"role":"figure","size":272888,"visible":true,"origin":"","legend":"\u003cp\u003eC-V measured at high frequency (1MHz) for MOS devices with Al/LaAlO\u003csub\u003ex\u003c/sub\u003e /n-Si/Al structure\u003c/p\u003e","description":"","filename":"Picture7.jpg","url":"https://assets-eu.researchsquare.com/files/rs-4984081/v1/d88c18f31b889d7c4d10af47.jpg"},{"id":65602155,"identity":"cecbdffa-c8d5-4389-9fd1-5930f2ae5231","added_by":"auto","created_at":"2024-09-30 12:02:08","extension":"jpg","order_by":8,"title":"Figure 8","display":"","copyAsset":false,"role":"figure","size":256308,"visible":true,"origin":"","legend":"\u003cp\u003eI-V measured at high frequency (1MHz) for MOS devices with Al/LaAlO\u003csub\u003ex\u003c/sub\u003e /n-Si/Al structure\u003c/p\u003e","description":"","filename":"Picture8.jpg","url":"https://assets-eu.researchsquare.com/files/rs-4984081/v1/5e140bf18c1b21df745d6cfd.jpg"},{"id":66126753,"identity":"1d64bd1b-05dc-495c-99e2-262f72428e56","added_by":"auto","created_at":"2024-10-08 02:54:13","extension":"pdf","order_by":0,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":5576186,"visible":true,"origin":"","legend":"","description":"","filename":"manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-4984081/v1/17d37b27-e249-4580-8770-5f3445da17e2.pdf"},{"id":65600828,"identity":"fdc90d14-2bbd-434d-93a0-d38cf0c7d77f","added_by":"auto","created_at":"2024-09-30 11:54:08","extension":"png","order_by":2,"title":"","display":"","copyAsset":false,"role":"supplement","size":618365,"visible":true,"origin":"","legend":"","description":"","filename":"Onlinefloatimage1.png","url":"https://assets-eu.researchsquare.com/files/rs-4984081/v1/c5e5e5ed1d9e18d06e146929.png"}],"financialInterests":"No competing interests reported.","formattedTitle":"The performance of LaAlO x gate dielectric films prepared by sol-gel method at different temperatures of annealing","fulltext":[{"header":"Highlights","content":"\u003cp\u003ePrepared LaAlO\u003csub\u003ex\u003c/sub\u003e thin films by sol-gel method and the effects of different annealing temperatures on the interface structure of the films were analyzed by XRD、AFM、XPS and so on.\u003c/p\u003e\n\u003cp\u003eFabraicated the Al/LaAlO\u003csub\u003ex\u003c/sub\u003e/Si/Al metal-oxide-semiconductor capacitors by RF magnetron sputtering, and the effects of different annealing temperatures on the electrical properties.\u003c/p\u003e\n\u003cp\u003eAnnealed at 700 ℃, the RMS of the LaAlO\u003csub\u003ex\u003c/sub\u003e film reaches a minimum of 0.320 nm and the content of M-O bond is higher. The lowest leakage current density of 3.54\u0026times;10\u003csup\u003e-3\u003c/sup\u003e A/cm\u003csup\u003e2\u003c/sup\u003e is also reached at 700 \u0026deg;C.\u003c/p\u003e"},{"header":"1 Introduction","content":"\u003cp\u003eMetal Oxide Semiconductor Field Effect Transistors (MOSFETS) are one of the core components of integrated circuits (ICs) because of their small size, high efficiency and low power consumption [\u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e, \u003cspan citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e]. It acts as a switch or amplifier in electronic devices, making digital logic operations possible. Advances in MOSFET technology have driven miniaturization and performance improvements in ICs, which have driven the development of robust and efficient electronic devices. Almost all electronic devices, from microprocessors to memory chips, use MOSFETs in ICs [\u003cspan additionalcitationids=\"CR4\" citationid=\"CR3\" class=\"CitationRef\"\u003e3\u003c/span\u003e\u0026ndash;\u003cspan citationid=\"CR5\" class=\"CitationRef\"\u003e5\u003c/span\u003e]. However, with the ongoing reduction in the size of MOSFETs, it becomes necessary to decrease the thickness of traditional silicon oxide (SiO₂) used as a gate dielectric in order to uphold adequate gate capacitance due to its low dielectric constant [\u003cspan additionalcitationids=\"CR7\" citationid=\"CR6\" class=\"CitationRef\"\u003e6\u003c/span\u003e\u0026ndash;\u003cspan citationid=\"CR8\" class=\"CitationRef\"\u003e8\u003c/span\u003e]. However, the thickness of SiO\u003csub\u003e2\u003c/sub\u003e gate medium can not be too thin. When the thickness of SiO\u003csub\u003e2\u003c/sub\u003e gate dielectric decreases to a certain value, the leakage current increases dramatically, and the performance of MOS devices deteriorates or even breakdown [\u003cspan citationid=\"CR9\" class=\"CitationRef\"\u003e9\u003c/span\u003e, \u003cspan citationid=\"CR10\" class=\"CitationRef\"\u003e10\u003c/span\u003e]. Therefore, finding a material with a higher dielectric constant was necessary to replace the traditional SiO\u003csub\u003e2\u003c/sub\u003e. In 2007, at the 45-nm technology node, Intel Corporation was the first to realize the use of HfO₂, a material with superior dielectric properties and exceptional stability, to replace SiO₂ as the gate dielectric material[\u003cspan citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e, \u003cspan citationid=\"CR10\" class=\"CitationRef\"\u003e10\u003c/span\u003e]. However, although HfO\u003csub\u003e2\u003c/sub\u003e has been applied in practice, there is a need to explore alternative high-k materials to replace it due to its evident limitations [\u003cspan citationid=\"CR5\" class=\"CitationRef\"\u003e5\u003c/span\u003e, \u003cspan citationid=\"CR11\" class=\"CitationRef\"\u003e11\u003c/span\u003e].\u003c/p\u003e \u003cp\u003eLately, there has been a growing fascination with the utilization of rare earth oxides in high-k gate dielectrics. La\u003csub\u003e2\u003c/sub\u003eO\u003csub\u003e3\u003c/sub\u003e has garnered significant interest as an exemplar of this. Due to its high-dielectric constant, lanthanum oxide also has a sufficiently large bandgap and higher conduction band offset, good thermodynamic stability, and excellent stability on Si substrates [\u003cspan additionalcitationids=\"CR13\" citationid=\"CR12\" class=\"CitationRef\"\u003e12\u003c/span\u003e\u0026ndash;\u003cspan citationid=\"CR14\" class=\"CitationRef\"\u003e14\u003c/span\u003e]. Therefore, La\u003csub\u003e2\u003c/sub\u003eO\u003csub\u003e3\u003c/sub\u003e emerges as a top contender for the next era of high-k gate dielectrics. But La\u003csub\u003e2\u003c/sub\u003eO\u003csub\u003e3\u003c/sub\u003e is unsuitable for high-temperature treatment during fabrication because of its low crystallization temperature, and its hygroscopicity is also a major problem for its MOS device applications. To improve its oxide quality, it has to be doped [\u003cspan additionalcitationids=\"CR16\" citationid=\"CR15\" class=\"CitationRef\"\u003e15\u003c/span\u003e\u0026ndash;\u003cspan citationid=\"CR17\" class=\"CitationRef\"\u003e17\u003c/span\u003e]. Some literature shows that Al doping of La\u003csub\u003e2\u003c/sub\u003eO\u003csub\u003e3\u003c/sub\u003e to increase its crystallization temperature can effectively reduce the hygroscopicity of La₂O₃, improve its stability in air, and enhance its electrical properties [\u003cspan additionalcitationids=\"CR19\" citationid=\"CR18\" class=\"CitationRef\"\u003e18\u003c/span\u003e\u0026ndash;\u003cspan citationid=\"CR20\" class=\"CitationRef\"\u003e20\u003c/span\u003e]. Introducing Al-doped La\u003csub\u003e2\u003c/sub\u003eO\u003csub\u003e3\u003c/sub\u003e has been shown to effectively enhance interface characteristics and improve the majority of desired high k properties [\u003cspan additionalcitationids=\"CR22\" citationid=\"CR21\" class=\"CitationRef\"\u003e21\u003c/span\u003e\u0026ndash;\u003cspan citationid=\"CR23\" class=\"CitationRef\"\u003e23\u003c/span\u003e].\u003c/p\u003e \u003cp\u003eAt present, the sol-gel method can also produce high quality metal oxide semiconductors (MOS). This method is used in this paper because it is lower cost and easier to control the composition of the film. However, using sol-gel method to prepare the film also has its shortcomings, the quality of the film is affected by many factors such as temperature. To enhance the quality of the thin film, it is crucial to consider the annealing temperature [\u003cspan citationid=\"CR24\" class=\"CitationRef\"\u003e24\u003c/span\u003e, \u003cspan citationid=\"CR25\" class=\"CitationRef\"\u003e25\u003c/span\u003e]. Currently, there is limited existing literature discussing the impact of annealing temperature on the structural and electrical characteristics of LaAlO\u003csub\u003ex\u003c/sub\u003e gate dielectrics. This study involves the application of the sol-gel method to spin-coat high-k gate dielectric LaAlO\u003csub\u003ex\u003c/sub\u003e thin films onto silicon substrates. The structural and dielectric properties of the samples were investigated at different annealing temperatures. AFM analyzed the LaAlOx films' root-mean-square (RMS), and the films' interfacial properties were analyzed by XPS core energy level spectroscopy. Furthermore, a thorough analysis was conducted on the capacitance-voltage (C-V) and leakage current-density-voltage (I-V) characteristics at high frequencies.\u003c/p\u003e"},{"header":"2 Experimental procedure","content":"\u003cdiv id=\"Sec3\" class=\"Section2\"\u003e \u003ch2\u003e2.1 Preparation of precursor solution\u003c/h2\u003e \u003cp\u003eA mixture of lanthanum nitrate and aluminum nitrate was dissolved in 2-methoxyethanol (C\u003csub\u003e3\u003c/sub\u003eH\u003csub\u003e8\u003c/sub\u003eO\u003csub\u003e2\u003c/sub\u003e) solution (AR) with a La/Al molar ratio of 1:1, And added the same molar ratio of citric acid. The solution is heated and stirred for several hours to obtain a clear and transparent solution. It was aged at 25 ℃ for 48 hours.\u003c/p\u003e \u003c/div\u003e \u003cdiv id=\"Sec4\" class=\"Section2\"\u003e \u003ch2\u003e2.2 Deposition and annealing of thin films\u003c/h2\u003e \u003cp\u003eIn the ultrasonic cleaning instrument, the N-type Si (100) substrate was cleaned with acetone, ethanol, 1% diluted hydrofluoric acid solution and ion cleaning machine at 25℃ in order to ensure Si substrate surface was clean and hydrophilic. The LaAlO\u003csub\u003ex\u003c/sub\u003e solution was added to the Si substrate in drops, and then the substrate was placed on the spinning coating machine for spinning coating, the selected speed was 3000r/mim, and the spinning coating time was 30s. The spin-coated Si substrate is then placed on a heating table to bake the cured film and remove the solvent residue. Finally, the substrates were placed in a muffle furnace and annealed at 500, 600, 700, and 800\u0026deg;C for one hour. XRD compared the prepared lanthanum oxide films and lanthanum aluminate films. The surface of the films was analyzed, and their thickness was estimated using SEM. AFM analyzed the RMS of the films. The chemical states of each element in LaAlO\u003csub\u003ex\u003c/sub\u003e thin film were analyzed by XPS, and then the structural changes of LaAlO\u003csub\u003ex\u003c/sub\u003e thin film were studied. The charge correction was performed by C1s peak binding energy (284.8eV).\u003c/p\u003e \u003c/div\u003e \u003cdiv id=\"Sec5\" class=\"Section2\"\u003e \u003ch2\u003e2.3 Fabrication and Characterization of MOS Devices\u003c/h2\u003e \u003cp\u003eAl gate electrodes were deposited onto LaAlO\u003csub\u003ex\u003c/sub\u003e films by magnetron sputtering using the shadow mask method to fabraicate the Al/LaAlO\u003csub\u003ex\u003c/sub\u003e/Si/Al MOS capacitors. The semiconductor device analyzer was utilized to measure the high frequency capacitance-voltage (C-V) and leakage current density-voltage (I-V) characteristics of Al/LaAlO\u003csub\u003ex\u003c/sub\u003e/Si/Al MOS capacitors.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003c/div\u003e"},{"header":"3 Analysis","content":"\u003cdiv id=\"Sec7\" class=\"Section2\"\u003e \u003ch2\u003e3.1 Microstructure analysis\u003c/h2\u003e \u003cp\u003eFigure \u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e2\u003c/span\u003e shows the XRD of La\u003csub\u003e2\u003c/sub\u003eO\u003csub\u003e3\u003c/sub\u003e and LaAlO\u003csub\u003ex\u003c/sub\u003e thin films deposited on Si substrate at 700\u0026deg;C. Based on some references, the La\u003csub\u003e2\u003c/sub\u003eO\u003csub\u003e3\u003c/sub\u003e film is amorphous at 500\u0026deg;C. Its weak diffraction peaks will appear at 600\u0026deg;C at 2θ equal to 29.96\u0026deg; and 39.53\u0026deg; [\u003cspan citationid=\"CR14\" class=\"CitationRef\"\u003e14\u003c/span\u003e]. According to reports, high-k gate dielectrics featuring an amorphous structure are considered more appropriate for CMOS device applications due to the fact that polycrystalline materials with grain gaps tend to create current pathways leading to increased leakage currents and reduced device reliability [\u003cspan citationid=\"CR26\" class=\"CitationRef\"\u003e26\u003c/span\u003e]. A comparison of La\u003csub\u003e2\u003c/sub\u003eO\u003csub\u003e3\u003c/sub\u003e and LaAlO\u003csub\u003ex\u003c/sub\u003e films annealed at 700\u0026deg;C reveals that the LaAlO\u003csub\u003ex\u003c/sub\u003e films do not show any obvious diffraction peaks, which indicates that aluminum doping does increase the crystallization temperature of La\u003csub\u003e2\u003c/sub\u003eO\u003csub\u003e3\u003c/sub\u003e, which is conducive to enhancing the dielectric properties of Al/LaAlO\u003csub\u003ex\u003c/sub\u003e/Si/Al MOS capacitors at high-temperature states [\u003cspan citationid=\"CR27\" class=\"CitationRef\"\u003e27\u003c/span\u003e, \u003cspan citationid=\"CR28\" class=\"CitationRef\"\u003e28\u003c/span\u003e].\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eThe morphology of the thin film samples was examined using a scanning electron microscope (SEM) to analyze both their surface and cross-section. Figure\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003e illustrates the SEM images of the cross-sectional views of LaAlO\u003csub\u003ex\u003c/sub\u003e thin films following exposure to various heat treatment temperatures. The film thickness reduces from 40 nm initially to 35 nm as the annealing temperature increases. This could be attributed to the transformation of hydroxyl groups into oxides in the films fabricated using the sol-gel technique and the evaporation of organic solvents involved in the films [\u003cspan citationid=\"CR14\" class=\"CitationRef\"\u003e14\u003c/span\u003e]. As seen from the Mapping diagram of the LaAlO\u003csub\u003ex\u003c/sub\u003e film, the La, Al, and O elements are consistent throughout the film.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eThe surface morphology of LaAlO\u003csub\u003ex\u003c/sub\u003e thin films was analyzed using AFM. The images in Fig.\u0026nbsp;\u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003e (a) and (b) depict the 2D and 3D AFM representations of the thin film samples, respectively. The RMS of the LaAlOx film after annealing at 500\u0026deg;C is measured to be 0.919 nm, and it decreases to a minimum of 0.320 nm when annealed at 700\u0026deg;C. Subsequently, the RMS increases to 0.539 nm when the annealing temperature reaches 800\u0026deg;C. This investigation replicates previous research, demonstrating that the annealing temperature significantly impacts surface roughness and grain size. A smoother gate dielectric layer resulting from a lower annealing temperature can effectively reduce interface trap density and enhance device performance The decrease in the RMS of LaAlO\u003csub\u003ex\u003c/sub\u003e films from 500\u0026deg;C to 700\u0026deg;C may be because the films are initially disordered, and as the temperature increases, the films tend to be ordered, and the roughness decreases. The rise in the RMS of the films between 700\u0026deg;C and 800\u0026deg;C may be due to the tendency of the films to crystallize [\u003cspan citationid=\"CR19\" class=\"CitationRef\"\u003e19\u003c/span\u003e].\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eThe chemistry at the interface is crucial for high-k/Si gate stacks, and precise identification of interfacial details will establish guidelines for choosing appropriate high-k gate dielectric materials for CMOS devices. The variation patterns of Si 2p, O 1s, La 3d, and Al 2p spectra of LaAlO\u003csub\u003ex\u003c/sub\u003e/Si gate stacks with annealing temperature were determined by XPS measurements. Figure\u0026nbsp;\u003cspan refid=\"Fig5\" class=\"InternalRef\"\u003e5\u003c/span\u003e shows the XPS measurement spectra of LaAlO\u003csub\u003ex\u003c/sub\u003e thin films. XPS experiments were conducted on the film specimens under varying annealing temperatures. C 1s (284.8 eV) in amorphous carbon was selected for the core calibration, and it can be observed in the figure that five elements, namely, La, Al, O, C, and Si, were detected in the full XPS spectrum of the LaAlO\u003csub\u003ex\u003c/sub\u003e film. It can be found that no peaks of other elements are detected except those of La, Si, Al, C, and O elements, indicating that Al has been doped into La\u003csub\u003e2\u003c/sub\u003eO\u003csub\u003e3\u003c/sub\u003e.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eFigure \u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e depicts the O1s core energy level spectra of LaAlO\u003csub\u003ex\u003c/sub\u003e gate-dielectric thin films with Si gate stacks, illustrating variations in response to annealing temperature. At 530.15 and 531.31 eV, all O1s peaks are deconvoluted into two subpeaks. In the film the first one comes from the bond between M and O in the film, while the second one comes from the bond between M and OH [\u003cspan citationid=\"CR29\" class=\"CitationRef\"\u003e29\u003c/span\u003e]. The existence of M-OH in gate dielectric films typically results in the generation of trap and defect states within the film's band gap, which can cause a rise in leakage current and a reduction in breakdown voltage for electrical devices. Meanwhile, forming a higher percentage of M-O bonds can lead to better dielectric properties for the device. Based on the data in Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(e), it is evident that the concentration of M-O bonds rises as the annealing temperature increases. The presence of M-OH bonds diminishes as the annealing temperature rises, as indicated in Table\u0026nbsp;\u003cspan refid=\"Tab1\" class=\"InternalRef\"\u003e1\u003c/span\u003e. This phenomenon can be attributed to the increase in temperature leading to thermal condensation within the La-OH and Al-OH bond films, gradually transforming them into La -O and Al-O bonds. Consequently, this results in an increased coordination number of metal ions, thereby facilitating the bonding of metal ions with oxygen ions. It can also be seen that as the annealing temperature increases to 800\u0026deg;C, the fitted O1s peak shifts to the direction of high binding energy, indicating that LaAlO\u003csub\u003ex\u003c/sub\u003e is fully oxidized and more silicate layers are formed, which will adversely affect the dielectric properties of Al/LaAlO\u003csub\u003ex\u003c/sub\u003e/Si/Al MOS capacitors.\u003c/p\u003e \u003cp\u003eFigure \u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(f) illustrates the La 3d spectra of LaAlOx thin films at various annealing temperatures. The spectra display a central peak (La 3d\u003csub\u003e5/2\u003c/sub\u003e) and a spin-splitting peak (La 3d\u003csub\u003e3/2\u003c/sub\u003e), with energy differences of approximately 16.80, 16.80, 16.90, and 17.00 eV from 500 to 800\u0026deg;C. Based on the available literature, it has been observed that the splitting energies of La3d\u003csub\u003e3/2\u003c/sub\u003e and La3d\u003csub\u003e5/2\u003c/sub\u003e are approximately 16.80 eV, indicating the presence of the La\u0026thinsp;+\u0026thinsp;state. [\u003cspan citationid=\"CR30\" class=\"CitationRef\"\u003e30\u003c/span\u003e]. At 700\u0026deg;C, the movement of the peaks towards lower binding energies suggests the existence of O-La-O bonds within the LaAlO\u003csub\u003ex\u003c/sub\u003e films. However, with an increase in temperature to 800\u0026deg;C, there is a shift in binding energy towards higher values due to the close proximity of the La silicate layer to the interface with the Si substrate [\u003cspan citationid=\"CR14\" class=\"CitationRef\"\u003e14\u003c/span\u003e].\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003e \u003cdiv class=\"gridtable\"\u003e\u003ctable float=\"Yes\" id=\"Tab1\" border=\"1\"\u003e \u003ccaption language=\"En\"\u003e \u003cdiv class=\"CaptionNumber\"\u003eTable 1\u003c/div\u003e \u003cdiv class=\"CaptionContent\"\u003e \u003cp\u003eCorresponding peak positions, half-height widths, and content percentages of each component of LaAlO\u003csub\u003ex\u003c/sub\u003e gate dielectric films O 1s\u003c/p\u003e \u003c/div\u003e \u003c/caption\u003e \u003ccolgroup cols=\"9\"\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c1\" colnum=\"1\"\u003e\u003c/div\u003e \u003cdiv align=\"char\" char=\".\" class=\"colspec\" colname=\"c2\" colnum=\"2\"\u003e\u003c/div\u003e \u003cdiv align=\"char\" char=\".\" class=\"colspec\" colname=\"c3\" colnum=\"3\"\u003e\u003c/div\u003e \u003cdiv align=\"char\" char=\".\" class=\"colspec\" colname=\"c4\" colnum=\"4\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c5\" colnum=\"5\"\u003e\u003c/div\u003e \u003cdiv align=\"char\" char=\".\" class=\"colspec\" colname=\"c6\" colnum=\"6\"\u003e\u003c/div\u003e \u003cdiv align=\"char\" char=\".\" class=\"colspec\" colname=\"c7\" colnum=\"7\"\u003e\u003c/div\u003e \u003cdiv align=\"char\" char=\".\" class=\"colspec\" colname=\"c8\" colnum=\"8\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c9\" colnum=\"9\"\u003e\u003c/div\u003e \u003cthead\u003e \u003ctr\u003e \u003cth align=\"left\" colname=\"c1\" morerows=\"1\" rowspan=\"2\"\u003e \u003cp\u003eTemperature\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c2\"\u003e\u0026nbsp;\u003c/th\u003e \u003cth align=\"left\" colname=\"c3\"\u003e \u003cp\u003eM-O\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c4\"\u003e\u0026nbsp;\u003c/th\u003e \u003cth align=\"left\" colname=\"c5\"\u003e\u0026nbsp;\u003c/th\u003e \u003cth align=\"left\" colname=\"c6\"\u003e\u0026nbsp;\u003c/th\u003e \u003cth align=\"left\" colname=\"c7\"\u003e \u003cp\u003eVo\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c8\"\u003e\u0026nbsp;\u003c/th\u003e \u003cth align=\"left\" colname=\"c9\"\u003e\u0026nbsp;\u003c/th\u003e \u003c/tr\u003e \u003ctr\u003e \u003cth align=\"left\" colname=\"c2\"\u003e \u003cp\u003ePeak position\u003c/p\u003e \u003cp\u003e(eV)\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c3\"\u003e \u003cp\u003eFWHM\u003c/p\u003e \u003cp\u003e(eV)\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c4\"\u003e \u003cp\u003eContent percentage\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c5\"\u003e\u0026nbsp;\u003c/th\u003e \u003cth align=\"left\" colname=\"c6\"\u003e \u003cp\u003ePeak position\u003c/p\u003e \u003cp\u003e(eV)\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c7\"\u003e \u003cp\u003eFWHM\u003c/p\u003e \u003cp\u003e(eV)\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c8\"\u003e \u003cp\u003eContent percentage\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c9\"\u003e\u0026nbsp;\u003c/th\u003e \u003c/tr\u003e \u003c/thead\u003e \u003ctbody\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003e500℃\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c2\"\u003e \u003cp\u003e529.97\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c3\"\u003e \u003cp\u003e2.29\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c4\"\u003e \u003cp\u003e74.6%\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e\u0026nbsp;\u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c6\"\u003e \u003cp\u003e531.32\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c7\"\u003e \u003cp\u003e1.77\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c8\"\u003e \u003cp\u003e25.4%\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c9\"\u003e\u0026nbsp;\u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003e600℃\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c2\"\u003e \u003cp\u003e530.03\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c3\"\u003e \u003cp\u003e2.18\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c4\"\u003e \u003cp\u003e78.7%\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e\u0026nbsp;\u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c6\"\u003e \u003cp\u003e531.46\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c7\"\u003e \u003cp\u003e1.68\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c8\"\u003e \u003cp\u003e21.3%\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c9\"\u003e\u0026nbsp;\u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003e700℃\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c2\"\u003e \u003cp\u003e529.47\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c3\"\u003e \u003cp\u003e2.51\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c4\"\u003e \u003cp\u003e83.3%\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e\u0026nbsp;\u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c6\"\u003e \u003cp\u003e531.04\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c7\"\u003e \u003cp\u003e2.02\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c8\"\u003e \u003cp\u003e16.7%\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c9\"\u003e\u0026nbsp;\u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003e800℃\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c2\"\u003e \u003cp\u003e529.89\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c3\"\u003e \u003cp\u003e2.5\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c4\"\u003e \u003cp\u003e87.7%\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e\u0026nbsp;\u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c6\"\u003e \u003cp\u003e531.57\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c7\"\u003e \u003cp\u003e2.24\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c8\"\u003e \u003cp\u003e12.3%\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c9\"\u003e\u0026nbsp;\u003c/td\u003e \u003c/tr\u003e \u003c/tbody\u003e \u003c/colgroup\u003e \u003c/table\u003e\u003c/div\u003e \u003cp\u003eMOS capacitors were fabricated using Al/LaAlO\u003csub\u003ex\u003c/sub\u003e/Si/Al structure, where Al top electrodes with an area of 7.068\u0026times;10\u003csup\u003e\u0026minus;\u0026thinsp;4\u003c/sup\u003e cm\u003csup\u003e2\u003c/sup\u003e were deposited on the LaAlO\u003csub\u003ex\u003c/sub\u003e gate dielectric film via magnetron sputtering under shadowing, and Al back electrodes with the same thickness were applied to the backside of the silicon substrate. Figure\u0026nbsp;\u003cspan refid=\"Fig7\" class=\"InternalRef\"\u003e7\u003c/span\u003e shows the variation curves of high-frequency (1 MHz) capacitance-voltage (C-V) with annealing temperature for the LaAlO\u003csub\u003ex\u003c/sub\u003e gate-dielectric MOS capacitor with double-sweeping in the range of \u0026plusmn;\u0026thinsp;8 V gate voltage. It is evident that the accumulated capacitance \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{\\text{C}}_{\\text{o}\\text{x}}\\)\u003c/span\u003e\u003c/span\u003e exhibits a clear pattern of change as the annealing temperature increases. Initially, it rises with the annealing temperature, peaks at 700\u0026deg;C, and subsequently declines. The accumulated capacitances of LaAlO\u003csub\u003ex\u003c/sub\u003e are 245.01, 332.31, 365.82, and 353.27 pF, respectively. By Eq.\u0026nbsp;[\u003cspan citationid=\"CR31\" class=\"CitationRef\"\u003e31\u003c/span\u003e]:\u003c/p\u003e \u003cdiv id=\"Equa\" class=\"Equation\"\u003e \u003cdiv format=\"TEX\" class=\"mathdisplay\" id=\"FileID_Equa\" name=\"EquationSource\"\u003e\n$$\\:\\text{k}=\\frac{{\\text{C}}_{\\text{o}\\text{x}}\\text{d}}{{{\\epsilon\\:}}_{0}\\text{A}}$$\u003c/div\u003e \u003c/div\u003e \u003c/p\u003e \u003cp\u003eWhere \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{\\text{C}}_{\\text{o}\\text{x}}\\)\u003c/span\u003e\u003c/span\u003e is the accumulated capacitance, d is the film thickness, \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{{\\epsilon\\:}}_{0}\\)\u003c/span\u003e\u003c/span\u003e is the vacuum dielectric constant (\u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{{\\epsilon\\:}}_{0}\\)\u003c/span\u003e\u003c/span\u003e=8.854\u0026times;10\u003csup\u003e\u0026minus;\u0026thinsp;12\u003c/sup\u003e F/m). The dielectric constants (k) of the samples annealed at 500\u0026deg;C, 600\u0026deg;C, 700\u0026deg;C, and 800\u0026deg;C were determined to be 15.73, 21.35, 20.91, and 20.79 respectively based on the area of the Al top electrode (A). The findings indicate that the effective dielectric constant (k) of the LaAlOx gate dielectric shifts from 15.73 for the annealed sample at 500\u0026deg;C to 20.79 for the annealed sample at 800\u0026deg;C, potentially attributed to the rise in annealing temperature. According to the XPS analysis, it is apparent that elevating the annealing temperature improves the interface quality and suppresses the expansion of low-k SiO\u003csub\u003ex\u003c/sub\u003e interlayer [\u003cspan citationid=\"CR32\" class=\"CitationRef\"\u003e32\u003c/span\u003e].\u003c/p\u003e \u003cp\u003eFurthermore, the flat-band capacitance (\u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{\\text{C}}_{\\text{f}\\text{b}}\\)\u003c/span\u003e\u003c/span\u003e) of the sample was used to calculate the \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{\\text{V}}_{\\text{f}\\text{b}}\\)\u003c/span\u003e\u003c/span\u003e, the EOT, the \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{\\text{Q}}_{\\text{o}\\text{x}}\\)\u003c/span\u003e\u003c/span\u003eand the electrical parameters such as the\u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:\\varDelta\\:{\\text{V}}_{\\text{f}\\text{b}}\\)\u003c/span\u003e\u003c/span\u003e, and the \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{\\text{N}}_{\\text{b}\\text{t}}\\)\u003c/span\u003e\u003c/span\u003e in Table\u0026nbsp;\u003cspan refid=\"Tab2\" class=\"InternalRef\"\u003e2\u003c/span\u003e. The \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{\\text{V}}_{\\text{f}\\text{b}}\\)\u003c/span\u003e\u003c/span\u003e is associated with the oxide charge density, while the hysteresis is linked to the boundary-trap oxide charge density.\u003c/p\u003e \u003cp\u003e \u003cdiv class=\"gridtable\"\u003e\u003ctable float=\"Yes\" id=\"Tab2\" border=\"1\"\u003e \u003ccaption language=\"En\"\u003e \u003cdiv class=\"CaptionNumber\"\u003eTable 2\u003c/div\u003e \u003cdiv class=\"CaptionContent\"\u003e \u003cp\u003eElectrical properties derived from C-V and I-V characteristics\u003c/p\u003e \u003c/div\u003e \u003c/caption\u003e \u003ccolgroup cols=\"10\"\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c1\" colnum=\"1\"\u003e\u003c/div\u003e \u003cdiv align=\"char\" char=\".\" class=\"colspec\" colname=\"c2\" colnum=\"2\"\u003e\u003c/div\u003e \u003cdiv align=\"char\" char=\".\" class=\"colspec\" colname=\"c3\" colnum=\"3\"\u003e\u003c/div\u003e \u003cdiv align=\"char\" char=\".\" class=\"colspec\" colname=\"c4\" colnum=\"4\"\u003e\u003c/div\u003e \u003cdiv align=\"char\" char=\".\" class=\"colspec\" colname=\"c5\" colnum=\"5\"\u003e\u003c/div\u003e \u003cdiv align=\"char\" char=\".\" class=\"colspec\" colname=\"c6\" colnum=\"6\"\u003e\u003c/div\u003e \u003cdiv align=\"char\" char=\".\" class=\"colspec\" colname=\"c7\" colnum=\"7\"\u003e\u003c/div\u003e \u003cdiv align=\"char\" char=\"\u0026times;\" class=\"colspec\" colname=\"c8\" colnum=\"8\"\u003e\u003c/div\u003e \u003cdiv align=\"char\" char=\"\u0026times;\" class=\"colspec\" colname=\"c9\" colnum=\"9\"\u003e\u003c/div\u003e \u003cdiv align=\"char\" char=\"\u0026times;\" class=\"colspec\" colname=\"c10\" colnum=\"10\"\u003e\u003c/div\u003e \u003cthead\u003e \u003ctr\u003e \u003cth align=\"left\" colname=\"c1\"\u003e \u003cp\u003eAnnealing\u003c/p\u003e \u003cp\u003eTemperature\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c2\"\u003e \u003cp\u003ek\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c3\"\u003e \u003cp\u003e\u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:EOT\\left(nm\\right)\\)\u003c/span\u003e\u003c/span\u003e\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c4\"\u003e \u003cp\u003e\u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{C}_{ox}\\left(pF\\right)\\)\u003c/span\u003e\u003c/span\u003e\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c5\"\u003e \u003cp\u003e\u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{C}_{fb}\\left(pF\\right)\\)\u003c/span\u003e\u003c/span\u003e\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c6\"\u003e \u003cp\u003e\u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{V}_{fb}\\)\u003c/span\u003e\u003c/span\u003e\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c7\"\u003e \u003cp\u003e\u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:\\varDelta\\:{V}_{fb}\\)\u003c/span\u003e\u003c/span\u003e\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c8\"\u003e \u003cp\u003e\u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{Q}_{ox}\\left({cm}^{-2}\\right)\\)\u003c/span\u003e\u003c/span\u003e\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c9\"\u003e \u003cp\u003e\u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{N}_{bt}\\left({cm}^{-2}\\right)\\)\u003c/span\u003e\u003c/span\u003e\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c10\"\u003e \u003cp\u003e\u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{J}_{g}\\left({A/cm}^{2}\\right)\\)\u003c/span\u003e\u003c/span\u003e\u003c/p\u003e \u003c/th\u003e \u003c/tr\u003e \u003c/thead\u003e \u003ctbody\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003e500℃\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c2\"\u003e \u003cp\u003e15.74\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c3\"\u003e \u003cp\u003e9.96\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c4\"\u003e \u003cp\u003e245.01\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c5\"\u003e \u003cp\u003e61.09\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c6\"\u003e \u003cp\u003e-0.32\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c7\"\u003e \u003cp\u003e1.28\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\"\u0026times;\" colname=\"c8\"\u003e \u003cp\u003e1.04\u0026times;10\u003csup\u003e12\u003c/sup\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\"\u0026times;\" colname=\"c9\"\u003e \u003cp\u003e2.77\u0026times;10\u003csup\u003e12\u003c/sup\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\"\u0026times;\" colname=\"c10\"\u003e \u003cp\u003e1.39\u0026times;10\u003csup\u003e\u0026minus;\u0026thinsp;1\u003c/sup\u003e\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003e600℃\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c2\"\u003e \u003cp\u003e21.35\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c3\"\u003e \u003cp\u003e7.34\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c4\"\u003e \u003cp\u003e332.31\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c5\"\u003e \u003cp\u003e49.23\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c6\"\u003e \u003cp\u003e-0.72\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c7\"\u003e \u003cp\u003e0.32\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\"\u0026times;\" colname=\"c8\"\u003e \u003cp\u003e2.35\u0026times;10\u003csup\u003e11\u003c/sup\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\"\u0026times;\" colname=\"c9\"\u003e \u003cp\u003e9.40\u0026times;10\u003csup\u003e11\u003c/sup\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\"\u0026times;\" colname=\"c10\"\u003e \u003cp\u003e2.17\u0026times;10\u003csup\u003e\u0026minus;\u0026thinsp;2\u003c/sup\u003e\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003e700℃\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c2\"\u003e \u003cp\u003e20.91\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c3\"\u003e \u003cp\u003e6.67\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c4\"\u003e \u003cp\u003e365.82\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c5\"\u003e \u003cp\u003e44.88\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c6\"\u003e \u003cp\u003e-0.24\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c7\"\u003e \u003cp\u003e0.16\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\"\u0026times;\" colname=\"c8\"\u003e \u003cp\u003e1.81\u0026times;10\u003csup\u003e12\u003c/sup\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\"\u0026times;\" colname=\"c9\"\u003e \u003cp\u003e5.17\u0026times;10\u003csup\u003e11\u003c/sup\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\"\u0026times;\" colname=\"c10\"\u003e \u003cp\u003e3.54\u0026times;10\u003csup\u003e\u0026minus;\u003c/sup\u003e3\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003e800℃\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c2\"\u003e \u003cp\u003e20.79\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c3\"\u003e \u003cp\u003e6.91\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c4\"\u003e \u003cp\u003e353.27\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c5\"\u003e \u003cp\u003e40.84\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c6\"\u003e \u003cp\u003e-0.08\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c7\"\u003e \u003cp\u003e0.16\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\"\u0026times;\" colname=\"c8\"\u003e \u003cp\u003e2.29\u0026times;10\u003csup\u003e12\u003c/sup\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\"\u0026times;\" colname=\"c9\"\u003e \u003cp\u003e4.99\u0026times;10\u003csup\u003e11\u003c/sup\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\"\u0026times;\" colname=\"c10\"\u003e \u003cp\u003e8.84\u0026times;10\u003csup\u003e\u0026minus;\u0026thinsp;3\u003c/sup\u003e\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003c/tbody\u003e \u003c/colgroup\u003e \u003c/table\u003e\u003c/div\u003e \u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eThe absolute value of \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{\\text{V}}_{\\text{f}\\text{b}}\\)\u003c/span\u003e\u003c/span\u003e decreases as the annealing temperature increases. Films annealed at high temperatures exhibit reduced defects and traps, resulting in improved interface quality compared to films annealed at low temperatures. It is clear from Fig.\u0026nbsp;\u003cspan refid=\"Fig7\" class=\"InternalRef\"\u003e7\u003c/span\u003e and Table\u0026nbsp;\u003cspan refid=\"Tab2\" class=\"InternalRef\"\u003e2\u003c/span\u003e that the LaAlO\u003csub\u003ex\u003c/sub\u003e films annealed at 700\u0026deg;C have less hysteresis. It can be inferred that the hysteresis phenomenon is connected to the trapping of oxygen charges at the boundary, which indicates that the interface properties of the doped lanthanum alumina thin film have been enhanced with the increase of annealing temperature. At a gate voltage of 1 V the I-V characteristics depicted in Fig.\u0026nbsp;\u003cspan refid=\"Fig9\" class=\"InternalRef\"\u003e8\u003c/span\u003e indicate that the LaAlO\u003csub\u003ex\u003c/sub\u003e films annealed at 700\u0026deg;C exhibit a minimum leakage current density of 3.54 \u0026times; 10\u003csup\u003e\u0026minus;\u0026thinsp;3\u003c/sup\u003e A/cm\u003csup\u003e2\u003c/sup\u003e. Raising the annealing temperature results in a higher surface density of the samples and improved adhesion of the film surface, leading to effectively reduced interfacial density of states and traps. The increase in \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{\\text{Q}}_{\\text{o}\\text{x}}\\)\u003c/span\u003e\u003c/span\u003e values with rising annealing temperature may be attributed to the generation of oxygen vacancies in the film caused by higher annealing temperatures. The \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{\\text{N}}_{\\text{b}\\text{t}}\\)\u003c/span\u003e\u003c/span\u003e values of samples annealed at higher temperatures appear to be relatively smaller compared to those annealed at 500\u0026deg;C. This could be attributed to the enhanced formation of denser gate dielectric films and higher-quality interfaces facilitated by the elevated annealing temperatures [\u003cspan citationid=\"CR20\" class=\"CitationRef\"\u003e20\u003c/span\u003e].\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eNevertheless, as the annealing temperature was raised to 800\u0026deg;C, there was a noticeable rise in the leakage current density of the films. The findings suggest the electrical performances of LaAlO\u003csub\u003ex\u003c/sub\u003e films are optimal when annealed at 700\u0026deg;C.\u003c/p\u003e \u003c/div\u003e"},{"header":"4 Conclusion","content":"\u003cp\u003eIn brief, we conducted a systematic investigation into the impact of varying annealing temperatures on the RMS, interfacial and electrical properties of LaAlO\u003csub\u003ex\u003c/sub\u003e high-k gate dielectric thin films prepared using the solution method. At 700\u0026deg;C, the RMS was minimized and the film's surface exhibited smoothness. XPS analysis reveals that the bonding between metal and oxygen increases while the bonding between metal and hydroxyl decreases with increasing annealing temperature. This suggests that the introduction of Al effectively suppresses the moisture absorption of La\u003csub\u003e2\u003c/sub\u003eO\u003csub\u003e3\u003c/sub\u003e, thereby preventing the formation of low-k SiO\u003csub\u003ex\u003c/sub\u003e and enhancing the interface quality between the dielectric film and Si substrate. At the same time, this enhances the dielectric properties of the Al/LaAlO\u003csub\u003ex\u003c/sub\u003e/Si/Al MOS capacitors. A semiconductor device analyzer found that higher annealing temperatures lead to an increase in the accumulated capacitance \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{\\text{C}}_{\\text{o}\\text{x}}\\)\u003c/span\u003e\u003c/span\u003e, resulting in a higher k value. Additionally, as the annealing temperature increases, the \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{N}_{bt}\\)\u003c/span\u003e\u003c/span\u003evalue decreases progressively due to the facilitation of denser gate dielectric film formation and improved interface quality. Raising the annealing temperature also leads to a decrease in leakage current density, with the lowest recorded value of 3.54\u0026times;10\u003csup\u003e\u0026minus;\u0026thinsp;3\u003c/sup\u003e A/cm\u003csup\u003e2\u003c/sup\u003e observed at 700\u0026deg;C. In general, LaAlO\u003csub\u003ex\u003c/sub\u003e films annealed at 700\u0026deg;C demonstrate outstanding characteristics attributed to enhanced interfacial chemistry and electrical properties, positioning them as potential choices for upcoming high-k gate dielectrics.\u003c/p\u003e"},{"header":"Declarations","content":"\u003ch2\u003eFunding\u003c/h2\u003e \u003cp\u003eThis research was supported by the Natural Science Foundation of Xinjiang Uygur Autonomous Region (2021D01C035)\u003c/p\u003e\u003ch2\u003eAuthor Contribution\u003c/h2\u003e\u003cp\u003eZhenhua Huang:A Kamale Tuokedaerhan: B Linyu Yang:C Chaozhong Guo:D Zhengang Cai:E Margulan Ibraimov:F Serikbek Sailanbek: GA: Writing \u0026ndash; review \u0026amp; editing, Writing \u0026ndash; original draft, Methodology, Investigation, Data curation. B:Supervision, Resources, Funding acquisition, Conceptualization.C: Supervision, Resources. D and E: Methodology, Formal analysis. F adn G: Resources.All authors reviewed the manuscript.\u003c/p\u003e\u003ch2\u003eAcknowledgments\u003c/h2\u003e \u003cp\u003eThis research was supported by the Natural Science Foundation of Xinjiang Uygur Autonomous Region (2021D01C035)\u003c/p\u003e"},{"header":"References","content":"\u003col\u003e\u003cli\u003e\u003cspan\u003ePrakash, P., K. Mohana Sundaram, and M. Anto Bennet, \u003cem\u003eA review on carbon nanotube field effect transistors (CNTFETs) for ultra-low power applications\u003c/em\u003e. Renewable and Sustainable Energy Reviews, 2018. 89: p. 194\u0026ndash;203. \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003ehttps://doi.org/10.1016/j.rser.2018.03.021\u003c/span\u003e\u003cspan address=\"10.1016/j.rser.2018.03.021\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eHe, G., X. Chen, and Z. Sun, \u003cem\u003eInterface engineering and chemistry of Hf-based high-k dielectrics on III\u0026ndash;V substrates\u003c/em\u003e. Surface Science Reports, 2013. 68(1): p. 68\u0026ndash;107. \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003ehttps://doi.org/10.1016/j.surfrep.2013.01.002\u003c/span\u003e\u003cspan address=\"10.1016/j.surfrep.2013.01.002\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eRatnesh, R.K., A. Goel, G. Kaushik, H. Garg, Chandan, M. Singh, and B. Prasad, \u003cem\u003eAdvancement and challenges in MOSFET scaling\u003c/em\u003e. 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Journal of Alloys and Compounds, 2017. 699: p. 415\u0026ndash;420. \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003ehttps://doi.org/10.1016/j.jallcom.2016.12.376\u003c/span\u003e\u003cspan address=\"10.1016/j.jallcom.2016.12.376\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e\u003c/span\u003e\u003c/li\u003e\u003c/ol\u003e"}],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":true,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":true,"highlight":"","institution":"","isAcceptedByJournal":false,"isAuthorSuppliedPdf":false,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":false,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"La2O3, sol-gel method, gate dielectric thin films, MOS capacitors","lastPublishedDoi":"10.21203/rs.3.rs-4984081/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-4984081/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eIn recent years, there has been growing interest in the exploration of rare earth oxides for their potential as high-k gate dielectrics. Lanthanum oxide (La\u003csub\u003e2\u003c/sub\u003eO\u003csub\u003e3\u003c/sub\u003e) has emerged as a particularly noteworthy candidate due to its impressive dielectric properties, wide bandgap, strong thermodynamic stability, and remarkable compatibility with silicon substrates. However, La\u003csub\u003e2\u003c/sub\u003eO\u003csub\u003e3\u003c/sub\u003e has a significant problem for MOS device applications due to its hygroscopicity and low crystallization temperature, making it unsuitable for high-temperature treatment during fabrication. To improve its oxide quality, it can be doped. Al-doped La\u003csub\u003e2\u003c/sub\u003eO\u003csub\u003e3\u003c/sub\u003e (LaAlO\u003csub\u003ex\u003c/sub\u003e) thin films annealed at different temperatures were prepared on n-type Si substrates by sol-gel method and the effect of temperature variation on LaAlOx thin films as gate dielectrics were investigated in terms of root-mean-square, interfacial properties, and electrical properties. The findings indicate that the introduction of Al doping raises the crystallization temperature of La\u003csub\u003e2\u003c/sub\u003eO\u003csub\u003e3\u003c/sub\u003e. Additionally, it was observed that the root-mean-square roughness of the LaAlOx films decreases from 0.919 nm to 0.320 nm with an increase in annealing temperature from 500 to 700°C. XPS has the capability to assess the interfacial characteristics of LaAlO\u003csub\u003ex\u003c/sub\u003e. It is evident that elevated temperatures promote the formation of M-O bonds, diminish film defects, and enhance the overall interfacial quality of the film. In addition, analyzed the electrical properties of the Al/ LaAlO\u003csub\u003ex\u003c/sub\u003e/Si/Al metal-oxide-semiconductor capacitors The findings indicate that the samples annealed at 700°C exhibit favorable electrical characteristics, demonstrating a dielectric constant of 20.91 under a gate voltage of 1 V and a leakage current density of 3.54×10\u003csup\u003e− 3\u003c/sup\u003eA/cm\u003csup\u003e2\u003c/sup\u003e.\u003c/p\u003e","manuscriptTitle":"The performance of LaAlO x gate dielectric films prepared by sol-gel method at different temperatures of annealing","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2024-09-30 11:54:03","doi":"10.21203/rs.3.rs-4984081/v1","editorialEvents":[{"type":"communityComments","content":0}],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true}}],"origin":"","ownerIdentity":"5dc32fd1-db00-4d26-b14c-2453fd9f68c6","owner":[],"postedDate":"September 30th, 2024","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"posted","subjectAreas":[],"tags":[],"updatedAt":"2024-10-08T02:54:00+00:00","versionOfRecord":[],"versionCreatedAt":"2024-09-30 11:54:03","video":"","vorDoi":"","vorDoiUrl":"","workflowStages":[]},"version":"v1","identity":"rs-4984081","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-4984081","identity":"rs-4984081","version":["v1"]},"buildId":"qtupq5eGEP_6zYnWcrvyt","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}