Homojunction-loaded inverters based on self-biased molybdenum disulfide transistors for sub-picowatt computing

Homojunction-loaded inverters based on self-biased molybdenum disulfide transistors for sub-picowatt computing | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Article Homojunction-loaded inverters based on self-biased molybdenum disulfide transistors for sub-picowatt computing Yue Zhang, Xiaofu Wei, Xiankun Zhang, Huihui Yu, Li Gao, Wenhui Tang, and 4 more This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-2502301/v1 This work is licensed under a CC BY 4.0 License Status: Published Journal Publication published 08 Jan, 2024 Read the published version in Nature Electronics → Version 1 posted You are reading this latest preprint version Abstract As transistors are scaled to smaller dimensions their static power increases. Combining two-dimensional (2D) channel materials with complementary metal–oxide–semiconductor (CMOS) logic architectures could be an effective solution to this issue due to the excellent field-effect properties of 2D materials. However, 2D materials have limited polarity control. Here, we report a pseudo-CMOS architecture for sub-picowatt logic computing that uses self-biased molybdenum disulfide transistors. The transistors have a gapped channel that forms a tunable barrier — thus circumventing the polarity control of 2D materials — and exhibit a reverse saturation current below 1 pA with high reliability and endurance. We use the devices to make homojunction-loaded inverters with good rail-to-rail operation at a switching threshold voltage of around 0.5 V, a static power of a few picowatts, a dynamic delay time of around 200 µs, a noise margin over 90%, and a peak voltage gain of 241. Additionally, fundamental gate circuits based on this pseudo-CMOS configuration are fabricated by integrating more devices. Physical sciences/Materials science/Materials for devices/Electronic devices Physical sciences/Materials science/Nanoscale materials/Two-dimensional materials Physical sciences/Engineering/Electrical and electronic engineering Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Introduction Critical to the development of integrated circuits (ICs) with high device density are transistors that use less power 1 , 2 . As the dimensions of silicon-based transistors are reduced, the static power advantages of the complementary metal–oxide–semiconductor (CMOS) architecture are lost due to increased leakage currents 3 , 4 . Reducing static power consumption caused by leakage current is thus essential to limiting power rise (nearly 30 nanowatts per unit now currently exceeds 40% of the total power 5 , 6 . One approach to address this problem is to use two-dimensional (2D) materials, such as molybdenum disulfide (MoS 2 ), because they have excellent field-effect properties 7 – 11 . However, the doping technology for silicon-based CMOS is too high-energy for atomically thin 2D materials 12 , meaning the potential of 2D materials-based ICs has not yet been fully realized 13 – 16 . Two main strategies have been developed to create 2D materials-based CMOS logic architecture composed of p-type field effect transistor (p-FET) and n-type field effect transistor (n-FET) pairs (Fig. 1 a). The first is to control the polarity of transistors (by contact engineering 17 , electrostatic doping 18 , 19 , and mild doping methods 20 , 21 ) to change the majority carrier types. But stable and precise technique towards practical circuit-level manufacture with low power and high performance still lacks due to the limited polarity control of ultra-thin 2D materials. The second strategy is to use two channel materials with different majority carrier types to realize CMOS logic functions 22 , 23 . However, the static current in the circuit is not completely suppressed due to the unbalanced carrier transport of transistor pairs. Therefore, most 2D large-scale logic circuits currently still follow earlier pseudo-n-type metal–oxide–semiconductor (pseudo-NMOS) architectures 24 – 26 composed of single-polarity transistors as the load and the driver (Fig. 1 b), which have higher static power than CMOS. In this work, we report a homojunction-loaded inverter composed of 2D self-biased transistor (SBT) as the load and 2D n-FET as the driver (Fig. 1 c). Compared with pseudo-NMOS and CMOS, this architecture, which well called pseudo-CMOS, circumvents the polarity control of transistors and greatly reduces static power (Fig. 1 d). The SBT is built by introducing a gap in the monolayer MoS 2 channel to form a homojunction, and its structure features is characterized by cross-section transmission electron microscopy (TEM), in-situ Kelvin probe force microscopy (KPFM), and photoluminescence spectroscopy (PL). Since the homogeneous SBT can timely cut off the current path of inverters when the n-FET is on, there is almost no static current flow in the circuit, achieving picowatt-level static power (Fig. 1 e). The dynamic switching behavior is analyzed using a square wave input signal. We also implement other Boolean logic functions — including XOR, AND, NAND, NOR, and OR gates — with voltage-level matching based on this pseudo-CMOS configuration. Structure and characterization of the homojunction Figure 2 a presents an idealized device structure of the doping-free homojunction with a gapped channel near the double-acting electrode, which served as both source-drain and gate. Monolayer MoS 2 grown by CVD is chosen as the channel material to fabricate devices. The thickness of MoS 2 is ~ 0.8 nm measured by atomic force microscopy (AFM), indicating the MoS 2 flake is a single layer (Supplementary Fig. 1c). The Raman spectra and PL spectrum of MoS 2 are shown in Supplementary Fig. 1d-e, and the conclusions are consistent with the results of the AFM. To confirm the unique device structure of this homojunction, a representative sample after fabrication is characterized by high-resolution TEM, showing the profile of the core region. An energy-dispersive spectrometer (EDS) is also used to confirm the material composition of the core region (Fig. 2 a and Supplementary Fig. 2). In our demonstration, the Cr/Au (10/50 nm) as the source contact is made on the MoS 2 , and hexagonal boron nitride (h-BN) flakes are used as dielectric layers. The extended electrode serves as both the drain and gate contact to complete the device fabrication (Fig. 2 b). Noteworthy, an eye-catching gap is left under the monolayer MoS 2 channel near the extended drain, creating a homojunction that can benefit from the self-biased effect. The signature structure feature of this homojunction is that the drain not only provides the biased voltage but also works as the gate to realize a barrier-tunable current path. The detailed fabrication process can be seen in the Methods and Supplementary Fig. 3. To demonstrate the self-biased effect of this homojunction, we perform in-situ KPFM experiments to map the potential distribution of the dashed square (Fig. 2 b). The measurement configuration enables us to spatially map the potential distribution of the core region under different bias conditions. Figure 2 c and Supplementary Fig. 4 show the KPFM mapping (upper part) and the corresponding averaged contact potential difference ( V CPD ) profile (lower part) of the selected area at the bias voltages V bias = -1 V, 0 V, and 1 V, respectively. A sharp potential mutation occurs at the gapped channel position after a bias voltage is applied, and the potential difference becomes more obvious as the bias voltage increases (Supplementary Fig. 5). It should be noted here that electrons, as the majority carriers in the channel, dominate the conductance of the device. Under positive bias voltage, a positive electrostatic field from the extended drain will implement electron doping to make the MoS 2 channel highly conductive, thus promoting the flow of electrons from the source to the drain. Under negative bias voltage, electrons are depleted in the channel due to a negative electrostatic doping from the drain, blocking the flow of electrons. As a result, the extended drain will simultaneously apply an electrostatic doping caused by this potential difference to tune the channel carrier concentration and form a bias-tunable homojunction at the gapped channel position. Subsequently, we perform monolayer MoS 2 in-situ PL spectrum characterization experiments under different bias conditions to further analyze the self-biased effect (Fig. 2 d and Supplementary Fig. 6). Here, we need to know that the PL intensity of the A exciton is highly dependent on electrostatic doping, while the A T trion is independent on electrostatic doping due to a largely trion binding energy 28 , and the A exciton will convert into the A T trion as the electron doping increases. Compared with V bias =0 V, the peak intensity of A exciton is significantly lower than that of A T trion at V bias = 1 V, indicating that there is an electron doping to further promote the transition from A exciton to A T trion. The peak intensity of A exciton is higher than that of A T trion at V bias = -1 V, indicating that there is a hole doping to deplete the excess electrons and thus inhibit the transition from A exciton to A T trion. Since the PL intensity of monolayer MoS 2 is dominated by the prominent A exciton, a PL intensity diminishment and a peak energy red-shift are observed at V bias = 1 V, while a significant PL intensity enhancement and a peak energy blue-shift are observed at V bias = -1 V (Supplementary Fig. 6b). The result is that this homojunction exhibits an obvious asymmetrical electrical transport behavior when the applied bias voltage is changed from positive to negative, as shown in Fig. 2 e. The I-V curve can be roughly divided into three regions: Ⅰ) reverse current saturation region; Ⅱ) forward ideal linear diode region; Ⅲ) forward series resistance-dominant region. An ideality factor ( n ) for evaluating the rectification performance of the homojunction can be calculated by fitting the Shockley diode Eq. 2 9,30 . $${I}_{ds}={I}_{s}\left[exp\left(\frac{{V}_{ds}}{n{V}_{T}}\right)-1\right]$$ where the V T and I s are defined as the thermal voltage and reverse saturation current, respectively. A near-unity ideality factor of ~ 1.1 ( n = 1 is ideal) can be obtained due to the rapid increase of current in region Ⅱ under forward bias (0.02–0.25 V), indicating excellent rectification performance. Then, we explore the electrostatic self-biased effect of the homojunction under special bias mode and a higher bias voltage (Supplementary Fig. 7). The results show that the device is on when the extended drain has a positive potential relative to the source, which is defined as forward bias. Conversely, the device is off when the extended drain has a negative potential relative to the source, which is defined as reverse bias. The excellent rectification characteristics of the homojunction have almost no degradation after 30 days in the atmospheric environment. And an ultrahigh rectification ratio of ~ 10 9 with an ultralow reverse saturation current below 1 pA is achieved with a bias range of ± 10 V. As a comparison, this value is far higher than previous reports based on 2D materials that have been developed 29 – 33 . This unique asymmetrical electrical behavior of the homojunction is attributed to the partially gapped MoS 2 channel and the electrostatic self-biased effect caused by the double-use extended electrode. Furthermore, we chose HfO 2 prepared by ALD instead of h-BN to demonstrate that the homojunction (SBT) is also suitable for other dielectric materials. The influence of HfO 2 thickness and channel length on the electrical transport properties of the SBT is systematically investigated, as shown in Supplementary Fig. 8. The size of the gap is mainly determined by the thickness of HfO 2 and the rectification characteristics of SBT have no degradation with the downscaling of the gap ( T HfO2 downscales to ≈ 15 nm). Even an improved rectification ratio is achieved, which may be attributed to the enhanced electrostatic doping as the thickness of HfO 2 decreases. Note that the off-current and on-current of SBT increase synchronously with the downscaling of the channel ( L ch downscales to < 300 nm). And an improved rectification characteristic is the fact that on-current increases more, which is attributed to lower gap effect on the channel resistance in the on-state. More importantly, the SBT exhibits very high stability, reliability, and endurance, which can be attributed to maintaining the integrity of the channel materials with an ingenious gap design, and the high stability of the grown MoS 2 itself. The SBT exhibits excellent rectification characteristics with negligible degradation at a square pulse bias signal for 10 Hz, even after 1,000 switching (on/off) cycles. Moreover, a retention time of about 10 years for steady operation is projected, and further details can be found in Supplementary Fig. 9. The robust rectification characteristics of HfO 2 -based SBT pave the way for fabricating low-power and high-performance logic circuits, as discussed in detail in the following section. Pseudo-CMOS logic inverter The inverter that outputs the opposite logic level (logic ‘0’ of low voltage and logic ‘1’ of high voltage) corresponding to its input is the most fundamental logic element that performs a Boolean operation. Different from the conventional CMOS inverter, we design a doping-free homojunction-loaded pseudo-CMOS inverter without different-polarity transistor pairs for high-performance and low-power logic computing (Fig. 3 a). First, the pseudo-CMOS inverter can be simply implemented on a monolayer MoS 2 channel by connecting one SBT as a switchable load and one n-FET as a driver in series. To achieve rail-to-rail output swing, the channel geometry is optimized by sizing the aspect ratio W/L (Fig. 3 b). Where W and L denote the width and length of the channels, is crucial, as it determines the switching threshold voltage V M of the inverter and thus the ability to cascade logic stages 24 , 26 . Figure 3 c shows the transfer curves of n-FETs with W/L ratios of ~ 16/2 and ~ 5/10, exhibiting obvious n-type unipolar transport behavior with a I on /I off ratio of > 10 8 and a desired subthreshold swing (SS) of ~ 0.1 V/dec. And the former (W/L ratios of ~ 16/2) current is > 10 times higher than the latter, demonstrating the feasibility of careful aspect ratio design. Thereby, we design the W/L ratios of SBT load and n-FET driver to be 16/2 and 5/10, respectively. The output characteristics of SBT and n-FET are depicted in Fig. 3 d, showing clear current saturation due to channel pinch-off. When the input voltage V in is approximately 0.5 V, the current value of the n-FET closely matches that of the SBT, indicating their almost equal resistance at this time. In the pseudo-CMOS inverter, the output voltage ( V out ) can be expressed as V out = V dd × R n−FET / ( R n−FET + R SBT ), where R n−FET and R SBT are the resistances of the n-FET driver and SBT load, respectively. As shown in Fig. 3 e, the n-FET driver is in high resistance mode at the input voltage V in = 0 V, and it should be noted that the SBT load is in a relatively low resistance mode ( V out almost equal to the supply voltage V dd ). As V in transits to 1 V, the driver is in low resistance mode while the SBT rapidly enters the saturated regime with V dd to V out voltage increases. The SBT starts in high resistance mode ( R SBT > > R n−FET ) due to the gapped channel and the V out is almost equal to ground ( V ss ), finishing the output switching. Figure 3 f shows the voltage transfer curve (VTC) of the pseudo-CMOS inverter. When the input voltage switches from 0 V to 1 V, the inverter exhibits a good rail-to-rail operation with a switching threshold voltage V M ≈ 0.5 V at V dd = 1 V, V ss = 0 V. Furthermore, a high noise margin (NM H ) of ~ 0.48 V and a low noise margin (NM L ) of ~ 0.46 V are extracted, and the total NM is greater than 90% of | V dd - V ss |, suggesting the high noise tolerance of the pseudo-CMOS inverter. The static power ( P static ) of an inverter can be expressed as P static = I static × V dd , where I static is the static current from V dd to V ss when the inverter operates in steady-state. Notably, a low peak static power of ~ 10 pW with a high peak voltage gain of 86 is calculated at V M ≈ 0.5 V (Fig. 3 f), which is important for low-power and high-performance logic computing. Moreover, a lower static power of sub-1 pW with a peak gain of 28 is achieved at V dd = 0.6 V (Supplementary Fig. 10), which is a record-low value compared with previous reports on 2D materials-based inverters (Supplementary Table 1). Note that low power may cause a loss in the operating speed of the pseudo-CMOS inverter. The dynamic switching behavior has been characterized using a square wave input signal with a voltage swing of 1 V at different AC frequencies and at V dd = 1 V (Supplementary Fig. 11). As demonstrated by the dynamic analysis, the inverter can immediately invert the input signal, and the output signal can maintain a high-quality waveform response that is opposite to the input signal at a relatively low frequency ( 5 kHz) mainly due to the RC delay in the circuit. RC delay can be obtained by analyzing the dynamic output switching curve of the inverter. The rising time delay (𝜏 𝑟 ) and falling time (𝜏 𝑓 ) here are defined as the time intervals between V 10% and V 90% 34, 35 . A 𝜏 𝑟 of ≈ 390 µs and a 𝜏 𝑓 of ≈ 20 µs are observed at 1 kHz, as shown in Fig. 3 g. We note that the 𝜏 𝑟 is around 20 times longer than 𝜏 𝑓 , which can be attributed to the higher intrinsic resistance of SBTs compared to n-FETs in on-state (Fig. 3 d). The average τ = (𝜏 𝑟 + 𝜏 𝑓 )/2 ≈ 205 µs, is similar to the values noted in previous reports on 2D-based CMOS inverters 18 , 35 , 36 , which can be attributed to the large device area and high parasitic capacitance from the overlap of the gate and drain 21 , 22 . Implementation of the pseudo-CMOS Boolean logic functions Compared to conventional pseudo-NMOS configuration, the gap design of pseudo-CMOS can greatly suppress static current in the inverter when the driver is on, thus achieving low-power logic computing. In detail, we perform the pseudo-CMOS inverter versus the conventional pseudo-NMOS inverter experiment under the same measurement conditions. Figure 4 a shows the schematic of the device used in the comparison experiment with the same monolayer MoS 2 and the same 20-nm-thick HfO 2 dielectric. To reduce the disturbance variable, two inverters share the same driver with W/L ratios of 5/10 and 16/2 for both load transistors (Fig. 4 b). And the transfer characteristic curves of all transistors (SBT load, n-FET load, and n-FET driver) are depicted in Supplementary Fig. 12, where V gs = V ds for SBT load and n-FET load. The VTCs of the pseudo-CMOS inverter show highly sharp voltage switching at V M ≈ 0.5 V with a full-swing output and a peak gain of up to 241 at V dd = 4 V (Fig. 4 c), which can be attributed to the switching point being in the steepest subthreshold region of the n-FET driver. In contrast, the pseudo-NMOS inverter also exhibits a full swing output with a V M ≈ 0.85 V, while the voltage gain decreases from 241 to 148 at V dd = 4 V (Fig. 4 d), which may be attributed to the switching point crossing the steepest subthreshold region. Notably, a low static current of < 20 pA is achieved (Supplementary Fig. 13), and the calculated peak static power of the pseudo-CMOS inverter is remarkably reduced from ~ 2.5 nW (for the pseudo-NMOS inverter) to ~ 7 pW at V dd = 0.5 V (Fig. 4 e). The improved static power is a consequence of the SBT having a higher high-resistance mode (> 10 10 Ω, while < 10 9 Ω for pseudo-NMOS load) when the shared n-FET driver is in low-resistance mode, as shown in Fig. 4 f. In principle, the gap design of SBT is to suppress static current in the circuit. When V ds = ( V out - V dd ) < 0 V, the gap barrier caused by the potential difference increases the resistance. However, it should be noted that the SBT is not always in high resistance mode due to the near-zero gap barrier ( V ds ≈ 0 V), which hardly affects the total resistance of the device (Fig. 1 c and Supplementary Fig. 14, energy band diagrams under two steady-states). When n-FET is in high resistance mode, SBT is in relatively low resistance mode to ensure full swing output logic ‘1’. When n-FET is in low resistance mode, SBT is in high resistance mode to ensure full swing output logic "0" and reduce static current in the circuit. As a result, there is no current path from V dd to V ss in two steady states, achieving ultralow static power. The dynamic switching behavior of two inverters is also investigated using a square wave input signal with a voltage swing of 4 V at V dd = 4 V for 1 kHz, as shown in Fig. 4 f-g. A 𝜏 𝑟 of ≈ 350 µs and a 𝜏 𝑓 of ≈ 20 µs are observed on the pseudo-CMOS inverter, while a 𝜏 𝑟 of ≈ 250 µs and a 𝜏 𝑓 of ≈ 20 µs are observed on the pseudo-NMOS inverter. The former 𝜏 𝑟 is slightly longer than that of the latter, which can be attributed to the higher resistance of the SBT load compared to the n-FET load. However, both of the 𝜏 𝑟 are much longer than the 𝜏 𝑓 since these values are not the intrinsic and still limited by the remaining external parasitic capacitance. RC delay depends on the value of the parasitic resistance and capacitance, where the capacitance is mainly determined by the device size 34 . After the optimization of the fabrication process, an improved switching speed (MHz or higher frequency level) can be achieved with transistors’ dimensional downscaling 18 , 35 . Especially, the resistance of the SBT may decrease to an appropriate level, meeting the state-of-the-art of both power and switching speed. With a record low static power, a high voltage gain, a high noise margin, and an optimizable operating speed, the pseudo-CMOS inverter becomes promising for use in multi-stage circuits. To this end, we have validated the feasibility of pseudo-CMOS technology in circuit-level manufacturing based on continuous MoS 2 thin films (Fig. 5 a and Supplementary Fig. 15). We fabricate essential logic gates (including NAND, NOR, AND, OR, and XOR) composed of SBTs and n-FETs with a careful design of the W/L ratios to ensure that the output voltage can normally drive state-switching of the next stage logic gate (Supplementary Fig. 16). The static power consumption of the pseudo-CMOS logic gates is evaluated in Fig. 5 b. Little tens of picoampere-level channel current is observed in steady-state, demonstrating enormous potential for use in low-power circuit manufacturing. The dynamic output voltage response is investigated using a 2 V full-scale square pulse input signal. At input A of 5 Hz and input B of 10 Hz, the pseudo-CMOS logic gates can achieve the desired Boolean operations with a full-swing output voltage and voltage-level matching (Fig. 5 c-g). Moreover, it is worth noting that only one SBT and one n-FET are required when XOR and AND gates apply the pass-transistor logic (PTL) architecture (Supplementary Fig. 17). The main benefit of this PTL configuration 37 , 38 is that the physical area of the logic gates can be greatly reduced by 80% for XOR and 60% for AND gates compared to the conventional configuration 25 , 39 . Conclusions We have reported a pseudo-CMOS logic architecture based on self-biased transistors. The SBT has a gapped MoS 2 channel that forms a bias-tunable homojunction with an ultralow reverse saturation current below 1 pA, which can fully cut off the current path and circumvents the need for polarity control of 2D material-based transistors. We created a pseudo-CMOS inverter using a SBT as a load and a MoS 2 n-FET as a driver with static power of a few picowatts, rail-to-rail operation at a switching threshold voltage of 0.5 V and noise margin > 90%. The dynamic operating speed (RC delay) is around 200 µs, and could be further optimized to megahertz or higher frequencies through transistor dimension downscaling. Finally, we showed that the pseudo-CMOS architecture can implement Boolean logic functions, including XOR, AND, NAND, NOR, and OR gates, which allows us to cascade any complex integrated circuit. Our pseudo-CMOS architecture with built-in SBTs is a promising approach for the development of future integrated circuits that balance power consumption and operating speed. Methods Growth of monolayer MoS 2 The single-crystal monolayer MoS 2 was grown in a single-temperature tubular furnace by oxygen-assisted chemical vapor deposition (CVD). Sulfur (S, Sigma-Aldrich, ≥ 99.5% purity) and molybdenum trioxide (MoO 3 , Sigma-Aldrich, ≥ 99.5% purity) powders were used as reactant materials and precursors, respectively. A ceramic boat containing S powder (1 g) was placed at the upstream position close to the air inlet, and the temperature was heated to 170 ℃ by the heating belt to produce sulfur vapor, which was carried through the Ar flow of 500 sccm during the growth. MoO 3 powder (15 mg) was placed in a quartz boat, and a 2×4 cm 2 Si substrate with 300 nm SiO 2 (from Silicon Valley Microelectronics, Inc.) was suspended on the quartz boat with the polished side facing the MoO 3 powder. Then the quartz boat was located at the center of the furnace. When the furnace temperature reaches the set value of 860 ℃, keep it for 30 minutes with an oxygen assist of ~ 1 sccm. Finally, natural cooling is carried out, and the growth of high-quality monolayer MoS 2 is completed. Device fabrication For the fabrication of self-biased homojunction, first, a patterned electrode cleaned by a reactive-ion etching (RIE) instrument was prepared on the Si substrate with 300 nm SiO 2 using e-beam lithography (EBL) complementary to optical lithography technology. And then the few-layer h-BN was precisely stacked on the prepared extended electrode by dry transfer technology using the polypropylene carbonate (PPC) film as a sacrificial layer. Where h-BN nanoflakes were mechanically exfoliated from bulk crystals by using 3M tape. Then, as-grown monolayer MoS 2 was accurately stacked on h-BN to form van der Waals heterojunction by 3% HF solution etch-assisted wet transfer technology with PMMA (polymethyl methacrylate) film as a sacrificial layer after the PPC on the upper surface of h-BN was removed by acetone and isopropanol solution. It should be noted that annealing at 200°C for 2 hours in a vacuum environment is required before depositing the electrode. Finally, using the EBL technique to pattern the electrodes exactly on the MoS 2 nanosheet and 10/50 nm Cr/Au was subsequently thermally evaporated onto substrates as metal contacts. As for the construction of complex logic gates, we need to use the EBL technique to map the desired local gate electrodes on the substrate in advance, followed by ALD deposition of a 20-nm-thickness HfO 2 dielectric layer. It is necessary to pattern MoS 2 film using the RIE etching technique to obtain the appropriate channel length/width ratio. Other construction processes are almost the same as above. Measurements The AFM and in-situ KPFM measurements were performed via the Bruker Dimension Icon system with a biased module (SAM-V, Bruker). A conductive probe (SCM-PIT-V2, Bruker Nano Inc., USA) with Pt/Ir coating was selected. The topography and thickness of the samples were measured under the peak force working mode, while the in-situ KPFM measurements were measured under the tapping mode with a resonant frequency of 75 kHz and a grounded tip biased sample height of 100 nm. Raman and in-situ PL spectrum measurements were performed with Confocal Raman microscopic systems (Horiba Jobin Yvon HR800) under a 532 nm laser and a program-controlled DC voltage and current stabilizing power. It should be noted that the devices required for the above measurement were bonded to the PCB (Printed Circuit Board) with a bonding system (Braunau Serie 53) in advance. The electrical measurements were implemented by semiconductor parameter analyzers (Keithley 4200-SCS, Keysight B1500A coupled with two pulse modules) combined with a Lakeshore probe station. In addition, dynamic behavior analysis is implemented using the two-channel function generator and digital oscilloscope. Declarations Competing interests The authors declare no competing interests. Author contributions X.W., Z.Z., and Y.Z. initiated and supervised the project. X.W., X.Z., Z.K, and Z.Z. designed the experiments. X.W. and X.Z. performed device fabrication, data collection and analysis. L.G. and Z.C. assisted in the preparation and characterization of monolayer MoS 2 by CVD. H.Y. and M.H. assisted in performing in situ characterization experiments. W.T., L.G, and H.Y. assisted in the device performance measurement, and data analysis. X.W., X.Z., Z.K., and Z.Z. co-wrote the manuscript. All authors discussed the results and commented on the manuscript. Acknowledgments This work was supported by the National Key Research and Development Program of China under grant nos. 2022YFA1203800 (Z.Z.), 2022YFA1203803 (Z.Z.), 2018YFA0703503 (Y.Z.), 2023YFF1500400 (Y.Z.), 2023YFF1500401 (X.Z.), the National Natural Science Foundation of China under grant nos. 51991340 (Y.Z.), 51991342 (Y.Z.), 52225206 (Z.Z.), 92163205 (Z.Z.), 52188101 (Y.Z.), 62322402 (X.Z.), 62204012 (X.Z.), 52250398 (X.Z.), 51972022 (Z.Z.), 52303362 (L.G.), 62304019 (H.Y.), the Frontier Cross Research Project of the Department of Chinese Academy of Sciences under grant nos. XK2023JSA001 (Y.Z.), the Beijing Nova Program under grant nos. 20220484145 (X.Z.), 20230484478 (X.Z.), the Fundamental Research Funds for the Central Universities under grant nos. FRF-06500207 (X.Z.), the State Key Lab for Advanced Metals and Materials (No. 2023-Z05 Z.Z.). We thank Professor Yuan Liu at the Hunan University and Professor Yanhao Yu at the Southern University of Science and Technology for constructive discussions. Data availability Source data are provided with this paper. All other data that support the findings of this study are available from the corresponding author on reasonable request. References Rupp, K. et al. 42 Years of Microprocessor Trend Data , (2018). International Roadmap for Devices and Systems (IRDS™) 2022 Edition—More Moore , (IEEE, 2022). Semiconductor, F. CMOS, the ideal logic family. nota de aplicación (1983). Henzler, S. Power management of digital circuits in deep sub-micron CMOS technologies . (Springer-Verlag, 2006). Rawat, A., Gupta, A. K. & Rawat, B. Performance projection of 2D material-based CMOS inverters for sub-10-nm channel length. IEEE Transactions on Electron Devices 68 , 3622-3629 (2021). Kim, N. S. et al. Leakage current: Moore's law meets static power. Computer 36 , 68-75 (2003). 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Supplementary Files InventoryofSupportingInformation.docx ReportingSummary.pdf Supplementaryinformation.pdf Cite Share Download PDF Status: Published Journal Publication published 08 Jan, 2024 Read the published version in Nature Electronics → Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-2502301","acceptedTermsAndConditions":true,"allowDirectSubmit":false,"archivedVersions":[],"articleType":"Article","associatedPublications":[],"authors":[{"id":256084878,"identity":"b79894dc-4b28-47a5-be68-ce3a3c3404b1","order_by":0,"name":"Yue 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Beijing","correspondingAuthor":false,"prefix":"","firstName":"Li","middleName":"","lastName":"Gao","suffix":""},{"id":256084883,"identity":"68d48945-b149-4e6b-acd0-77788d3f0930","order_by":5,"name":"Wenhui Tang","email":"","orcid":"","institution":"University of Science and Technology Beijing","correspondingAuthor":false,"prefix":"","firstName":"Wenhui","middleName":"","lastName":"Tang","suffix":""},{"id":256084884,"identity":"99e8cc8c-0e46-4d05-a0f9-5f0de2b10ade","order_by":6,"name":"Mengyu Hong","email":"","orcid":"","institution":"University of Science and Technology Beijing","correspondingAuthor":false,"prefix":"","firstName":"Mengyu","middleName":"","lastName":"Hong","suffix":""},{"id":256084885,"identity":"63993cab-8998-45fa-a0d8-9060888cb928","order_by":7,"name":"Zhangyi Chen","email":"","orcid":"","institution":"University of Science and Technology Beijing","correspondingAuthor":false,"prefix":"","firstName":"Zhangyi","middleName":"","lastName":"Chen","suffix":""},{"id":256084886,"identity":"6ac3b49f-bcee-41e2-a2b3-db01d44d1481","order_by":8,"name":"Zheng Zhang","email":"","orcid":"https://orcid.org/0000-0002-9104-7562","institution":"University of Science and Technology Beijing","correspondingAuthor":false,"prefix":"","firstName":"Zheng","middleName":"","lastName":"Zhang","suffix":""},{"id":256084887,"identity":"4730762d-e6fa-440f-bd0c-e9624611a337","order_by":9,"name":"Zhuo Kang","email":"","orcid":"https://orcid.org/0000-0003-3608-4069","institution":"University of Science and Technology Beijing","correspondingAuthor":false,"prefix":"","firstName":"Zhuo","middleName":"","lastName":"Kang","suffix":""}],"badges":[],"createdAt":"2023-01-21 12:25:33","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-2502301/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-2502301/v1","draftVersion":[],"editorialEvents":[{"content":"https://doi.org/10.1038/s41928-023-01112-w","type":"published","date":"2024-01-08T05:00:00+00:00"}],"editorialNote":"","failedWorkflow":false,"files":[{"id":57427037,"identity":"d26eee86-e326-4fbf-bf48-dc9d4c7f6b5f","added_by":"auto","created_at":"2024-05-30 14:30:08","extension":"png","order_by":1,"title":"Figure 1","display":"","copyAsset":false,"role":"figure","size":48325,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eComparison of the pseudo-CMOS inverter with the CMOS and the pseudo-NMOS configuration based on 2D materials. a-b\u003c/strong\u003e, Schematic of the CMOS inverter with a p-FET and a n-FET (\u003cstrong\u003ea\u003c/strong\u003e), the pseudo-NMOS inverter with a n-FET load and a n-FET driver (\u003cstrong\u003eb\u003c/strong\u003e). \u003cstrong\u003ec\u003c/strong\u003e, Schematic of the pseudo-CMOS inverter with a switchable SBT load and a n-FET driver, and energy band diagram near the gap position under two steady-states. \u003cstrong\u003ed\u003c/strong\u003e, Schematic curves of the static power as a function of input voltage under different inverter architectures. \u003cstrong\u003ee\u003c/strong\u003e, Static power levels of 2D materials-based inverters with different inverter architectures.\u003c/p\u003e","description":"","filename":"SeparateFig11.png","url":"https://assets-eu.researchsquare.com/files/rs-2502301/v1/1f2b3b27cd27c09ad827d2f1.png"},{"id":57428201,"identity":"99926f42-2334-452a-9dd8-2243da076377","added_by":"auto","created_at":"2024-05-30 14:38:09","extension":"png","order_by":2,"title":"Figure 2","display":"","copyAsset":false,"role":"figure","size":299856,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eStructure and characterization of the homojunction.\u003c/strong\u003e \u003cstrong\u003ea, \u003c/strong\u003eSchematic and \u003cem\u003ein-situ\u003c/em\u003e KPFM setup of the homojunction with an eye-catching gap near the double-acting drain electrode under the monolayer MoS\u003csub\u003e2\u003c/sub\u003e channel. Few-layers h-BN is used as the gate dielectric material. The enlarged image on the right shows the TEM analysis and corresponding EDS mapping.\u003cstrong\u003e b,\u003c/strong\u003e Optical image of the homojunction for in-situ KPFM characterization. The area in the black dashed square is used for KPFM mapping characterization. Scale bar: 10 μm. \u003cstrong\u003ec,\u003c/strong\u003e The KPFM mapping (upper) of the selected area from the dashed square in (\u003cstrong\u003eb\u003c/strong\u003e), at \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003ebias\u003c/em\u003e\u003c/sub\u003e= -1 V. Corresponding V\u003csub\u003eCPD\u003c/sub\u003e profiles (lower) were extracted from the solid white line in the mapping above. \u003cstrong\u003ed, \u003c/strong\u003ePL spectra of the MoS\u003csub\u003e2\u003c/sub\u003e from the black bar frame in Supplementary Fig. 6a under different bias voltages (\u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003ebias\u003c/em\u003e\u003c/sub\u003e= -1 V, 0 V, and 1 V). The red, dark green, and green lines are the three fitted peaks (A exciton, A\u003csup\u003eT\u003c/sup\u003e trion, and B exciton, respectively) by Lorentzian functions\u003csup\u003e27\u003c/sup\u003e. And the corresponding dashed lines as a guide to the eye for the peak position shift of A, A\u003csup\u003eT\u003c/sup\u003e, and B features. \u003cstrong\u003ee\u003c/strong\u003e, \u003cem\u003eI-V\u003c/em\u003e output curve and partial fitting curve (blue line) of the homojunction with three regions: (I) reverse current saturation region, (II) forward ideal linear diode region, and (III) forward series resistance-dominant region. An ideality factor of n = 1.1 is estimated under forward bias (0.02-0.25 V).\u003c/p\u003e","description":"","filename":"SeparateFig21.png","url":"https://assets-eu.researchsquare.com/files/rs-2502301/v1/4bb0b881a6c562b38cfa415e.png"},{"id":57427040,"identity":"4b83897a-9a61-4957-b355-59b05e60032a","added_by":"auto","created_at":"2024-05-30 14:30:09","extension":"png","order_by":3,"title":"Figure 3","display":"","copyAsset":false,"role":"figure","size":212330,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eStatic and dynamic characteristics of the pseudo-CMOS inverter. a\u003c/strong\u003e, Schematic of the pseudo-CMOS inverter with one SBT as a switchable load and one n-FET as a driver in series. The source and extended drain of the SBT are the power supply (\u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003edd\u003c/em\u003e\u003c/sub\u003e) and the output (\u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003eout\u003c/em\u003e\u003c/sub\u003e) terminals of the inverter, respectively. The gate and source of the n-FET are the input (\u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003ein\u003c/em\u003e\u003c/sub\u003e) and negative voltage (\u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003ess\u003c/em\u003e\u003c/sub\u003e) terminals of the inverter.\u003cstrong\u003e b\u003c/strong\u003e, Optical image of the pseudo-CMOS inverter with W/L ratios of 16/2 (SBT, load) and 5/10 (n-FET, driver) based on the monolayer MoS\u003csub\u003e2\u003c/sub\u003e channel and a 20-nm-thickness HfO\u003csub\u003e2\u003c/sub\u003e dielectric. Scale bar: 20 μm. \u003cstrong\u003ec\u003c/strong\u003e, Transfer characteristics of the transistors with different W/L ratios of 16/2 and 5/10, respectively. \u003cstrong\u003ed\u003c/strong\u003e, Output characteristics of the SBT load (red line) and the n-FET driver (blue lines) under a given input voltage from 0 to 1 V with a 0.1 V step at \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003edd\u003c/em\u003e\u003c/sub\u003e\u003csub\u003e \u003c/sub\u003e= 1 V and \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003ess \u003c/em\u003e\u003c/sub\u003e= 0 V.\u003cstrong\u003e e\u003c/strong\u003e,\u003cem\u003e \u003c/em\u003eOutput resistance of the SBT load (upper) and the n-FET driver (lower) in two operating states of the inverter.\u003cstrong\u003e f\u003c/strong\u003e, Voltage transfer curve (VTC) and its mirror reflection of the pseudo-CMOS inverter with a switching threshold voltage V\u003csub\u003eM\u003c/sub\u003e ≈ 0.5 V. The V\u003csub\u003eOH\u003c/sub\u003e, V\u003csub\u003eOL\u003c/sub\u003e, V\u003csub\u003eIL\u003c/sub\u003e, and V\u003csub\u003eIH\u003c/sub\u003e represent the minimum high output voltage, maximum low output voltage, maximum low input voltage, and minimum high input voltage for the inverter, respectively.\u003cstrong\u003e g\u003c/strong\u003e, Static power curve (left axis) and voltage gain curve (right axis) as a function of \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003ein\u003c/em\u003e\u003c/sub\u003e, a peak static power of ~10 pW and a peak voltage gain of ~86 are achieved.\u003cstrong\u003e h\u003c/strong\u003e, Dynamic output voltage response at a square wave input signal with a frequency of 1 kHz (upper), and the corresponding rise time and fall time of the output voltage (lower).\u003c/p\u003e","description":"","filename":"SeparateFig31.png","url":"https://assets-eu.researchsquare.com/files/rs-2502301/v1/864c2b4554dffb48366f6e00.png"},{"id":57427042,"identity":"ad27b101-5523-404d-8057-e79bcd71cfe2","added_by":"auto","created_at":"2024-05-30 14:30:09","extension":"png","order_by":4,"title":"Figure 4","display":"","copyAsset":false,"role":"figure","size":223712,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eComparison of the static and dynamic characteristics between the pseudo-CMOS and pseudo-NMOS inverters\u003c/strong\u003e.\u003cstrong\u003e a\u003c/strong\u003e, Schematic and circuit diagram of the pseudo-CMOS and pseudo-NMOS inverters based on the same monolayer MoS\u003csub\u003e2\u003c/sub\u003e. \u003cstrong\u003eb\u003c/strong\u003e, Corresponding optical micrograph image with a careful W/L ratio design. Scale bar: 30 μm. \u003cstrong\u003ec\u003c/strong\u003e-\u003cstrong\u003ed\u003c/strong\u003e, Typical VTCs of the pseudo-CMOS (\u003cstrong\u003ec\u003c/strong\u003e) and pseudo-NMOS (\u003cstrong\u003ed\u003c/strong\u003e) inverters as a function of \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003ein\u003c/em\u003e\u003c/sub\u003e under different \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003edd\u003c/em\u003e\u003c/sub\u003e. The inset is the corresponding peak voltage gain as a function of \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003edd\u003c/em\u003e\u003c/sub\u003e. A peak gain of ~241 (\u003cstrong\u003ec\u003c/strong\u003e) and ~148 (\u003cstrong\u003ed\u003c/strong\u003e) are achieved at \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003edd\u003c/em\u003e\u003c/sub\u003e = 4 V and \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003ess\u003c/em\u003e\u003c/sub\u003e = 0 V, respectively. \u003cstrong\u003ee\u003c/strong\u003e, Static peak power (P\u003csub\u003estatic, max\u003c/sub\u003e) of the pseudo-CMOS and pseudo-NMOS inverters as a function of \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003edd\u003c/em\u003e\u003c/sub\u003e, a P\u003csub\u003estatic, max\u003c/sub\u003e of ~7 pW and ~2.5 nW are calculated at \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003edd\u003c/em\u003e\u003c/sub\u003e = 0.5 V, \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003ess\u003c/em\u003e\u003c/sub\u003e = 0 V, respectively.\u003cstrong\u003e f\u003c/strong\u003e,\u003cem\u003e \u003c/em\u003eOutput resistance of the driver (upper) and load (lower) in two operating states of the inverter.\u003cstrong\u003e g\u003c/strong\u003e-\u003cstrong\u003eh\u003c/strong\u003e, Dynamic output voltage response of the pseudo-CMOS (\u003cstrong\u003eg\u003c/strong\u003e) and the pseudo-NMOS (\u003cstrong\u003eh\u003c/strong\u003e) inverters at a square wave input signal with a frequency of 1 kHz (upper), and the corresponding rise time and fall time of the output voltage (lower).\u003c/p\u003e","description":"","filename":"SeparateFig41.png","url":"https://assets-eu.researchsquare.com/files/rs-2502301/v1/91f69aee2becdf004aa0afca.png"},{"id":57427043,"identity":"88fd6600-4fb0-461c-9e43-89567ffe98d7","added_by":"auto","created_at":"2024-05-30 14:30:09","extension":"png","order_by":5,"title":"Figure 5","display":"","copyAsset":false,"role":"figure","size":309803,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003ePseudo-CMOS logic gates based on monolayer MoS\u003c/strong\u003e\u003csub\u003e\u003cstrong\u003e2\u003c/strong\u003e\u003c/sub\u003e\u003cstrong\u003e continuous film. a, \u003c/strong\u003eOptical images of\u003cstrong\u003e \u003c/strong\u003ethe pseudo-CMOS logic gates, including NAND (2T1SBT), AND (3T2SBT), NOR (2T1SBT), OR (3T2SBT), and XOR (7T4SBT). Scale bar: 50 μm.\u003cstrong\u003e b\u003c/strong\u003e, Steady-state current of the pseudo-CMOS logic gates in operation at \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003edd\u003c/em\u003e\u003c/sub\u003e = 2 V. \u003cstrong\u003ec\u003c/strong\u003e-\u003cstrong\u003eg,\u003c/strong\u003e Dynamic output voltage response of the NAND (\u003cstrong\u003ec\u003c/strong\u003e), NOR (\u003cstrong\u003ed\u003c/strong\u003e), AND (\u003cstrong\u003ee\u003c/strong\u003e), OR (\u003cstrong\u003ef\u003c/strong\u003e), and XOR (\u003cstrong\u003eg\u003c/strong\u003e) at an input A of 5 Hz and an input B of 10 Hz.\u003c/p\u003e","description":"","filename":"SeparateFig51.png","url":"https://assets-eu.researchsquare.com/files/rs-2502301/v1/3e8b6dcd779df175990463f2.png"},{"id":57429201,"identity":"c096198e-5dd9-4232-a943-6757966c14cb","added_by":"auto","created_at":"2024-05-30 14:46:10","extension":"pdf","order_by":0,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":1820805,"visible":true,"origin":"","legend":"","description":"","filename":"manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-2502301/v1/d25ee4f9-1530-4b2e-a4ea-2907faccf5a8.pdf"},{"id":57427038,"identity":"6940d79e-d538-447d-825d-4a85dac39140","added_by":"auto","created_at":"2024-05-30 14:30:09","extension":"docx","order_by":1,"title":"","display":"","copyAsset":false,"role":"supplement","size":52177,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cbr\u003e\u003c/p\u003e","description":"","filename":"InventoryofSupportingInformation.docx","url":"https://assets-eu.researchsquare.com/files/rs-2502301/v1/b9172b4af351bbfc103a6ba8.docx"},{"id":57428202,"identity":"07e5cded-828d-49ab-b4b7-91e729a968f3","added_by":"auto","created_at":"2024-05-30 14:38:09","extension":"pdf","order_by":2,"title":"","display":"","copyAsset":false,"role":"supplement","size":90081,"visible":true,"origin":"","legend":"","description":"","filename":"ReportingSummary.pdf","url":"https://assets-eu.researchsquare.com/files/rs-2502301/v1/ef3a35ef96ef8cfcb7154e78.pdf"},{"id":57427045,"identity":"b8467b17-962f-4e71-a619-1b1aa8175ad6","added_by":"auto","created_at":"2024-05-30 14:30:09","extension":"pdf","order_by":3,"title":"","display":"","copyAsset":false,"role":"supplement","size":16610290,"visible":true,"origin":"","legend":"","description":"","filename":"Supplementaryinformation.pdf","url":"https://assets-eu.researchsquare.com/files/rs-2502301/v1/17e9f283898fdfc8e44b5f1e.pdf"}],"financialInterests":"There is \u003cb\u003eNO\u003c/b\u003e Competing Interest.","formattedTitle":"Homojunction-loaded inverters based on self-biased molybdenum disulfide transistors for sub-picowatt computing","fulltext":[{"header":"Introduction","content":"\u003cp\u003eCritical to the development of integrated circuits (ICs) with high device density are transistors that use less power\u003csup\u003e\u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e,\u003cspan citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e\u003c/sup\u003e. As the dimensions of silicon-based transistors are reduced, the static power advantages of the complementary metal\u0026ndash;oxide\u0026ndash;semiconductor (CMOS) architecture are lost due to increased leakage currents\u003csup\u003e\u003cspan citationid=\"CR3\" class=\"CitationRef\"\u003e3\u003c/span\u003e,\u003cspan citationid=\"CR4\" class=\"CitationRef\"\u003e4\u003c/span\u003e\u003c/sup\u003e. Reducing static power consumption caused by leakage current is thus essential to limiting power rise (nearly 30 nanowatts per unit now currently exceeds 40% of the total power\u003csup\u003e\u003cspan citationid=\"CR5\" class=\"CitationRef\"\u003e5\u003c/span\u003e,\u003cspan citationid=\"CR6\" class=\"CitationRef\"\u003e6\u003c/span\u003e\u003c/sup\u003e. One approach to address this problem is to use two-dimensional (2D) materials, such as molybdenum disulfide (MoS\u003csub\u003e2\u003c/sub\u003e), because they have excellent field-effect properties\u003csup\u003e\u003cspan additionalcitationids=\"CR8 CR9 CR10\" citationid=\"CR7\" class=\"CitationRef\"\u003e7\u003c/span\u003e\u0026ndash;\u003cspan citationid=\"CR11\" class=\"CitationRef\"\u003e11\u003c/span\u003e\u003c/sup\u003e. However, the doping technology for silicon-based CMOS is too high-energy for atomically thin 2D materials\u003csup\u003e\u003cspan citationid=\"CR12\" class=\"CitationRef\"\u003e12\u003c/span\u003e\u003c/sup\u003e, meaning the potential of 2D materials-based ICs has not yet been fully realized\u003csup\u003e\u003cspan additionalcitationids=\"CR14 CR15\" citationid=\"CR13\" class=\"CitationRef\"\u003e13\u003c/span\u003e\u0026ndash;\u003cspan citationid=\"CR16\" class=\"CitationRef\"\u003e16\u003c/span\u003e\u003c/sup\u003e.\u003c/p\u003e\u003cp\u003eTwo main strategies have been developed to create 2D materials-based CMOS logic architecture composed of p-type field effect transistor (p-FET) and n-type field effect transistor (n-FET) pairs (Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003ea). The first is to control the polarity of transistors (by contact engineering\u003csup\u003e\u003cspan citationid=\"CR17\" class=\"CitationRef\"\u003e17\u003c/span\u003e\u003c/sup\u003e, electrostatic doping\u003csup\u003e\u003cspan citationid=\"CR18\" class=\"CitationRef\"\u003e18\u003c/span\u003e,\u003cspan citationid=\"CR19\" class=\"CitationRef\"\u003e19\u003c/span\u003e\u003c/sup\u003e, and mild doping methods\u003csup\u003e\u003cspan citationid=\"CR20\" class=\"CitationRef\"\u003e20\u003c/span\u003e,\u003cspan citationid=\"CR21\" class=\"CitationRef\"\u003e21\u003c/span\u003e\u003c/sup\u003e) to change the majority carrier types. But stable and precise technique towards practical circuit-level manufacture with low power and high performance still lacks due to the limited polarity control of ultra-thin 2D materials. The second strategy is to use two channel materials with different majority carrier types to realize CMOS logic functions\u003csup\u003e\u003cspan citationid=\"CR22\" class=\"CitationRef\"\u003e22\u003c/span\u003e,\u003cspan citationid=\"CR23\" class=\"CitationRef\"\u003e23\u003c/span\u003e\u003c/sup\u003e. However, the static current in the circuit is not completely suppressed due to the unbalanced carrier transport of transistor pairs. Therefore, most 2D large-scale logic circuits currently still follow earlier pseudo-n-type metal\u0026ndash;oxide\u0026ndash;semiconductor (pseudo-NMOS) architectures\u003csup\u003e\u003cspan additionalcitationids=\"CR25\" citationid=\"CR24\" class=\"CitationRef\"\u003e24\u003c/span\u003e\u0026ndash;\u003cspan citationid=\"CR26\" class=\"CitationRef\"\u003e26\u003c/span\u003e\u003c/sup\u003e composed of single-polarity transistors as the load and the driver (Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003eb), which have higher static power than CMOS.\u003c/p\u003e\u003cp\u003e\u003c/p\u003e\u003cp\u003eIn this work, we report a homojunction-loaded inverter composed of 2D self-biased transistor (SBT) as the load and 2D n-FET as the driver (Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003ec). Compared with pseudo-NMOS and CMOS, this architecture, which well called pseudo-CMOS, circumvents the polarity control of transistors and greatly reduces static power (Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003ed). The SBT is built by introducing a gap in the monolayer MoS\u003csub\u003e2\u003c/sub\u003e channel to form a homojunction, and its structure features is characterized by cross-section transmission electron microscopy (TEM), in-situ Kelvin probe force microscopy (KPFM), and photoluminescence spectroscopy (PL). Since the homogeneous SBT can timely cut off the current path of inverters when the n-FET is on, there is almost no static current flow in the circuit, achieving picowatt-level static power (Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003ee). The dynamic switching behavior is analyzed using a square wave input signal. We also implement other Boolean logic functions \u0026mdash; including XOR, AND, NAND, NOR, and OR gates \u0026mdash; with voltage-level matching based on this pseudo-CMOS configuration.\u003c/p\u003e"},{"header":"Structure and characterization of the homojunction","content":"\u003cp\u003eFigure \u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e2\u003c/span\u003ea presents an idealized device structure of the doping-free homojunction with a gapped channel near the double-acting electrode, which served as both source-drain and gate. Monolayer MoS\u003csub\u003e2\u003c/sub\u003e grown by CVD is chosen as the channel material to fabricate devices. The thickness of MoS\u003csub\u003e2\u003c/sub\u003e is ~\u0026thinsp;0.8 nm measured by atomic force microscopy (AFM), indicating the MoS\u003csub\u003e2\u003c/sub\u003e flake is a single layer (Supplementary Fig.\u0026nbsp;1c). The Raman spectra and PL spectrum of MoS\u003csub\u003e2\u003c/sub\u003e are shown in Supplementary Fig.\u0026nbsp;1d-e, and the conclusions are consistent with the results of the AFM. To confirm the unique device structure of this homojunction, a representative sample after fabrication is characterized by high-resolution TEM, showing the profile of the core region. An energy-dispersive spectrometer (EDS) is also used to confirm the material composition of the core region (Fig.\u0026nbsp;\u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e2\u003c/span\u003ea and Supplementary Fig.\u0026nbsp;2). In our demonstration, the Cr/Au (10/50 nm) as the source contact is made on the MoS\u003csub\u003e2\u003c/sub\u003e, and hexagonal boron nitride (h-BN) flakes are used as dielectric layers. The extended electrode serves as both the drain and gate contact to complete the device fabrication (Fig.\u0026nbsp;\u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e2\u003c/span\u003eb). Noteworthy, an eye-catching gap is left under the monolayer MoS\u003csub\u003e2\u003c/sub\u003e channel near the extended drain, creating a homojunction that can benefit from the self-biased effect. The signature structure feature of this homojunction is that the drain not only provides the biased voltage but also works as the gate to realize a barrier-tunable current path. The detailed fabrication process can be seen in the Methods and Supplementary Fig.\u0026nbsp;3.\u003c/p\u003e\u003cp\u003eTo demonstrate the self-biased effect of this homojunction, we perform \u003cem\u003ein-situ\u003c/em\u003e KPFM experiments to map the potential distribution of the dashed square (Fig.\u0026nbsp;\u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e2\u003c/span\u003eb). The measurement configuration enables us to spatially map the potential distribution of the core region under different bias conditions. Figure\u0026nbsp;\u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e2\u003c/span\u003ec and Supplementary Fig.\u0026nbsp;4 show the KPFM mapping (upper part) and the corresponding averaged contact potential difference (\u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003eCPD\u003c/em\u003e\u003c/sub\u003e) profile (lower part) of the selected area at the bias voltages V\u003csub\u003ebias\u003c/sub\u003e = -1 V, 0 V, and 1 V, respectively. A sharp potential mutation occurs at the gapped channel position after a bias voltage is applied, and the potential difference becomes more obvious as the bias voltage increases (Supplementary Fig.\u0026nbsp;5). It should be noted here that electrons, as the majority carriers in the channel, dominate the conductance of the device. Under positive bias voltage, a positive electrostatic field from the extended drain will implement electron doping to make the MoS\u003csub\u003e2\u003c/sub\u003e channel highly conductive, thus promoting the flow of electrons from the source to the drain. Under negative bias voltage, electrons are depleted in the channel due to a negative electrostatic doping from the drain, blocking the flow of electrons. As a result, the extended drain will simultaneously apply an electrostatic doping caused by this potential difference to tune the channel carrier concentration and form a bias-tunable homojunction at the gapped channel position.\u003c/p\u003e\u003cp\u003eSubsequently, we perform monolayer MoS\u003csub\u003e2\u003c/sub\u003e \u003cem\u003ein-situ\u003c/em\u003e PL spectrum characterization experiments under different bias conditions to further analyze the self-biased effect (Fig.\u0026nbsp;\u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e2\u003c/span\u003ed and Supplementary Fig.\u0026nbsp;6). Here, we need to know that the PL intensity of the A exciton is highly dependent on electrostatic doping, while the A\u003csup\u003eT\u003c/sup\u003e trion is independent on electrostatic doping due to a largely trion binding energy\u003csup\u003e\u003cspan citationid=\"CR28\" class=\"CitationRef\"\u003e28\u003c/span\u003e\u003c/sup\u003e, and the A exciton will convert into the A\u003csup\u003eT\u003c/sup\u003e trion as the electron doping increases. Compared with \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003ebias\u003c/em\u003e\u003c/sub\u003e=0 V, the peak intensity of A exciton is significantly lower than that of A\u003csup\u003eT\u003c/sup\u003e trion at \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003ebias\u003c/em\u003e\u003c/sub\u003e= 1 V, indicating that there is an electron doping to further promote the transition from A exciton to A\u003csup\u003eT\u003c/sup\u003e trion. The peak intensity of A exciton is higher than that of A\u003csup\u003eT\u003c/sup\u003e trion at \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003ebias\u003c/em\u003e\u003c/sub\u003e= -1 V, indicating that there is a hole doping to deplete the excess electrons and thus inhibit the transition from A exciton to A\u003csup\u003eT\u003c/sup\u003e trion. Since the PL intensity of monolayer MoS\u003csub\u003e2\u003c/sub\u003e is dominated by the prominent A exciton, a PL intensity diminishment and a peak energy red-shift are observed at \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003ebias\u003c/em\u003e\u003c/sub\u003e= 1 V, while a significant PL intensity enhancement and a peak energy blue-shift are observed at \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003ebias\u003c/em\u003e\u003c/sub\u003e= -1 V (Supplementary Fig.\u0026nbsp;6b).\u003c/p\u003e\u003cp\u003eThe result is that this homojunction exhibits an obvious asymmetrical electrical transport behavior when the applied bias voltage is changed from positive to negative, as shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e2\u003c/span\u003ee. The \u003cem\u003eI-V\u003c/em\u003e curve can be roughly divided into three regions: Ⅰ) reverse current saturation region; Ⅱ) forward ideal linear diode region; Ⅲ) forward series resistance-dominant region. An ideality factor (\u003cem\u003en\u003c/em\u003e) for evaluating the rectification performance of the homojunction can be calculated by fitting the Shockley diode Eq.\u0026nbsp;2\u003csup\u003e9,30\u003c/sup\u003e.\u003cdiv id=\"Equa\" class=\"Equation\"\u003e\u003cdiv format=\"TEX\" class=\"mathdisplay\" id=\"FileID_Equa\" name=\"EquationSource\"\u003e\n$${I}_{ds}={I}_{s}\\left[exp\\left(\\frac{{V}_{ds}}{n{V}_{T}}\\right)-1\\right]$$\u003c/div\u003e\u003c/div\u003e\u003c/p\u003e\u003cp\u003ewhere the \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003eT\u003c/em\u003e\u003c/sub\u003e and \u003cem\u003eI\u003c/em\u003e\u003csub\u003e\u003cem\u003es\u003c/em\u003e\u003c/sub\u003e are defined as the thermal voltage and reverse saturation current, respectively. A near-unity ideality factor of ~\u0026thinsp;1.1 (\u003cem\u003en\u003c/em\u003e\u0026thinsp;=\u0026thinsp;1 is ideal) can be obtained due to the rapid increase of current in region Ⅱ under forward bias (0.02\u0026ndash;0.25 V), indicating excellent rectification performance. Then, we explore the electrostatic self-biased effect of the homojunction under special bias mode and a higher bias voltage (Supplementary Fig.\u0026nbsp;7). The results show that the device is on when the extended drain has a positive potential relative to the source, which is defined as forward bias. Conversely, the device is off when the extended drain has a negative potential relative to the source, which is defined as reverse bias. The excellent rectification characteristics of the homojunction have almost no degradation after 30 days in the atmospheric environment. And an ultrahigh rectification ratio of ~\u0026thinsp;10\u003csup\u003e9\u003c/sup\u003e with an ultralow reverse saturation current below 1 pA is achieved with a bias range of \u0026plusmn;\u0026thinsp;10 V. As a comparison, this value is far higher than previous reports based on 2D materials that have been developed\u003csup\u003e\u003cspan additionalcitationids=\"CR30 CR31 CR32\" citationid=\"CR29\" class=\"CitationRef\"\u003e29\u003c/span\u003e\u0026ndash;\u003cspan citationid=\"CR33\" class=\"CitationRef\"\u003e33\u003c/span\u003e\u003c/sup\u003e. This unique asymmetrical electrical behavior of the homojunction is attributed to the partially gapped MoS\u003csub\u003e2\u003c/sub\u003e channel and the electrostatic self-biased effect caused by the double-use extended electrode.\u003c/p\u003e\u003cp\u003eFurthermore, we chose HfO\u003csub\u003e2\u003c/sub\u003e prepared by ALD instead of h-BN to demonstrate that the homojunction (SBT) is also suitable for other dielectric materials. The influence of HfO\u003csub\u003e2\u003c/sub\u003e thickness and channel length on the electrical transport properties of the SBT is systematically investigated, as shown in Supplementary Fig.\u0026nbsp;8. The size of the gap is mainly determined by the thickness of HfO\u003csub\u003e2\u003c/sub\u003e and the rectification characteristics of SBT have no degradation with the downscaling of the gap (\u003cem\u003eT\u003c/em\u003e\u003csub\u003e\u003cem\u003eHfO2\u003c/em\u003e\u003c/sub\u003e downscales to \u0026asymp;\u0026thinsp;15 nm). Even an improved rectification ratio is achieved, which may be attributed to the enhanced electrostatic doping as the thickness of HfO\u003csub\u003e2\u003c/sub\u003e decreases. Note that the off-current and on-current of SBT increase synchronously with the downscaling of the channel (\u003cem\u003eL\u003c/em\u003e\u003csub\u003e\u003cem\u003ech\u003c/em\u003e\u003c/sub\u003e downscales to \u0026lt;\u0026thinsp;300 nm). And an improved rectification characteristic is the fact that on-current increases more, which is attributed to lower gap effect on the channel resistance in the on-state. More importantly, the SBT exhibits very high stability, reliability, and endurance, which can be attributed to maintaining the integrity of the channel materials with an ingenious gap design, and the high stability of the grown MoS\u003csub\u003e2\u003c/sub\u003e itself. The SBT exhibits excellent rectification characteristics with negligible degradation at a square pulse bias signal for 10 Hz, even after 1,000 switching (on/off) cycles. Moreover, a retention time of about 10 years for steady operation is projected, and further details can be found in Supplementary Fig.\u0026nbsp;9. The robust rectification characteristics of HfO\u003csub\u003e2\u003c/sub\u003e-based SBT pave the way for fabricating low-power and high-performance logic circuits, as discussed in detail in the following section.\u003c/p\u003e"},{"header":"Pseudo-CMOS logic inverter","content":"\u003cp\u003eThe inverter that outputs the opposite logic level (logic \u0026lsquo;0\u0026rsquo; of low voltage and logic \u0026lsquo;1\u0026rsquo; of high voltage) corresponding to its input is the most fundamental logic element that performs a Boolean operation. Different from the conventional CMOS inverter, we design a doping-free homojunction-loaded pseudo-CMOS inverter without different-polarity transistor pairs for high-performance and low-power logic computing (Fig.\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003ea). First, the pseudo-CMOS inverter can be simply implemented on a monolayer MoS\u003csub\u003e2\u003c/sub\u003e channel by connecting one SBT as a switchable load and one n-FET as a driver in series. To achieve rail-to-rail output swing, the channel geometry is optimized by sizing the aspect ratio \u003cem\u003eW/L\u003c/em\u003e (Fig.\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003eb). Where \u003cem\u003eW\u003c/em\u003e and \u003cem\u003eL\u003c/em\u003e denote the width and length of the channels, is crucial, as it determines the switching threshold voltage V\u003csub\u003eM\u003c/sub\u003e of the inverter and thus the ability to cascade logic stages\u003csup\u003e\u003cspan citationid=\"CR24\" class=\"CitationRef\"\u003e24\u003c/span\u003e,\u003cspan citationid=\"CR26\" class=\"CitationRef\"\u003e26\u003c/span\u003e\u003c/sup\u003e. Figure\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003ec shows the transfer curves of n-FETs with W/L ratios of ~\u0026thinsp;16/2 and ~\u0026thinsp;5/10, exhibiting obvious n-type unipolar transport behavior with a I\u003csub\u003eon\u003c/sub\u003e/I\u003csub\u003eoff\u003c/sub\u003e ratio of \u0026gt;\u0026thinsp;10\u003csup\u003e8\u003c/sup\u003e and a desired subthreshold swing (SS) of ~\u0026thinsp;0.1 V/dec. And the former (W/L ratios of ~\u0026thinsp;16/2) current is \u0026gt;\u0026thinsp;10 times higher than the latter, demonstrating the feasibility of careful aspect ratio design. Thereby, we design the W/L ratios of SBT load and n-FET driver to be 16/2 and 5/10, respectively.\u003c/p\u003e\u003cp\u003eThe output characteristics of SBT and n-FET are depicted in Fig.\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003ed, showing clear current saturation due to channel pinch-off. When the input voltage V\u003csub\u003ein\u003c/sub\u003e is approximately 0.5 V, the current value of the n-FET closely matches that of the SBT, indicating their almost equal resistance at this time. In the pseudo-CMOS inverter, the output voltage (\u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003eout\u003c/em\u003e\u003c/sub\u003e) can be expressed as \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003eout\u003c/em\u003e\u003c/sub\u003e = \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003edd\u003c/em\u003e\u003c/sub\u003e \u0026times; \u003cem\u003eR\u003c/em\u003e\u003csub\u003e\u003cem\u003en\u0026minus;FET\u003c/em\u003e\u003c/sub\u003e / (\u003cem\u003eR\u003c/em\u003e\u003csub\u003e\u003cem\u003en\u0026minus;FET\u003c/em\u003e\u003c/sub\u003e + \u003cem\u003eR\u003c/em\u003e\u003csub\u003e\u003cem\u003eSBT\u003c/em\u003e\u003c/sub\u003e), where \u003cem\u003eR\u003c/em\u003e\u003csub\u003e\u003cem\u003en\u0026minus;FET\u003c/em\u003e\u003c/sub\u003e and \u003cem\u003eR\u003c/em\u003e\u003csub\u003e\u003cem\u003eSBT\u003c/em\u003e\u003c/sub\u003e are the resistances of the n-FET driver and SBT load, respectively. As shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003ee, the n-FET driver is in high resistance mode at the input voltage \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003ein\u003c/em\u003e\u003c/sub\u003e = 0 V, and it should be noted that the SBT load is in a relatively low resistance mode (\u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003eout\u003c/em\u003e\u003c/sub\u003e almost equal to the supply voltage \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003edd\u003c/em\u003e\u003c/sub\u003e). As \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003ein\u003c/em\u003e\u003c/sub\u003e transits to 1 V, the driver is in low resistance mode while the SBT rapidly enters the saturated regime with \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003edd\u003c/em\u003e\u003c/sub\u003e to \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003eout\u003c/em\u003e\u003c/sub\u003e voltage increases. The SBT starts in high resistance mode (\u003cem\u003eR\u003c/em\u003e\u003csub\u003e\u003cem\u003eSBT\u003c/em\u003e\u003c/sub\u003e\u0026thinsp;\u0026gt;\u0026thinsp;\u0026gt;\u0026thinsp;\u003cem\u003eR\u003c/em\u003e\u003csub\u003e\u003cem\u003en\u0026minus;FET\u003c/em\u003e\u003c/sub\u003e) due to the gapped channel and the V\u003csub\u003eout\u003c/sub\u003e is almost equal to ground (\u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003ess\u003c/em\u003e\u003c/sub\u003e), finishing the output switching.\u003c/p\u003e\u003cp\u003eFigure \u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003ef shows the voltage transfer curve (VTC) of the pseudo-CMOS inverter. When the input voltage switches from 0 V to 1 V, the inverter exhibits a good rail-to-rail operation with a switching threshold voltage \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003eM\u003c/em\u003e\u003c/sub\u003e \u0026asymp; 0.5 V at \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003edd\u003c/em\u003e\u003c/sub\u003e = 1 V, \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003ess\u003c/em\u003e\u003c/sub\u003e= 0 V. Furthermore, a high noise margin (NM\u003csub\u003eH\u003c/sub\u003e) of ~\u0026thinsp;0.48 V and a low noise margin (NM\u003csub\u003eL\u003c/sub\u003e) of ~\u0026thinsp;0.46 V are extracted, and the total NM is greater than 90% of |\u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003edd\u003c/em\u003e\u003c/sub\u003e-\u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003ess\u003c/em\u003e\u003c/sub\u003e|, suggesting the high noise tolerance of the pseudo-CMOS inverter. The static power (\u003cem\u003eP\u003c/em\u003e\u003csub\u003e\u003cem\u003estatic\u003c/em\u003e\u003c/sub\u003e) of an inverter can be expressed as \u003cem\u003eP\u003c/em\u003e\u003csub\u003e\u003cem\u003estatic\u003c/em\u003e\u003c/sub\u003e = \u003cem\u003eI\u003c/em\u003e\u003csub\u003e\u003cem\u003estatic\u003c/em\u003e\u003c/sub\u003e\u0026times;\u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003edd\u003c/em\u003e\u003c/sub\u003e, where \u003cem\u003eI\u003c/em\u003e\u003csub\u003e\u003cem\u003estatic\u003c/em\u003e\u003c/sub\u003e is the static current from \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003edd\u003c/em\u003e\u003c/sub\u003e to \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003ess\u003c/em\u003e\u003c/sub\u003e when the inverter operates in steady-state. Notably, a low peak static power of ~\u0026thinsp;10 pW with a high peak voltage gain of 86 is calculated at \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003eM\u003c/em\u003e\u003c/sub\u003e \u0026asymp; 0.5 V (Fig.\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003ef), which is important for low-power and high-performance logic computing. Moreover, a lower static power of sub-1 pW with a peak gain of 28 is achieved at \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003edd\u003c/em\u003e\u003c/sub\u003e = 0.6 V (Supplementary Fig.\u0026nbsp;10), which is a record-low value compared with previous reports on 2D materials-based inverters (Supplementary Table\u0026nbsp;1).\u003c/p\u003e\u003cp\u003eNote that low power may cause a loss in the operating speed of the pseudo-CMOS inverter. The dynamic switching behavior has been characterized using a square wave input signal with a voltage swing of 1 V at different AC frequencies and at \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003edd\u003c/em\u003e\u003c/sub\u003e = 1 V (Supplementary Fig.\u0026nbsp;11). As demonstrated by the dynamic analysis, the inverter can immediately invert the input signal, and the output signal can maintain a high-quality waveform response that is opposite to the input signal at a relatively low frequency (\u0026lt;\u0026thinsp;500 Hz). However, the output waveform gradually deforms as the frequency of the input signal increases, and full-swing output cannot be achieved at a higher frequency (\u0026gt;\u0026thinsp;5 kHz) mainly due to the RC delay in the circuit. RC delay can be obtained by analyzing the dynamic output switching curve of the inverter. The rising time delay (\u0026#120591;\u003csub\u003e\u0026#119903;\u003c/sub\u003e) and falling time (\u0026#120591;\u003csub\u003e\u0026#119891;\u003c/sub\u003e) here are defined as the time intervals between \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003e10%\u003c/em\u003e\u003c/sub\u003e and \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003e90%\u003c/em\u003e\u003c/sub\u003e\u003csup\u003e34,\u003cspan citationid=\"CR35\" class=\"CitationRef\"\u003e35\u003c/span\u003e\u003c/sup\u003e. A \u0026#120591;\u003csub\u003e\u0026#119903;\u003c/sub\u003e of \u0026asymp;\u0026thinsp;390 \u0026micro;s and a \u0026#120591;\u003csub\u003e\u0026#119891;\u003c/sub\u003e of \u0026asymp;\u0026thinsp;20 \u0026micro;s are observed at 1 kHz, as shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003eg. We note that the \u0026#120591;\u003csub\u003e\u0026#119903;\u003c/sub\u003e is around 20 times longer than \u0026#120591;\u003csub\u003e\u0026#119891;\u003c/sub\u003e, which can be attributed to the higher intrinsic resistance of SBTs compared to n-FETs in on-state (Fig.\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003ed). The average τ = (\u0026#120591;\u003csub\u003e\u0026#119903;\u003c/sub\u003e + \u0026#120591;\u003csub\u003e\u0026#119891;\u003c/sub\u003e)/2\u0026thinsp;\u0026asymp;\u0026thinsp;205 \u0026micro;s, is similar to the values noted in previous reports on 2D-based CMOS inverters\u003csup\u003e\u003cspan citationid=\"CR18\" class=\"CitationRef\"\u003e18\u003c/span\u003e,\u003cspan citationid=\"CR35\" class=\"CitationRef\"\u003e35\u003c/span\u003e,\u003cspan citationid=\"CR36\" class=\"CitationRef\"\u003e36\u003c/span\u003e\u003c/sup\u003e, which can be attributed to the large device area and high parasitic capacitance from the overlap of the gate and drain\u003csup\u003e\u003cspan citationid=\"CR21\" class=\"CitationRef\"\u003e21\u003c/span\u003e,\u003cspan citationid=\"CR22\" class=\"CitationRef\"\u003e22\u003c/span\u003e\u003c/sup\u003e.\u003c/p\u003e"},{"header":"Implementation of the pseudo-CMOS Boolean logic functions","content":"\u003cp\u003eCompared to conventional pseudo-NMOS configuration, the gap design of pseudo-CMOS can greatly suppress static current in the inverter when the driver is on, thus achieving low-power logic computing. In detail, we perform the pseudo-CMOS inverter versus the conventional pseudo-NMOS inverter experiment under the same measurement conditions. Figure\u0026nbsp;\u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003ea shows the schematic of the device used in the comparison experiment with the same monolayer MoS\u003csub\u003e2\u003c/sub\u003e and the same 20-nm-thick HfO\u003csub\u003e2\u003c/sub\u003e dielectric. To reduce the disturbance variable, two inverters share the same driver with W/L ratios of 5/10 and 16/2 for both load transistors (Fig.\u0026nbsp;\u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003eb). And the transfer characteristic curves of all transistors (SBT load, n-FET load, and n-FET driver) are depicted in Supplementary Fig.\u0026nbsp;12, where \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003egs\u003c/em\u003e\u003c/sub\u003e = \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003eds\u003c/em\u003e\u003c/sub\u003e for SBT load and n-FET load. The VTCs of the pseudo-CMOS inverter show highly sharp voltage switching at \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003eM\u003c/em\u003e\u003c/sub\u003e \u0026asymp; 0.5 V with a full-swing output and a peak gain of up to 241 at \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003edd\u003c/em\u003e\u003c/sub\u003e = 4 V (Fig.\u0026nbsp;\u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003ec), which can be attributed to the switching point being in the steepest subthreshold region of the n-FET driver. In contrast, the pseudo-NMOS inverter also exhibits a full swing output with a \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003eM\u003c/em\u003e\u003c/sub\u003e \u0026asymp; 0.85 V, while the voltage gain decreases from 241 to 148 at \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003edd\u003c/em\u003e\u003c/sub\u003e = 4 V (Fig.\u0026nbsp;\u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003ed), which may be attributed to the switching point crossing the steepest subthreshold region. Notably, a low static current of \u0026lt;\u0026thinsp;20 pA is achieved (Supplementary Fig.\u0026nbsp;13), and the calculated peak static power of the pseudo-CMOS inverter is remarkably reduced from ~\u0026thinsp;2.5 nW (for the pseudo-NMOS inverter) to ~\u0026thinsp;7 pW at \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003edd\u003c/em\u003e\u003c/sub\u003e = 0.5 V (Fig.\u0026nbsp;\u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003ee). The improved static power is a consequence of the SBT having a higher high-resistance mode (\u0026gt;\u0026thinsp;10\u003csup\u003e10\u003c/sup\u003e Ω, while\u0026thinsp;\u0026lt;\u0026thinsp;10\u003csup\u003e9\u003c/sup\u003e Ω for pseudo-NMOS load) when the shared n-FET driver is in low-resistance mode, as shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003ef.\u003c/p\u003e\u003cp\u003eIn principle, the gap design of SBT is to suppress static current in the circuit. When \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003eds\u003c/em\u003e\u003c/sub\u003e = (\u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003eout\u003c/em\u003e\u003c/sub\u003e-\u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003edd\u003c/em\u003e\u003c/sub\u003e)\u0026thinsp;\u0026lt;\u0026thinsp;0 V, the gap barrier caused by the potential difference increases the resistance. However, it should be noted that the SBT is not always in high resistance mode due to the near-zero gap barrier (\u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003eds\u003c/em\u003e\u003c/sub\u003e \u0026asymp; 0 V), which hardly affects the total resistance of the device (Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003ec and Supplementary Fig.\u0026nbsp;14, energy band diagrams under two steady-states). When n-FET is in high resistance mode, SBT is in relatively low resistance mode to ensure full swing output logic \u0026lsquo;1\u0026rsquo;. When n-FET is in low resistance mode, SBT is in high resistance mode to ensure full swing output logic \"0\" and reduce static current in the circuit. As a result, there is no current path from \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003edd\u003c/em\u003e\u003c/sub\u003e to \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003ess\u003c/em\u003e\u003c/sub\u003e in two steady states, achieving ultralow static power.\u003c/p\u003e\u003cp\u003eThe dynamic switching behavior of two inverters is also investigated using a square wave input signal with a voltage swing of 4 V at \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003edd\u003c/em\u003e\u003c/sub\u003e = 4 V for 1 kHz, as shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003ef-g. A \u0026#120591;\u003csub\u003e\u0026#119903;\u003c/sub\u003e of \u0026asymp;\u0026thinsp;350 \u0026micro;s and a \u0026#120591;\u003csub\u003e\u0026#119891;\u003c/sub\u003e of \u0026asymp;\u0026thinsp;20 \u0026micro;s are observed on the pseudo-CMOS inverter, while a \u0026#120591;\u003csub\u003e\u0026#119903;\u003c/sub\u003e of \u0026asymp;\u0026thinsp;250 \u0026micro;s and a \u0026#120591;\u003csub\u003e\u0026#119891;\u003c/sub\u003e of \u0026asymp;\u0026thinsp;20 \u0026micro;s are observed on the pseudo-NMOS inverter. The former \u0026#120591;\u003csub\u003e\u0026#119903;\u003c/sub\u003e is slightly longer than that of the latter, which can be attributed to the higher resistance of the SBT load compared to the n-FET load. However, both of the \u0026#120591;\u003csub\u003e\u0026#119903;\u003c/sub\u003e are much longer than the \u0026#120591;\u003csub\u003e\u0026#119891;\u003c/sub\u003e since these values are not the intrinsic and still limited by the remaining external parasitic capacitance. RC delay depends on the value of the parasitic resistance and capacitance, where the capacitance is mainly determined by the device size\u003csup\u003e\u003cspan citationid=\"CR34\" class=\"CitationRef\"\u003e34\u003c/span\u003e\u003c/sup\u003e. After the optimization of the fabrication process, an improved switching speed (MHz or higher frequency level) can be achieved with transistors\u0026rsquo; dimensional downscaling\u003csup\u003e\u003cspan citationid=\"CR18\" class=\"CitationRef\"\u003e18\u003c/span\u003e,\u003cspan citationid=\"CR35\" class=\"CitationRef\"\u003e35\u003c/span\u003e\u003c/sup\u003e. Especially, the resistance of the SBT may decrease to an appropriate level, meeting the state-of-the-art of both power and switching speed.\u003c/p\u003e\u003cp\u003eWith a record low static power, a high voltage gain, a high noise margin, and an optimizable operating speed, the pseudo-CMOS inverter becomes promising for use in multi-stage circuits. To this end, we have validated the feasibility of pseudo-CMOS technology in circuit-level manufacturing based on continuous MoS\u003csub\u003e2\u003c/sub\u003e thin films (Fig.\u0026nbsp;\u003cspan refid=\"Fig5\" class=\"InternalRef\"\u003e5\u003c/span\u003ea and Supplementary Fig.\u0026nbsp;15). We fabricate essential logic gates (including NAND, NOR, AND, OR, and XOR) composed of SBTs and n-FETs with a careful design of the W/L ratios to ensure that the output voltage can normally drive state-switching of the next stage logic gate (Supplementary Fig.\u0026nbsp;16). The static power consumption of the pseudo-CMOS logic gates is evaluated in Fig.\u0026nbsp;\u003cspan refid=\"Fig5\" class=\"InternalRef\"\u003e5\u003c/span\u003eb. Little tens of picoampere-level channel current is observed in steady-state, demonstrating enormous potential for use in low-power circuit manufacturing. The dynamic output voltage response is investigated using a 2 V full-scale square pulse input signal. At input A of 5 Hz and input B of 10 Hz, the pseudo-CMOS logic gates can achieve the desired Boolean operations with a full-swing output voltage and voltage-level matching (Fig.\u0026nbsp;\u003cspan refid=\"Fig5\" class=\"InternalRef\"\u003e5\u003c/span\u003ec-g). Moreover, it is worth noting that only one SBT and one n-FET are required when XOR and AND gates apply the pass-transistor logic (PTL) architecture (Supplementary Fig.\u0026nbsp;17). The main benefit of this PTL configuration\u003csup\u003e\u003cspan citationid=\"CR37\" class=\"CitationRef\"\u003e37\u003c/span\u003e,\u003cspan citationid=\"CR38\" class=\"CitationRef\"\u003e38\u003c/span\u003e\u003c/sup\u003e is that the physical area of the logic gates can be greatly reduced by 80% for XOR and 60% for AND gates compared to the conventional configuration\u003csup\u003e\u003cspan citationid=\"CR25\" class=\"CitationRef\"\u003e25\u003c/span\u003e,\u003cspan citationid=\"CR39\" class=\"CitationRef\"\u003e39\u003c/span\u003e\u003c/sup\u003e.\u003c/p\u003e"},{"header":"Conclusions","content":"\u003cp\u003eWe have reported a pseudo-CMOS logic architecture based on self-biased transistors. The SBT has a gapped MoS\u003csub\u003e2\u003c/sub\u003e channel that forms a bias-tunable homojunction with an ultralow reverse saturation current below 1 pA, which can fully cut off the current path and circumvents the need for polarity control of 2D material-based transistors. We created a pseudo-CMOS inverter using a SBT as a load and a MoS\u003csub\u003e2\u003c/sub\u003e n-FET as a driver with static power of a few picowatts, rail-to-rail operation at a switching threshold voltage of 0.5 V and noise margin\u0026thinsp;\u0026gt;\u0026thinsp;90%. The dynamic operating speed (RC delay) is around 200 \u0026micro;s, and could be further optimized to megahertz or higher frequencies through transistor dimension downscaling. Finally, we showed that the pseudo-CMOS architecture can implement Boolean logic functions, including XOR, AND, NAND, NOR, and OR gates, which allows us to cascade any complex integrated circuit. Our pseudo-CMOS architecture with built-in SBTs is a promising approach for the development of future integrated circuits that balance power consumption and operating speed.\u003c/p\u003e"},{"header":"Methods","content":"\u003cp\u003e \u003cstrong\u003eGrowth of monolayer MoS\u003csub\u003e2\u003c/sub\u003e\u003c/strong\u003e\u003c/p\u003e \u003cp\u003eThe single-crystal monolayer MoS\u003csub\u003e2\u003c/sub\u003e was grown in a single-temperature tubular furnace by oxygen-assisted chemical vapor deposition (CVD). Sulfur (S, Sigma-Aldrich, \u0026ge;\u0026thinsp;99.5% purity) and molybdenum trioxide (MoO\u003csub\u003e3\u003c/sub\u003e, Sigma-Aldrich, \u0026ge;\u0026thinsp;99.5% purity) powders were used as reactant materials and precursors, respectively. A ceramic boat containing S powder (1 g) was placed at the upstream position close to the air inlet, and the temperature was heated to 170 ℃ by the heating belt to produce sulfur vapor, which was carried through the Ar flow of 500 sccm during the growth. MoO\u003csub\u003e3\u003c/sub\u003e powder (15 mg) was placed in a quartz boat, and a 2\u0026times;4 cm\u003csup\u003e\u003cspan citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e\u003c/sup\u003e Si substrate with 300 nm SiO\u003csub\u003e2\u003c/sub\u003e (from Silicon Valley Microelectronics, Inc.) was suspended on the quartz boat with the polished side facing the MoO\u003csub\u003e3\u003c/sub\u003e powder. Then the quartz boat was located at the center of the furnace. When the furnace temperature reaches the set value of 860 ℃, keep it for 30 minutes with an oxygen assist of ~\u0026thinsp;1 sccm. Finally, natural cooling is carried out, and the growth of high-quality monolayer MoS\u003csub\u003e2\u003c/sub\u003e is completed.\u003c/p\u003e \u003cp\u003e \u003cstrong\u003eDevice fabrication\u003c/strong\u003e\u003c/p\u003e \u003cp\u003eFor the fabrication of self-biased homojunction, first, a patterned electrode cleaned by a reactive-ion etching (RIE) instrument was prepared on the Si substrate with 300 nm SiO\u003csub\u003e2\u003c/sub\u003e using e-beam lithography (EBL) complementary to optical lithography technology. And then the few-layer h-BN was precisely stacked on the prepared extended electrode by dry transfer technology using the polypropylene carbonate (PPC) film as a sacrificial layer. Where h-BN nanoflakes were mechanically exfoliated from bulk crystals by using 3M tape. Then, as-grown monolayer MoS\u003csub\u003e2\u003c/sub\u003e was accurately stacked on h-BN to form van der Waals heterojunction by 3% HF solution etch-assisted wet transfer technology with PMMA (polymethyl methacrylate) film as a sacrificial layer after the PPC on the upper surface of h-BN was removed by acetone and isopropanol solution. It should be noted that annealing at 200\u0026deg;C for 2 hours in a vacuum environment is required before depositing the electrode. Finally, using the EBL technique to pattern the electrodes exactly on the MoS\u003csub\u003e2\u003c/sub\u003e nanosheet and 10/50 nm Cr/Au was subsequently thermally evaporated onto substrates as metal contacts. As for the construction of complex logic gates, we need to use the EBL technique to map the desired local gate electrodes on the substrate in advance, followed by ALD deposition of a 20-nm-thickness HfO\u003csub\u003e2\u003c/sub\u003e dielectric layer. It is necessary to pattern MoS\u003csub\u003e2\u003c/sub\u003e film using the RIE etching technique to obtain the appropriate channel length/width ratio. Other construction processes are almost the same as above.\u003c/p\u003e \u003cp\u003e \u003cstrong\u003eMeasurements\u003c/strong\u003e \u003cp\u003eThe AFM and \u003cem\u003ein-situ\u003c/em\u003e KPFM measurements were performed via the Bruker Dimension Icon system with a biased module (SAM-V, Bruker). A conductive probe (SCM-PIT-V2, Bruker Nano Inc., USA) with Pt/Ir coating was selected. The topography and thickness of the samples were measured under the peak force working mode, while the \u003cem\u003ein-situ\u003c/em\u003e KPFM measurements were measured under the tapping mode with a resonant frequency of 75 kHz and a grounded tip biased sample height of 100 nm. Raman and \u003cem\u003ein-situ\u003c/em\u003e PL spectrum measurements were performed with Confocal Raman microscopic systems (Horiba Jobin Yvon HR800) under a 532 nm laser and a program-controlled DC voltage and current stabilizing power. It should be noted that the devices required for the above measurement were bonded to the PCB (Printed Circuit Board) with a bonding system (Braunau Serie 53) in advance. The electrical measurements were implemented by semiconductor parameter analyzers (Keithley 4200-SCS, Keysight B1500A coupled with two pulse modules) combined with a Lakeshore probe station. In addition, dynamic behavior analysis is implemented using the two-channel function generator and digital oscilloscope.\u003c/p\u003e \u003c/p\u003e"},{"header":"Declarations","content":"\u003ch2\u003eCompeting interests\u003c/h2\u003e \u003cp\u003eThe authors declare no competing interests.\u003c/p\u003e \u003ch2\u003eAuthor contributions\u003c/h2\u003e \u003cp\u003eX.W., Z.Z., and Y.Z. initiated and supervised the project. X.W., X.Z., Z.K, and Z.Z. designed the experiments. X.W. and X.Z. performed device fabrication, data collection and analysis. L.G. and Z.C. assisted in the preparation and characterization of monolayer MoS\u003csub\u003e2\u003c/sub\u003e by CVD. H.Y. and M.H. assisted in performing in situ characterization experiments. W.T., L.G, and H.Y. assisted in the device performance measurement, and data analysis. X.W., X.Z., Z.K., and Z.Z. co-wrote the manuscript. All authors discussed the results and commented on the manuscript.\u003c/p\u003e\u003ch2\u003eAcknowledgments\u003c/h2\u003e \u003cp\u003eThis work was supported by the National Key Research and Development Program of China under grant nos. 2022YFA1203800 (Z.Z.), 2022YFA1203803 (Z.Z.), 2018YFA0703503 (Y.Z.), 2023YFF1500400 (Y.Z.), 2023YFF1500401 (X.Z.), the National Natural Science Foundation of China under grant nos. 51991340 (Y.Z.), 51991342 (Y.Z.), 52225206 (Z.Z.), 92163205 (Z.Z.), 52188101 (Y.Z.), 62322402 (X.Z.), 62204012 (X.Z.), 52250398 (X.Z.), 51972022 (Z.Z.), 52303362 (L.G.), 62304019 (H.Y.), the Frontier Cross Research Project of the Department of Chinese Academy of Sciences under grant nos. XK2023JSA001 (Y.Z.), the Beijing Nova Program under grant nos. 20220484145 (X.Z.), 20230484478 (X.Z.), the Fundamental Research Funds for the Central Universities under grant nos. FRF-06500207 (X.Z.), the State Key Lab for Advanced Metals and Materials (No. 2023-Z05 Z.Z.). We thank Professor Yuan Liu at the Hunan University and Professor Yanhao Yu at the Southern University of Science and Technology for constructive discussions.\u003c/p\u003e\u003ch2\u003eData availability\u003c/h2\u003e \u003cp\u003eSource data are provided with this paper. All other data that support the findings of this study are available from the corresponding author on reasonable request.\u003c/p\u003e"},{"header":"References","content":"\u003col\u003e\n\u003cli\u003eRupp, K.\u003cem\u003e et al.\u003c/em\u003e \u003cem\u003e42 Years of Microprocessor Trend Data\u003c/em\u003e, \u0026lt;https://www.karlrupp.net/2018/02/42-years-of-microprocessor-trend-data/\u0026gt; (2018).\u003c/li\u003e\n\u003cli\u003e\u003cem\u003eInternational Roadmap for Devices and Systems (IRDS\u0026trade;) 2022 Edition\u0026mdash;More Moore\u003c/em\u003e, \u0026lt;https://irds.ieee.org/images/files/pdf/2022/2022IRDS_MM.pdf\u0026gt; (IEEE, 2022).\u003c/li\u003e\n\u003cli\u003eSemiconductor, F. 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Combining two-dimensional (2D) channel materials with complementary metal–oxide–semiconductor (CMOS) logic architectures could be an effective solution to this issue due to the excellent field-effect properties of 2D materials. However, 2D materials have limited polarity control. Here, we report a pseudo-CMOS architecture for sub-picowatt logic computing that uses self-biased molybdenum disulfide transistors. The transistors have a gapped channel that forms a tunable barrier — thus circumventing the polarity control of 2D materials — and exhibit a reverse saturation current below 1 pA with high reliability and endurance. We use the devices to make homojunction-loaded inverters with good rail-to-rail operation at a switching threshold voltage of around 0.5 V, a static power of a few picowatts, a dynamic delay time of around 200 µs, a noise margin over 90%, and a peak voltage gain of 241. Additionally, fundamental gate circuits based on this pseudo-CMOS configuration are fabricated by integrating more devices.","manuscriptTitle":"Homojunction-loaded inverters based on self-biased molybdenum disulfide transistors for sub-picowatt computing","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2024-05-30 14:30:04","doi":"10.21203/rs.3.rs-2502301/v1","editorialEvents":[],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"nature-electronics","isNatureJournal":true,"hasQc":false,"allowDirectSubmit":false,"externalIdentity":"natelectron","sideBox":"Learn more about [Nature Electronics](http://www.nature.com/natelectron/)","snPcode":"","submissionUrl":"","title":"Nature Electronics","twitterHandle":"","acdcEnabled":true,"dfaEnabled":true,"editorialSystem":"ejp","reportingPortfolio":"Nature Research","inReviewEnabled":true,"inReviewRevisionsEnabled":false}}],"origin":"","ownerIdentity":"1daf1698-bc28-4b53-b866-6f54ef91c26f","owner":[],"postedDate":"May 30th, 2024","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"published-in-journal","subjectAreas":[{"id":27046829,"name":"Physical sciences/Materials science/Materials for devices/Electronic devices"},{"id":27046830,"name":"Physical sciences/Materials science/Nanoscale materials/Two-dimensional materials"},{"id":27046831,"name":"Physical sciences/Engineering/Electrical and electronic engineering"}],"tags":[],"updatedAt":"2024-05-30T14:30:04+00:00","versionOfRecord":{"articleIdentity":"rs-2502301","link":"https://doi.org/10.1038/s41928-023-01112-w","journal":{"identity":"nature-electronics","isVorOnly":false,"title":"Nature Electronics"},"publishedOn":"2024-01-08 05:00:00","publishedOnDateReadable":"January 8th, 2024"},"versionCreatedAt":"2024-05-30 14:30:04","video":"","vorDoi":"10.1038/s41928-023-01112-w","vorDoiUrl":"https://doi.org/10.1038/s41928-023-01112-w","workflowStages":[]},"version":"v1","identity":"rs-2502301","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-2502301","identity":"rs-2502301","version":["v1"]},"buildId":"qtupq5eGEP_6zYnWcrvyt","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}