The FinFET to Nanosheet Transition: A Critical Enabler for Energy-Efficient AIoT Applications

The FinFET to Nanosheet Transition: A Critical Enabler for Energy-Efficient AIoT Applications | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article The FinFET to Nanosheet Transition: A Critical Enabler for Energy-Efficient AIoT Applications Ritu Raj Lamsal, Mamta Bhattarai This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-7705956/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract The relentless scaling of complementary metal-oxide-semiconductor (CMOS) technology, as dictated by Moore's Law, has driven the semiconductor industry through multiple transistor architecture revolutions. The planar bulk MOSFET, after decades of dominance, was succeeded by the three-dimensional FinFET at the 22/16 nm node to overcome severe short-channel effects (SCEs). However, as scaling continues to the 5 nm node and beyond, the limitations of the FinFET have become apparent. This literature review examines the journey from FinFETs to the next-generation architecture: the Gate-All-Around (GAA) Nanosheet Field-Effect Transistor (NSFET). It covers the motivations for this transition, the advantages and challenges of nanosheet technology, and the future roadmap towards forksheet and complementary FET (CFET) architectures. This paper presents a comparative analysis of power and delay characteristics between 5nm FinFET and 3nm Gate All Around (GAA) Nanosheet technologies using the educational EDA tool. A standard CMOS inverter is used as a test vehicle for this analysis. Simulation results demonstrate a significant improvement in the power-delay product (PDP) for the 3nm Nanosheet technology, improvement in propagation delay compared to the 5nm FinFET, primarily due to superior electrostatic control enabling lower supply voltage operation. The findings underscore the critical importance of the transition to GAA architectures for next-generation applications in Artificial Intelligence (AI), Machine Learning (ML), and the Internet of Things (IoT), where computational efficiency and ultra-low power consumption are paramount. Electronic Materials and Devices CMOS FinFET Nanosheet FET Gate All Around Low-Power Design AIoT Hardware Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 1. Introduction 1.1 The Era of the FinFET The insatiable demand for higher processing power and superior energy efficiency in modern electronics, driven by transformative technologies like Artificial Intelligence (AI) and the Internet of Things (IoT), relentlessly pushes the boundaries of semiconductor technology [ 1 ]. This demand creates a dual challenge: IoT edge devices require ultra-low-power processors to operate autonomously for years on miniature batteries, while AI training and inference demand immense computational throughput within strict thermal budgets, making power density a first-order design constraint [ 2 ]. Meeting these demands hinges on the continued scaling of transistor technology. For decades, this scaling was successfully achieved through the planar Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). However, as gate lengths approached the sub-30 nm regime, the industry encountered fundamental physical barriers. The inability to maintain electrostatic control over the channel led to severe short-channel effects (SCEs), characterized by exponential increases in leakage current and threshold voltage roll-off, rendering further planar scaling impractical [ 3 ]. This crisis precipitated a fundamental architectural shift. The seminal work by Hisamoto et al. introduced the concept of a three-dimensional transistor, the precursor to the modern FinFET, which demonstrated significantly improved SCE immunity [ 4 ]. The FinFET architecture addressed the limitations of the planar device by raising a narrow silicon "fin" from the substrate, allowing the gate to wrap around three sides of the channel. This provided vastly superior electrostatic control compared to its planar predecessor [ 5 ]. The industry's adoption of FinFETs, led by Intel at the 22 nm node, marked a critical inflection point, enabling continued performance and density scaling for nearly a decade [ 6 ]. FinFETs offered compelling advantages, including higher on-state current (I ON ) for a given footprint, lower leakage current (I OFF ), and a reduced subthreshold swing (SS). Nevertheless, as scaling approaches the 5 nm node and beyond, the limitations of the FinFET architecture have become pronounced. Challenges in further fin width scaling, increased variability, and ultimately insufficient gate control—stemming from the gate only contacting three sides of the channel—lead to rising leakage currents, once again threatening the path of Moore's Law [ 7 ]. In response, the Gate-All-Around (GAA) transistor, specifically the Nanosheet FET (NSFET), has emerged as the designated successor to the FinFET. This architecture represents the logical culmination of 3D design, where the gate material completely surrounds a stack of horizontal silicon channels (nanosheets) [ 8 ]. This configuration provides the ultimate electrostatic control, effectively suppressing SCEs at the 2 nm node and below. A key benefit of this enhanced control is the ability to further reduce the operating voltage (V DD ), which quadratically reduces dynamic power consumption and directly lowers leakage current [ 9 ]. These characteristics make GAA Nanosheet technology uniquely suited to address the critical need for high-performance, ultra-low-power hardware required for the next generation of AI and IoT applications [ 1 , 2 ]. 1.2 Limitations of the FinFET at Scaled Nodes Despite its success, the FinFET faces fundamental physical limitations as the contacted poly pitch (CPP) and fin pitch are scaled down below 5 nm. Key challenges identified in the literature include: Electrostatic Control: In a FinFET, the gate only wraps around three sides of the channel, leaving a bottom interface that is vulnerable to leakage paths. At ultra-scaled fin widths, variability in fin patterning and line-edge roughness becomes a significant issue for performance and yield [ 10 ]. Drive Current Limitations: The drive current of a FinFET is proportional to the fin height. To increase current, designers must either increase fin height (leading to difficult high-aspect-ratio etching and filling processes) or place multiple fins in parallel (consuming more area and increasing parasitic capacitance) [ 11 ]. V T Tuning and Work Function Metal Deposition: Conformal deposition of work function metals (WFM) on the three-dimensional fin structure becomes increasingly challenging with pitch scaling. Inadequate WFM deposition leads to poor threshold voltage (V T ) control and variability [ 12 ]. These limitations necessitated a new architecture with even more robust electrostatic integrity: the Gate-All-Around (GAA) transistor. 1.3. The Gate-All-Around Nanosheet FET: A Superior Successor The Nanosheet FET represents the logical evolution beyond the FinFET. Instead of a vertical fin, the NSFET features multiple horizontal sheets of silicon stacked on top of one another, with the gate material wrapping around each sheet completely. This true GAA structure provides the ultimate electrostatic control, effectively suppressing SCEs at the sub-5 nm node [ 13 ]. Key Advantages of NSFETs: Enhanced Electrostatic Control: The GAA configuration provides superior control over the channel, resulting in a near-ideal subthreshold swing and significantly reduced drain-induced barrier lowering (DIBL) compared to FinFET at the same gate length [ 14 ]. Higher Drive Current per Footprint: The drive current is proportional to the total width of the nanosheet. By stacking multiple sheets vertically, a much larger effective width can be achieved within the same footprint as a single fin, leading to higher performance without area penalty [ 15 ]. Better V T Tunability: The structure allows for independent tuning of nanosheet thickness and width, providing an additional knob for designers to optimize performance and power [ 16 ]. Furthermore, WFM deposition on horizontal surfaces is generally considered more manageable than on complex fin sidewalls. 1.4 State of the Art Global Foundries for Nanosheet Fabrication Samsung Foundry currently stands as the primary manufacturer of chips utilizing nanosheet transistors, having achieved a significant industry milestone by initiating volume production of its 3nm node with Multi-Bridge-Channel FET (MBCFET™) technology in 2022. This accomplishment positioned Samsung as the pioneer in commercializing the Gate-All-Around (GAA) architecture [ 17 ]. The competitive landscape, however, is dynamic. Taiwan Semiconductor Manufacturing Company (TSMC), the global foundry leader, is preparing to introduce its own nanosheet technology with a planned volume production of its 2nm (N2) node in 2025 [ 18 , 19 ]. Meanwhile, Intel Foundry's path has involved a strategic pivot. While the company developed its Intel 20A node—featuring its RibbonFET GAA technology—as a crucial testbed for foundational innovations, it announced a significant shift in September 2024 [ 20 ]. Intel canceled the 20A node for commercial production, opting instead to leverage external foundry partners like TSMC for products such as its Arrow Lake CPUs. This decision, aimed at cost-saving and resource optimization, allows Intel to redirect efforts toward accelerating the volume production of its more advanced 18A (1.8nm-class) node. Consequently, while Samsung presently leads in production volume, the industry is converging on GAA technology. By 2025, both Samsung and TSMC are projected to have nanosheet-based processes in high-volume manufacturing. Intel aims to join them with its refined 18A node, collectively establishing GAA transistors as the new industry standard for the most advanced semiconductor nodes. Table 1 Summary of State of the Art Foundries Foundry / Company Technology Node Name for Nanosheet Tech Status (as of 2024) Samsung Foundry 3nm (SF3), 2nm (SF2) MBCFET™ In Production (since 2022 for 3nm) TSMC 2nm (N2) Nanosheet (GAA) Volume Production planned for 2025 Intel Foundry 20A (2nm-class) RibbonFET Planned for 2024 ( Cancelled later) 2. Materials and Methods The analysis was conducted using Microwind version 3.9, an integrated circuit design and simulation tool for educational purposes. It features a built-in MOS scaling utility and a basic model for GAA transistors, allowing for a first-order comparison of different technology nodes [ 21 ]. Figure 1 illustrates the parameters associated with FinFET and nanosheet FET. It is important to note that the results are based on predictive and simplified models and are intended for trend analysis rather than absolute accuracy. 2.2 Test Vehicle A standard CMOS inverter was chosen as the fundamental test vehicle for this analysis. The layout and three dimensional model is shown in Fig. 2 and Fig. 3 for FinFET and GAA Nanosheet respectively. Its simplicity allows for clear isolation and measurement of intrinsic device properties like delay and switching power. 2.3 Simulation Setup Two separate designs were created for 5nm FinFET Inverter and 2nm Nanosheet FET inverter as shown in Figs. 2 and 3 . A supply voltage (V DD ) of 0.65V was applied, consistent with industry projections for this node [22, 23]. For a fair comparison, both inverters were designed to drive an identical load capacitor (C L = 5fF). The input was driven by a pulse voltage source with a rise/fall time of 0.05ns and a period of 0.1ns. 2.4 Analysis Methodology Transient Analysis : Used to measure the propagation delay t p from the 50% point of the input signal to the 50% point of the output signal. Power Analysis : Power Consumption feature was used to obtain the average dynamic power consumption during switching. DC Analysis : Used to plot the Voltage Transfer Characteristic (VTC) and estimate the static (leakage) power by measuring the current at stable input states (V in = 0V and V IN =V DD ). 3. Results and Discussion Various analysis plots for 5nm FinFET are shown in Fig. 5 . The DC analysis Fig. 5 (a) reveals the switching Characteristics of the inverter. The voltage verses time plot is shown in Fig. 5 (b) similarly voltage vs current and frequency verses time plots are depicted in Fig. 5 (c) and (d) respectively. The simulation is run for 2 nano second in interval of 100ps. The power consumption is 19.134 microwatts at 27 degree celcius. The average delay is estimated around 10 ps. The noise margin is estimated as High-level noise margin (NMH) NMH = VOH–VIH ≈ 0.65 V – 0.33 V = 0.32 V Low-level noise margin (NML) : NML = VIL–VOL ≈ 0.28 V – 0.0 V = 0.28 V Similarly Fig. 6 depicts various characteristics of GAA nanosheet. Nanosheet shows lower power consumption 18.03 µW vs 19.219 µW. This demonstrates the better electrostatic control of GAA architecture and Lower leakage currents contribute to reduced static power. The VTC of the 2nm NSFET inverter is steeper and more ideal than that of the 5nm FinFET, indicating a higher gain and better noise margins. This is a direct result of the enhanced electrostatic integrity of the GAA structure, which leads to a sharper transition from the off-state to the on-state. The simulation results show a faster switching response for the 2nm Nanosheet inverter. Transient analysis was performed to compare the switching speed. The key insights drawn from the overall analysis is summarized below: I. Speed Improvement (Delay) : The transition from a three-sided gate (FinFET) to a four-sided, full-wrap gate (GAA Nanosheet) provides ultimate electrostatic control. This suppresses drain-induced barrier lowering (DIBL) and allows for more aggressive channel scaling, resulting in a higher on-state current (I ON ) and thus faster circuit switching II. Power Improvement (Power) : The foundational benefit of the GAA structure is its ability to maintain performance at a significantly lower threshold voltage (V th ) and supply voltage (V DD ) without succumbing to leakage. Since dynamic power has a quadratic dependence on V DD , even a modest reduction in voltage yields substantial power savings. The 2nm node leverages this to operate at 0.55V, drastically cutting active power. III. Efficiency Improvement (PDP) : The PDP metric combines speed and power. The Nanosheet's architecture delivers a "win-win" scenario: it is both faster and consumes less power per operation. This synergistic improvement makes the 2nm GAA technology vastly more energy-efficient than the 5nm FinFET node, which is essential for extending battery life in mobile devices and reducing the enormous energy footprint of data centers. 3.4 Implications for Emerging Technologies (AI, ML, IoT) The results have profound implications: Internet of Things (IoT) : Emerging technology Internet of Things (IoT) is widely used in many sectors. The ultra-low power consumption directly translates to extended battery life for edge devices, enabling more complex and always-on sensing and processing at the edge [ 24 , 33 ]. Artificial Intelligence/Machine Learning : AI chips, particularly those performing inference, are power-bound. A reduction in PDP allows for either more operations per second (higher performance) within the same thermal envelope or the same performance at a drastically reduced power budget, enabling AI on mobile and embedded devices [ 2 , 25 ]. The faster delay also improves the clock frequency potential of AI accelerators. 4. Challenges in Nanosheet Fabrication The transition to NSFETs introduces significant fabrication complexities, which are a major focus of current research: Inner Spacer Formation: A critical innovation in NSFETs is the inner spacer, which isolates the source/drain epitaxy from the gate to reduce parasitic capacitance. Precise deposition and etchback of dielectric materials like silicon nitride (SiN) in the narrow gaps between nanosheets are extremely challenging [ 26 ]. Channel Release: Forming the GAA structure requires selectively etching away the sacrificial silicon-germanium (SiGe) layers from between the silicon nanosheets without damaging the Si channels or collapsing the stack. This requires highly selective etch chemistries [ 27 ]. Nanosheet Width Scaling and Strain: As the width of the nanosheets is reduced to improve electrostatics, the benefits of uniaxial strain from the source/drain stressors diminish, potentially impacting carrier mobility [ 28 ]. Morphological Stability: The mechanical stability of long, thin, and released silicon nanosheets is a concern, requiring robust processes to prevent deformation or collapse during fabrication [ 29 ]. 5. Future Outlook: Beyond Nanosheets Research is already looking beyond the NSFET. The Forksheet FET introduces a dielectric wall between the n-type and p-type nanosheets to reduce the n-p spacing further, enabling continued pitch scaling and reduced variability [ 30 ]. Further ahead, the Complementary FET (CFET) takes 3D integration to its logical conclusion by stacking nFETs on top of pFETs, effectively doubling the transistor density without increasing the silicon footprint [ 31 ]. 6. Conclusion The proliferation of AI and IoT applications across critical sectors including agriculture, healthcare, and manufacturing [ 32 – 35 ] has intensified the demand for high-performance computing architectures that operate under stringent power constraints. The transition from FinFETs to Nanosheet FETs represents a necessary architectural shift to maintain the pace of Moore's Law. While FinFETs solved the SCE problems of planar devices, their limitations at ultra-scaled nodes have made the superior electrostatic control of the GAA Nanosheet essential. Although NSFET fabrication presents significant challenges in areas like inner spacer formation and channel release, the industry has identified pathways to overcome these hurdles. Nanosheet technology is now in early production at the 3 nm/2 nm nodes, establishing itself as the workhorse for the next decade of advanced CMOS, while research continues into more advanced architectures like the Forksheet and CFET. This study utilized the Microwind 3.9 simulation environment to perform a comparative analysis of 5nm FinFET and 2nm GAA Nanosheet technologies. The results conclusively demonstrate the superior performance of the Nanosheet architecture, showcasing improvement in speed and reduction in power consumption.These improvements are fundamentally linked to the enhanced electrostatic control of the GAA structure, which permits aggressive scaling of the supply voltage without sacrificing performance. This transition is not merely an incremental improvement but a necessary architectural shift to sustain the progress of Moore's Law. The findings underscore why the semiconductor industry is adopting GAA Nanosheet technology at the 3nm/2nm nodes to power the next generation of ultra-low-power, high-performance computing applications, from ubiquitous IoT sensors to powerful AI accelerators. Future work would involve using more advanced simulation tools with industry-standard compact models (e.g., BSIM-CMG) for greater accuracy. Declarations Authors Declaration Authors declare no conflict of interest Funding: No funding received for this work Acknowledgement: The authors would like to acknowledge Microwind Simulation tool for its use in simulation and layout generation. References W. Haensch et al., "The next wave of computing: A world of intelligent things," IBM Journal of Research and Development, vol. 63, no. 6, pp. 1:1-1:10, 2019. M. Horowitz, "1.1 Computing's energy problem (and what we can do about it)," IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, pp. 10-14, 2014. R. H. Dennard et al., "Design of ion-implanted MOSFET's with very small physical dimensions," IEEE Journal of Solid-State Circuits, vol. 9, no. 5, pp. 256-268, Oct. 1974. D. Hisamoto et al., "A folded-channel MOSFET for deep-sub-tenth micron era," International Electron Devices Meeting (IEDM) Technical Digest, pp. 1032-1034, 1998. C. Auth et al., "A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors," Symposium on VLSI Technology (VLSIT), pp. 131-132, 2012. S. Natarajan et al., "A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm² SRAM cell size," IEEE International Electron Devices Meeting (IEDM), pp. 3.7.1-3.7.3, 2014. N. Loubet et al., "Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET," Symposium on VLSI Technology, pp. T230-T231, 2017. G. Bae et al., "3nm GAA technology featuring multi-bridge-channel FET for low power and high performance applications," IEEE International Electron Devices Meeting (IEDM), pp. 28.7.1-28.7.4, 2018. A. P. Chandrakasan and R. W. Brodersen, "Minimizing power consumption in digital CMOS circuits," Proceedings of the IEEE, vol. 83, no. 4, pp. 498-523, 1995. S. Barraud et al., "Performance and design considerations for Gate-All-Around stacked-NanoWires FETs," International Electron Devices Meeting (IEDM) Technical Digest , pp. 769-772, 2016. N. Loubet et al., "Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET," Symposium on VLSI Technology , pp. T230-T231, 2017. J. Zhang et al., "Full bottom dielectric isolation to enable stacked nanosheet transistor for low power and high performance applications," International Electron Devices Meeting (IEDM) Technical Digest , pp. 635-638, 2019. M. Guillorn et al., "Power performance benchmarking of nanosheet FETs for future technology nodes," IEEE Transactions on Electron Devices , vol. 67, no. 10, pp. 4053-4058, Oct. 2020. G. Bae et al., "3nm GAA technology featuring multi-bridge-channel FET for low power and high performance applications," International Electron Devices Meeting (IEDM) Technical Digest , pp. 28.7.1-28.7.4, 2018. S.-Y. Wu et al., "A 7nm CMOS platform technology featuring 4th generation FinFET transistors with a 0.027um² high density 6-T SRAM cell for mobile SoC applications," International Electron Devices Meeting (IEDM) Technical Digest , pp. 2.6.1-2.6.4, 2016. H. Mertens et al., "Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates," Symposium on VLSI Technology , pp. 1-2, 2016. Samsung Foundry, "Samsung Unveils Plans for 3nm GAA Technology Mass Production in 2022," Samsung Newsroom, 2021. G. Bae et al., "3nm GAA Technology Featuring Multi-Bridge-Channel FET for Low Power and High Performance Applications," in IEEE International Electron Devices Meeting (IEDM), 2018. TSMC, "TSMC Symposium 2023: N2 Technology Update," 2023. Intel Corporation, "Intel Accelerated Event," 2021. E. Sicard, "Microwind & Dsch Version 3.5 - A Tutorial," INSA, Toulouse, France, 2007. M. Bohr, "A 30 Year Retrospective on Dennard's MOSFET Scaling Paper," IEEE Solid-State Circuits Society Newsletter, vol. 12, no. 1, pp. 11-13, 2007. N. Loubet et al., "Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET," Symposium on VLSI Technology , pp. T230-T231, 2017. R. Divakaruni and V. Narayanan, “Challenges of 10 nm and 7 nm CMOS for server and mobile applications,” ECS Trans. , vol. 72, no. 4, pp. 3–14, May 2016. Radamson HH, Zhu H, Wu Z, He X, Lin H, Liu J, Xiang J, Kong Z, Xiong W, Li J, Cui H, Gao J, Yang H, Du Y, Xu B, Li B, Zhao X, Yu J, Dong Y, Wang G. State of the Art and Future Perspectives in Advanced CMOS Technology. Nanomaterials (Basel). 2020 Aug 7;10(8):1555. doi: 10.3390/nano10081555. PMID: 32784801; PMCID: PMC7466708. Yang J, Huang Z, Wang D, Liu T, Sun X, Qian L, Pan Z, Xu S, Wang C, Wu C, et al. A Novel Scheme for Full Bottom Dielectric Isolation in Stacked Si Nanosheet Gate-All-Around Transistors. Micromachines . 2023; 14(6):1107. https://doi.org/10.3390/mi14061107 P. K. Dubey, D. Marian, A. Toral-Lopez, T. Knobloch, T. Grasser, and G. Fiori, "Simulation of Vertically Stacked 2-D Nanosheet FETs," IEEE Trans. Electron Devices , vol. 72, no. 3, pp. 1200-1207, Mar. 2025. P. Weckx et al ., "Novel forksheet device architecture as ultimate logic scaling device towards 2nm," 2019 IEEE International Electron Devices Meeting (IEDM) , San Francisco, CA, USA, 2019, pp. 36.5.1-36.5.4, doi: 10.1109/IEDM19573.2019.8993635. J. Ryckaert et al ., "The Complementary FET (CFET) for CMOS scaling beyond N3," 2018 IEEE Symposium on VLSI Technology , Honolulu, HI, USA, 2018, pp. 141-142, doi: 10.1109/VLSIT.2018.8510618. Weckx, P., Gupta, M.K., Oniki, Y., Ragnarsson, L., Horiguchi, N., Spessot, A., Verkest, D., Ryckaert, J., Litta, E.D., Yakimets, D., Matagne, P., Schuddinck, P., Jang, D., Chehab, B., & Baert, R. (2019). Novel forksheet device architecture as ultimate logic scaling device towards 2nm. 2019 IEEE International Electron Devices Meeting (IEDM) , 36.5.1-36.5.4. P. Schuddinck et al. , "The Complementary FET (CFET) for CMOS Scaling Beyond N3," in Symposium on VLSI Technology , Honolulu, HI, USA, 2018, pp. 141-142. Ritu Raj Lamsal, Prahlad Acharya, Rijan Pokhrel et al. Integrating Machine Learning and RAG-Based Chatbot for Mandarin Orange Disease Detection in Hilly Region of Nepal, 27 February 2025, PREPRINT (Version 1) available at Research Square [https://doi.org/10.21203/rs.3.rs-6105402/v1] Lamsal, Ritu Raj. "A Review on Advancing Digital Transformation in Agritech: Focus on Nepal." International conference on Recent Trends in AI ICRTAI-2025, http://dx. doi. org/10.13140/RG . Vol. 2. G. Poornima, S. G. M. A., and R. R. Lamsal, "Revolutionizing Healthcare: The Synergy of Computer Vision and IoT Integration," in Future Innovations in the Convergence of AI and Internet of Things in Medicine , 1st ed., IGI Global, 2025, ch. 13, pp. 1-20, doi: 10.4018/979-8-3693-7703-1.ch013. Lamsal, R.R., Devkota, A. & Bhusal, M.S. Navigating Global Challenges: The Crucial Role of Semiconductors in Advancing Globalization. J. Inst. Eng. India Ser. B 104 , 1389–1399 (2023). https://doi.org/10.1007/s40031-023-00938-4 Additional Declarations The authors declare no competing interests. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-7705956","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":520122170,"identity":"e787b18c-f4e1-4b6d-a40f-35fc130cd96b","order_by":0,"name":"Ritu Raj Lamsal","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAAA3klEQVRIiWNgGAWjYBACPjBZACIOHwASEjIEtbCBSQMQcSwBpIWHFC08EJKwFvbTyR9+GDDk8zee+fzqRo0FDwP74aMb8Grhyd0m2WPAYDnjwNlt1jnHgA7jSUu7gd9hudtATjJgAGoxzmEDapHgMcOvhf/t5o9/gFrkD5x5ZpzzjxgtErkbpEG2GBw4w/w4t40oLW+3ScsYSBgYHjhmxpzbJ8HDRsgv/Py5mz++qbAxkLtx+PHnnG91cvzsh4/h1QIFEkB0gE0CbC8RymH2NTB/IF71KBgFo2AUjCQAAIVOQznoNQAOAAAAAElFTkSuQmCC","orcid":"https://orcid.org/0000-0002-3751-2785","institution":"Madan Bhandari University of Science and Technology","correspondingAuthor":true,"prefix":"","firstName":"Ritu","middleName":"Raj","lastName":"Lamsal","suffix":""},{"id":520122171,"identity":"fdec4860-2a7c-4f9f-b3e0-a7af6ccdaec4","order_by":1,"name":"Mamta Bhattarai","email":"","orcid":"","institution":"South Asian university","correspondingAuthor":false,"prefix":"","firstName":"Mamta","middleName":"","lastName":"Bhattarai","suffix":""}],"badges":[],"createdAt":"2025-09-24 17:10:23","currentVersionCode":1,"declarations":{"humanSubjects":false,"vertebrateSubjects":false,"conflictsOfInterestStatement":false,"humanSubjectEthicalGuidelines":false,"humanSubjectConsent":false,"humanSubjectClinicalTrial":false,"humanSubjectCaseReport":false,"vertebrateSubjectEthicalGuidelines":false},"doi":"10.21203/rs.3.rs-7705956/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-7705956/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":92238590,"identity":"862faf3f-4875-4180-8366-ff8365c9d00c","added_by":"auto","created_at":"2025-09-26 08:04:15","extension":"docx","order_by":0,"title":"","display":"","copyAsset":false,"role":"acdc-reference","size":759492,"visible":true,"origin":"","legend":"","description":"","filename":"TheFinFETtoNanosheetTransitionACriticalEnablerforEnergyEfficientAIoTApplications.docx","url":"https://assets-eu.researchsquare.com/files/rs-7705956/v1/a03494ed97818e31c2174e14.docx"},{"id":92239350,"identity":"26ae611e-54ad-4a67-beec-b398dc7aa548","added_by":"auto","created_at":"2025-09-26 08:12:15","extension":"json","order_by":1,"title":"","display":"","copyAsset":false,"role":"acdc-reference","size":342,"visible":true,"origin":"","legend":"","description":"","filename":"rs7705956.json","url":"https://assets-eu.researchsquare.com/files/rs-7705956/v1/f151936e69afb5dfc6d82fab.json"},{"id":92238610,"identity":"b580ec52-5a50-47bf-ac3b-15088306aac3","added_by":"auto","created_at":"2025-09-26 08:04:16","extension":"xml","order_by":2,"title":"","display":"","copyAsset":false,"role":"acdc-reference","size":67551,"visible":true,"origin":"","legend":"","description":"","filename":"rs77059560enriched.xml","url":"https://assets-eu.researchsquare.com/files/rs-7705956/v1/025b7778d7f6738cb7817865.xml"},{"id":92238598,"identity":"4143e6ca-7830-4ed5-82d9-b24d98ff2045","added_by":"auto","created_at":"2025-09-26 08:04:15","extension":"jpeg","order_by":3,"title":"","display":"","copyAsset":false,"role":"acdc-reference","size":273041,"visible":true,"origin":"","legend":"","description":"","filename":"floatimage1.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-7705956/v1/a4c0e8711e1947d30ded0ad1.jpeg"},{"id":92238594,"identity":"4648562d-94cc-4978-b9d4-87fba57d2e7a","added_by":"auto","created_at":"2025-09-26 08:04:15","extension":"jpeg","order_by":4,"title":"","display":"","copyAsset":false,"role":"acdc-reference","size":422258,"visible":true,"origin":"","legend":"","description":"","filename":"floatimage2.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-7705956/v1/3f98133ffcc8fc70be06498c.jpeg"},{"id":92238591,"identity":"7034632d-8cb0-44e5-a174-aa0bc7d200a2","added_by":"auto","created_at":"2025-09-26 08:04:15","extension":"jpeg","order_by":5,"title":"","display":"","copyAsset":false,"role":"acdc-reference","size":386340,"visible":true,"origin":"","legend":"","description":"","filename":"floatimage3.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-7705956/v1/5f2d8c82697a3df1a6db9d84.jpeg"},{"id":92238592,"identity":"1fab65bf-7d61-4e1e-b71b-6dc307ee1bb7","added_by":"auto","created_at":"2025-09-26 08:04:15","extension":"png","order_by":6,"title":"","display":"","copyAsset":false,"role":"acdc-reference","size":13700,"visible":true,"origin":"","legend":"","description":"","filename":"floatimage4.png","url":"https://assets-eu.researchsquare.com/files/rs-7705956/v1/ad9ef02c5cb9a657585eeafd.png"},{"id":92238608,"identity":"f416012c-4faa-4ee1-9e7e-82b9668c714e","added_by":"auto","created_at":"2025-09-26 08:04:16","extension":"jpeg","order_by":7,"title":"","display":"","copyAsset":false,"role":"acdc-reference","size":573567,"visible":true,"origin":"","legend":"","description":"","filename":"floatimage5.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-7705956/v1/ebc3c3f8574841b45aca16d1.jpeg"},{"id":92238606,"identity":"a33d4ec7-e546-4a1d-bd8e-b12d477076ba","added_by":"auto","created_at":"2025-09-26 08:04:16","extension":"jpeg","order_by":8,"title":"","display":"","copyAsset":false,"role":"acdc-reference","size":292686,"visible":true,"origin":"","legend":"","description":"","filename":"floatimage6.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-7705956/v1/096c6d812974ba0f915594a7.jpeg"},{"id":92238597,"identity":"8b576f2d-a980-4757-bbfc-a0b78cd7a17f","added_by":"auto","created_at":"2025-09-26 08:04:15","extension":"jpeg","order_by":9,"title":"","display":"","copyAsset":false,"role":"acdc-reference","size":331282,"visible":true,"origin":"","legend":"","description":"","filename":"floatimage7.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-7705956/v1/216a39cb89ee2e87e6abcb41.jpeg"},{"id":92239352,"identity":"aa8630b7-2818-47d7-a3d1-5802a559356b","added_by":"auto","created_at":"2025-09-26 08:12:15","extension":"png","order_by":10,"title":"","display":"","copyAsset":false,"role":"acdc-reference","size":42913,"visible":true,"origin":"","legend":"","description":"","filename":"Onlinefloatimage1.png","url":"https://assets-eu.researchsquare.com/files/rs-7705956/v1/36f5b2fca992087dee0edb22.png"},{"id":92238603,"identity":"1efcc084-50f2-4c12-a7d1-9509a35e2718","added_by":"auto","created_at":"2025-09-26 08:04:15","extension":"png","order_by":11,"title":"","display":"","copyAsset":false,"role":"acdc-reference","size":58708,"visible":true,"origin":"","legend":"","description":"","filename":"Onlinefloatimage2.png","url":"https://assets-eu.researchsquare.com/files/rs-7705956/v1/62488cbb13596fe0a7f3be22.png"},{"id":92238605,"identity":"ab2f946d-bd68-4097-832c-671708ccd3ec","added_by":"auto","created_at":"2025-09-26 08:04:16","extension":"png","order_by":12,"title":"","display":"","copyAsset":false,"role":"acdc-reference","size":59652,"visible":true,"origin":"","legend":"","description":"","filename":"Onlinefloatimage3.png","url":"https://assets-eu.researchsquare.com/files/rs-7705956/v1/9c228e59bd30e703288bd8fc.png"},{"id":92238607,"identity":"875b203c-b464-4ceb-b769-0e6a1bc5c453","added_by":"auto","created_at":"2025-09-26 08:04:16","extension":"png","order_by":13,"title":"","display":"","copyAsset":false,"role":"acdc-reference","size":6852,"visible":true,"origin":"","legend":"","description":"","filename":"Onlinefloatimage4.png","url":"https://assets-eu.researchsquare.com/files/rs-7705956/v1/180fc23be981501eeffe48e4.png"},{"id":92238600,"identity":"737f3c28-2441-4e0c-9bf5-7626d24e0a4d","added_by":"auto","created_at":"2025-09-26 08:04:15","extension":"png","order_by":14,"title":"","display":"","copyAsset":false,"role":"acdc-reference","size":76959,"visible":true,"origin":"","legend":"","description":"","filename":"Onlinefloatimage5.png","url":"https://assets-eu.researchsquare.com/files/rs-7705956/v1/06fb8dfb39a8ad61220b926a.png"},{"id":92238604,"identity":"f6b39ac0-6129-4299-b233-b848b20ac739","added_by":"auto","created_at":"2025-09-26 08:04:16","extension":"png","order_by":15,"title":"","display":"","copyAsset":false,"role":"acdc-reference","size":59321,"visible":true,"origin":"","legend":"","description":"","filename":"Onlinefloatimage6.png","url":"https://assets-eu.researchsquare.com/files/rs-7705956/v1/e99999a20915aa121234366e.png"},{"id":92239351,"identity":"f0591a9a-7ccb-4394-94d8-8e9d3fa7d04a","added_by":"auto","created_at":"2025-09-26 08:12:15","extension":"png","order_by":16,"title":"","display":"","copyAsset":false,"role":"acdc-reference","size":71944,"visible":true,"origin":"","legend":"","description":"","filename":"Onlinefloatimage7.png","url":"https://assets-eu.researchsquare.com/files/rs-7705956/v1/f7d99129380142dd75ff5e1f.png"},{"id":92238602,"identity":"58abafa4-3497-4eef-80aa-07012a698a03","added_by":"auto","created_at":"2025-09-26 08:04:15","extension":"xml","order_by":17,"title":"","display":"","copyAsset":false,"role":"acdc-reference","size":66255,"visible":true,"origin":"","legend":"","description":"","filename":"rs77059560structuring.xml","url":"https://assets-eu.researchsquare.com/files/rs-7705956/v1/638e10817c0507c2906d91ee.xml"},{"id":92238609,"identity":"2800868f-24e8-49bc-b077-74af68bc66a8","added_by":"auto","created_at":"2025-09-26 08:04:16","extension":"html","order_by":18,"title":"","display":"","copyAsset":false,"role":"acdc-reference","size":75210,"visible":true,"origin":"","legend":"","description":"","filename":"earlyproof.html","url":"https://assets-eu.researchsquare.com/files/rs-7705956/v1/460080ef797fefadaf3fdf89.html"},{"id":92238586,"identity":"8642a046-e7dd-4cc3-bf02-5babc798e842","added_by":"auto","created_at":"2025-09-26 08:04:15","extension":"png","order_by":1,"title":"Figure 1","display":"","copyAsset":false,"role":"figure","size":91340,"visible":true,"origin":"","legend":"\u003cp\u003e(a) FinFET Parameters\u003c/p\u003e\n\u003cp\u003e(b) Nanosheet FET Parameters\u003c/p\u003e","description":"","filename":"1.png","url":"https://assets-eu.researchsquare.com/files/rs-7705956/v1/74e18d81276cc35b405fa701.png"},{"id":92238611,"identity":"8efa1dd3-98eb-468c-a69d-6a71164645fb","added_by":"auto","created_at":"2025-09-26 08:04:16","extension":"png","order_by":2,"title":"Figure 2","display":"","copyAsset":false,"role":"figure","size":146566,"visible":true,"origin":"","legend":"\u003cp\u003eFinFET Inverter Layout , 3d view and layers\u003c/p\u003e","description":"","filename":"2.png","url":"https://assets-eu.researchsquare.com/files/rs-7705956/v1/3101799495aaa01004d7890f.png"},{"id":92238587,"identity":"564d887b-24fd-4db1-8dfb-047cf35e5d89","added_by":"auto","created_at":"2025-09-26 08:04:15","extension":"png","order_by":3,"title":"Figure 3","display":"","copyAsset":false,"role":"figure","size":114923,"visible":true,"origin":"","legend":"\u003cp\u003eGAA Nanosheet Inverter Layout, 3d view and Layers\u003c/p\u003e","description":"","filename":"3.png","url":"https://assets-eu.researchsquare.com/files/rs-7705956/v1/ec77d108f4586d8aa9b4cb12.png"},{"id":92238589,"identity":"c9b40ab5-46cd-494e-aa35-1f5d54ca2d33","added_by":"auto","created_at":"2025-09-26 08:04:15","extension":"png","order_by":4,"title":"Figure 4","display":"","copyAsset":false,"role":"figure","size":50387,"visible":true,"origin":"","legend":"\u003cp\u003eClock frequency and its parameters\u003c/p\u003e","description":"","filename":"4.png","url":"https://assets-eu.researchsquare.com/files/rs-7705956/v1/8647d8df803ada3d88ec5576.png"},{"id":92238595,"identity":"e33035e1-e4f4-4196-b488-323bf94361d5","added_by":"auto","created_at":"2025-09-26 08:04:15","extension":"png","order_by":5,"title":"Figure 5","display":"","copyAsset":false,"role":"figure","size":197810,"visible":true,"origin":"","legend":"\u003cp\u003eVarious characteristics of FinFET Inverter\u003c/p\u003e","description":"","filename":"5.png","url":"https://assets-eu.researchsquare.com/files/rs-7705956/v1/7a1404c215720bb41df01ead.png"},{"id":92238599,"identity":"e24e1477-2eee-4c93-bd62-6101a4018cf4","added_by":"auto","created_at":"2025-09-26 08:04:15","extension":"png","order_by":6,"title":"Figure 6","display":"","copyAsset":false,"role":"figure","size":219645,"visible":true,"origin":"","legend":"\u003cp\u003eVarious characteristics of GAA nanosheet Inverter\u003c/p\u003e","description":"","filename":"6.png","url":"https://assets-eu.researchsquare.com/files/rs-7705956/v1/437dfdbf65dd0b1cc5477b7c.png"},{"id":92239483,"identity":"8f43a8dc-e04b-4713-810d-c86050c84c60","added_by":"auto","created_at":"2025-09-26 08:20:20","extension":"pdf","order_by":0,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":1336920,"visible":true,"origin":"","legend":"","description":"","filename":"manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-7705956/v1/4a5725e4-60fc-4b6b-beac-bfc59a3f5db0.pdf"}],"financialInterests":"The authors declare no competing interests.","formattedTitle":"\u003cp\u003e\u003cstrong\u003eThe FinFET to Nanosheet Transition: A Critical Enabler for Energy-Efficient AIoT Applications\u003c/strong\u003e\u003c/p\u003e","fulltext":[{"header":"1. Introduction","content":"\u003cdiv id=\"Sec2\" class=\"Section2\"\u003e\u003ch2\u003e1.1 The Era of the FinFET\u003c/h2\u003e\u003cp\u003eThe insatiable demand for higher processing power and superior energy efficiency in modern electronics, driven by transformative technologies like Artificial Intelligence (AI) and the Internet of Things (IoT), relentlessly pushes the boundaries of semiconductor technology [\u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e]. This demand creates a dual challenge: IoT edge devices require ultra-low-power processors to operate autonomously for years on miniature batteries, while AI training and inference demand immense computational throughput within strict thermal budgets, making power density a first-order design constraint [\u003cspan citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e]. Meeting these demands hinges on the continued scaling of transistor technology. For decades, this scaling was successfully achieved through the planar Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). However, as gate lengths approached the sub-30 nm regime, the industry encountered fundamental physical barriers. The inability to maintain electrostatic control over the channel led to severe short-channel effects (SCEs), characterized by exponential increases in leakage current and threshold voltage roll-off, rendering further planar scaling impractical [\u003cspan citationid=\"CR3\" class=\"CitationRef\"\u003e3\u003c/span\u003e].\u003c/p\u003e\u003cp\u003eThis crisis precipitated a fundamental architectural shift. The seminal work by Hisamoto et al. introduced the concept of a three-dimensional transistor, the precursor to the modern FinFET, which demonstrated significantly improved SCE immunity [\u003cspan citationid=\"CR4\" class=\"CitationRef\"\u003e4\u003c/span\u003e]. The FinFET architecture addressed the limitations of the planar device by raising a narrow silicon \"fin\" from the substrate, allowing the gate to wrap around three sides of the channel. This provided vastly superior electrostatic control compared to its planar predecessor [\u003cspan citationid=\"CR5\" class=\"CitationRef\"\u003e5\u003c/span\u003e]. The industry's adoption of FinFETs, led by Intel at the 22 nm node, marked a critical inflection point, enabling continued performance and density scaling for nearly a decade [\u003cspan citationid=\"CR6\" class=\"CitationRef\"\u003e6\u003c/span\u003e]. FinFETs offered compelling advantages, including higher on-state current (I\u003csub\u003eON\u003c/sub\u003e) for a given footprint, lower leakage current (I\u003csub\u003eOFF\u003c/sub\u003e), and a reduced subthreshold swing (SS).\u003c/p\u003e\u003cp\u003eNevertheless, as scaling approaches the 5 nm node and beyond, the limitations of the FinFET architecture have become pronounced. Challenges in further fin width scaling, increased variability, and ultimately insufficient gate control\u0026mdash;stemming from the gate only contacting three sides of the channel\u0026mdash;lead to rising leakage currents, once again threatening the path of Moore's Law [\u003cspan citationid=\"CR7\" class=\"CitationRef\"\u003e7\u003c/span\u003e].\u003c/p\u003e\u003cp\u003eIn response, the Gate-All-Around (GAA) transistor, specifically the Nanosheet FET (NSFET), has emerged as the designated successor to the FinFET. This architecture represents the logical culmination of 3D design, where the gate material completely surrounds a stack of horizontal silicon channels (nanosheets) [\u003cspan citationid=\"CR8\" class=\"CitationRef\"\u003e8\u003c/span\u003e]. This configuration provides the ultimate electrostatic control, effectively suppressing SCEs at the 2 nm node and below. A key benefit of this enhanced control is the ability to further reduce the operating voltage (V\u003csub\u003eDD\u003c/sub\u003e), which quadratically reduces dynamic power consumption and directly lowers leakage current [\u003cspan citationid=\"CR9\" class=\"CitationRef\"\u003e9\u003c/span\u003e]. These characteristics make GAA Nanosheet technology uniquely suited to address the critical need for high-performance, ultra-low-power hardware required for the next generation of AI and IoT applications [\u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e, \u003cspan citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e].\u003c/p\u003e\u003c/div\u003e\u003cdiv id=\"Sec3\" class=\"Section2\"\u003e\u003ch2\u003e\u003cb\u003e1.2 Limitations of the FinFET at Scaled Nodes\u003c/b\u003e\u003c/h2\u003e\u003cp\u003eDespite its success, the FinFET faces fundamental physical limitations as the contacted poly pitch (CPP) and fin pitch are scaled down below 5 nm. Key challenges identified in the literature include:\u003c/p\u003e\u003cp\u003e\u003cul\u003e\u003cli\u003e\u003cp\u003eElectrostatic Control: In a FinFET, the gate only wraps around three sides of the channel, leaving a bottom interface that is vulnerable to leakage paths. At ultra-scaled fin widths, variability in fin patterning and line-edge roughness becomes a significant issue for performance and yield [\u003cspan citationid=\"CR10\" class=\"CitationRef\"\u003e10\u003c/span\u003e].\u003c/p\u003e\u003c/li\u003e\u003cli\u003e\u003cp\u003eDrive Current Limitations: The drive current of a FinFET is proportional to the fin height. To increase current, designers must either increase fin height (leading to difficult high-aspect-ratio etching and filling processes) or place multiple fins in parallel (consuming more area and increasing parasitic capacitance) [\u003cspan citationid=\"CR11\" class=\"CitationRef\"\u003e11\u003c/span\u003e].\u003c/p\u003e\u003c/li\u003e\u003cli\u003e\u003cp\u003eV\u003csub\u003eT\u003c/sub\u003e Tuning and Work Function Metal Deposition: Conformal deposition of work function metals (WFM) on the three-dimensional fin structure becomes increasingly challenging with pitch scaling. Inadequate WFM deposition leads to poor threshold voltage (V\u003csub\u003eT\u003c/sub\u003e) control and variability [\u003cspan citationid=\"CR12\" class=\"CitationRef\"\u003e12\u003c/span\u003e].\u003c/p\u003e\u003c/li\u003e\u003c/ul\u003e\u003c/p\u003e\u003cp\u003eThese limitations necessitated a new architecture with even more robust electrostatic integrity: the Gate-All-Around (GAA) transistor.\u003c/p\u003e\u003c/div\u003e\u003cdiv id=\"Sec4\" class=\"Section2\"\u003e\u003ch2\u003e1.3. The Gate-All-Around Nanosheet FET: A Superior Successor\u003c/h2\u003e\u003cp\u003eThe Nanosheet FET represents the logical evolution beyond the FinFET. Instead of a vertical fin, the NSFET features multiple horizontal sheets of silicon stacked on top of one another, with the gate material wrapping around each sheet completely. This true GAA structure provides the ultimate electrostatic control, effectively suppressing SCEs at the sub-5 nm node [\u003cspan citationid=\"CR13\" class=\"CitationRef\"\u003e13\u003c/span\u003e].\u003c/p\u003e\u003cp\u003eKey Advantages of NSFETs:\u003c/p\u003e\u003cp\u003e\u003cul\u003e\u003cli\u003e\u003cp\u003eEnhanced Electrostatic Control: The GAA configuration provides superior control over the channel, resulting in a near-ideal subthreshold swing and significantly reduced drain-induced barrier lowering (DIBL) compared to FinFET at the same gate length [\u003cspan citationid=\"CR14\" class=\"CitationRef\"\u003e14\u003c/span\u003e].\u003c/p\u003e\u003c/li\u003e\u003cli\u003e\u003cp\u003eHigher Drive Current per Footprint: The drive current is proportional to the total width of the nanosheet. By stacking multiple sheets vertically, a much larger effective width can be achieved within the same footprint as a single fin, leading to higher performance without area penalty [\u003cspan citationid=\"CR15\" class=\"CitationRef\"\u003e15\u003c/span\u003e].\u003c/p\u003e\u003c/li\u003e\u003cli\u003e\u003cp\u003eBetter V\u003csub\u003eT\u003c/sub\u003e Tunability: The structure allows for independent tuning of nanosheet thickness and width, providing an additional knob for designers to optimize performance and power [\u003cspan citationid=\"CR16\" class=\"CitationRef\"\u003e16\u003c/span\u003e]. Furthermore, WFM deposition on horizontal surfaces is generally considered more manageable than on complex fin sidewalls.\u003c/p\u003e\u003c/li\u003e\u003c/ul\u003e\u003c/p\u003e\u003c/div\u003e\u003cdiv id=\"Sec5\" class=\"Section2\"\u003e\u003ch2\u003e1.4 State of the Art Global Foundries for Nanosheet Fabrication\u003c/h2\u003e\u003cp\u003eSamsung Foundry currently stands as the primary manufacturer of chips utilizing nanosheet transistors, having achieved a significant industry milestone by initiating volume production of its 3nm node with Multi-Bridge-Channel FET (MBCFET\u0026trade;) technology in 2022. This accomplishment positioned Samsung as the pioneer in commercializing the Gate-All-Around (GAA) architecture [\u003cspan citationid=\"CR17\" class=\"CitationRef\"\u003e17\u003c/span\u003e]. The competitive landscape, however, is dynamic. Taiwan Semiconductor Manufacturing Company (TSMC), the global foundry leader, is preparing to introduce its own nanosheet technology with a planned volume production of its 2nm (N2) node in 2025 [\u003cspan citationid=\"CR18\" class=\"CitationRef\"\u003e18\u003c/span\u003e, \u003cspan citationid=\"CR19\" class=\"CitationRef\"\u003e19\u003c/span\u003e]. Meanwhile, Intel Foundry's path has involved a strategic pivot. While the company developed its Intel 20A node\u0026mdash;featuring its RibbonFET GAA technology\u0026mdash;as a crucial testbed for foundational innovations, it announced a significant shift in September 2024 [\u003cspan citationid=\"CR20\" class=\"CitationRef\"\u003e20\u003c/span\u003e]. Intel canceled the 20A node for commercial production, opting instead to leverage external foundry partners like TSMC for products such as its Arrow Lake CPUs. This decision, aimed at cost-saving and resource optimization, allows Intel to redirect efforts toward accelerating the volume production of its more advanced 18A (1.8nm-class) node.\u003c/p\u003e\u003cp\u003eConsequently, while Samsung presently leads in production volume, the industry is converging on GAA technology. By 2025, both Samsung and TSMC are projected to have nanosheet-based processes in high-volume manufacturing. Intel aims to join them with its refined 18A node, collectively establishing GAA transistors as the new industry standard for the most advanced semiconductor nodes.\u003c/p\u003e\u003cp\u003e\u003cdiv class=\"gridtable\"\u003e\u003ctable float=\"Yes\" id=\"Tab1\" border=\"1\"\u003e\u003ccaption language=\"En\"\u003e\u003cdiv class=\"CaptionNumber\"\u003eTable 1\u003c/div\u003e\u003cdiv class=\"CaptionContent\"\u003e\u003cp\u003eSummary of State of the Art Foundries\u003c/p\u003e\u003c/div\u003e\u003c/caption\u003e\u003ccolgroup cols=\"4\"\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c1\" colnum=\"1\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c2\" colnum=\"2\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c3\" colnum=\"3\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c4\" colnum=\"4\"\u003e\u003c/div\u003e\u003cthead\u003e\u003ctr\u003e\u003cth align=\"left\" colname=\"c1\"\u003e\u003cp\u003eFoundry / Company\u003c/p\u003e\u003c/th\u003e\u003cth align=\"left\" colname=\"c2\"\u003e\u003cp\u003eTechnology Node\u003c/p\u003e\u003c/th\u003e\u003cth align=\"left\" colname=\"c3\"\u003e\u003cp\u003eName for Nanosheet Tech\u003c/p\u003e\u003c/th\u003e\u003cth align=\"left\" colname=\"c4\"\u003e\u003cp\u003eStatus (as of 2024)\u003c/p\u003e\u003c/th\u003e\u003c/tr\u003e\u003c/thead\u003e\u003ctbody\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c1\"\u003e\u003cp\u003eSamsung Foundry\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003e3nm (SF3), 2nm (SF2)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003eMBCFET\u0026trade;\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003eIn Production\u0026nbsp;(since 2022 for 3nm)\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c1\"\u003e\u003cp\u003eTSMC\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003e2nm (N2)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003eNanosheet (GAA)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003eVolume Production planned for\u0026nbsp;2025\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c1\"\u003e\u003cp\u003eIntel Foundry\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003e20A (2nm-class)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003eRibbonFET\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003ePlanned for\u0026nbsp;2024 ( Cancelled later)\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003c/tbody\u003e\u003c/colgroup\u003e\u003c/table\u003e\u003c/div\u003e\u003c/p\u003e\u003c/div\u003e"},{"header":"2. Materials and Methods","content":"\u003cp\u003eThe analysis was conducted using Microwind version 3.9, an integrated circuit design and simulation tool for educational purposes. It features a built-in MOS scaling utility and a basic model for GAA transistors, allowing for a first-order comparison of different technology nodes [\u003cspan citationid=\"CR21\" class=\"CitationRef\"\u003e21\u003c/span\u003e]. Figure\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003e illustrates the parameters associated with FinFET and nanosheet FET. It is important to note that the results are based on predictive and simplified models and are intended for trend analysis rather than absolute accuracy.\u003c/p\u003e\u003cp\u003e\u003c/p\u003e\u003cdiv id=\"Sec7\" class=\"Section2\"\u003e\u003ch2\u003e2.2 Test Vehicle\u003c/h2\u003e\u003cp\u003eA standard CMOS inverter was chosen as the fundamental test vehicle for this analysis. The layout and three dimensional model is shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e2\u003c/span\u003e and Fig.\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003e for FinFET and GAA Nanosheet respectively. Its simplicity allows for clear isolation and measurement of intrinsic device properties like delay and switching power.\u003c/p\u003e\u003cp\u003e\u003c/p\u003e\u003cp\u003e\u003c/p\u003e\u003c/div\u003e\u003cdiv id=\"Sec8\" class=\"Section2\"\u003e\u003ch2\u003e2.3 Simulation Setup\u003c/h2\u003e\u003cp\u003eTwo separate designs were created for 5nm FinFET Inverter and 2nm Nanosheet FET inverter as shown in Figs.\u0026nbsp;\u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e2\u003c/span\u003e and \u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003e. A supply voltage (V\u003csub\u003eDD\u003c/sub\u003e) of 0.65V was applied, consistent with industry projections for this node [22, 23].\u003c/p\u003e\u003cp\u003e\u003c/p\u003e\u003cp\u003eFor a fair comparison, both inverters were designed to drive an identical load capacitor (C\u003csub\u003eL\u003c/sub\u003e = 5fF). The input was driven by a pulse voltage source with a rise/fall time of 0.05ns and a period of 0.1ns.\u003c/p\u003e\u003cp\u003e\u003cb\u003e2.4 Analysis Methodology\u003c/b\u003e\u003c/p\u003e\u003cp\u003e\u003cul\u003e\u003cli\u003e\u003cp\u003e\u003cb\u003eTransient Analysis\u003c/b\u003e: Used to measure the propagation delay t\u003csub\u003ep\u003c/sub\u003e from the 50% point of the input signal to the 50% point of the output signal.\u003c/p\u003e\u003c/li\u003e\u003cli\u003e\u003cp\u003e\u003cb\u003ePower Analysis\u003c/b\u003e: Power Consumption feature was used to obtain the average dynamic power consumption during switching.\u003c/p\u003e\u003c/li\u003e\u003cli\u003e\u003cp\u003e\u003cb\u003eDC Analysis\u003c/b\u003e: Used to plot the Voltage Transfer Characteristic (VTC) and estimate the static (leakage) power by measuring the current at stable input states (V\u003csub\u003ein\u003c/sub\u003e = 0V and V\u003csub\u003eIN\u003c/sub\u003e=V\u003csub\u003eDD\u003c/sub\u003e).\u003c/p\u003e\u003c/li\u003e\u003c/ul\u003e\u003c/p\u003e\u003c/div\u003e"},{"header":"3. Results and Discussion","content":"\u003cp\u003eVarious analysis plots for 5nm FinFET are shown in Fig. \u003cspan class=\"InternalRef\"\u003e5\u003c/span\u003e. The DC analysis Fig. \u003cspan class=\"InternalRef\"\u003e5\u003c/span\u003e (a) reveals the switching Characteristics of the inverter. The voltage verses time plot is shown in Fig. \u003cspan class=\"InternalRef\"\u003e5\u003c/span\u003e(b) similarly voltage vs current and frequency verses time plots are depicted in Fig. \u003cspan class=\"InternalRef\"\u003e5\u003c/span\u003e (c) and (d) respectively. The simulation is run for 2 nano second in interval of 100ps. The power consumption is 19.134 microwatts at 27 degree celcius. The average delay is estimated around 10 ps. The noise margin is estimated as\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eHigh-level noise margin (NMH)\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eNMH\u0026thinsp;=\u0026thinsp;VOH\u0026ndash;VIH\u0026thinsp;\u0026asymp;\u0026thinsp;\u003cstrong\u003e0.65 V \u0026ndash; 0.33 V\u0026thinsp;=\u0026thinsp;0.32 V\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eLow-level noise margin (NML)\u003c/strong\u003e :\u003c/p\u003e\n\u003cp\u003eNML\u0026thinsp;=\u0026thinsp;VIL\u0026ndash;VOL\u0026thinsp;\u0026asymp;\u0026thinsp;\u003cstrong\u003e0.28 V \u0026ndash; 0.0 V\u0026thinsp;=\u0026thinsp;0.28 V\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eSimilarly Fig. \u003cspan class=\"InternalRef\"\u003e6\u003c/span\u003e depicts various characteristics of GAA nanosheet. Nanosheet shows lower power consumption 18.03 \u0026micro;W vs 19.219 \u0026micro;W. This demonstrates the better electrostatic control of GAA architecture and Lower leakage currents contribute to reduced static power.\u003c/p\u003e\n\u003cp\u003eThe VTC of the 2nm NSFET inverter is steeper and more ideal than that of the 5nm FinFET, indicating a higher gain and better noise margins. This is a direct result of the enhanced electrostatic integrity of the GAA structure, which leads to a sharper transition from the off-state to the on-state. The simulation results show a faster switching response for the 2nm Nanosheet inverter. Transient analysis was performed to compare the switching speed. The key insights drawn from the overall analysis is summarized below:\u003c/p\u003e\n\u003cp\u003e\u003cspan\u003e\u003c/span\u003e\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eI. Speed Improvement (Delay)\u003c/strong\u003e: The transition from a three-sided gate (FinFET) to a four-sided, full-wrap gate (GAA Nanosheet) provides ultimate electrostatic control. This suppresses drain-induced barrier lowering (DIBL) and allows for more aggressive channel scaling, resulting in a higher on-state current (I\u003csub\u003eON\u003c/sub\u003e) and thus faster circuit switching\u003c/p\u003e\u003cspan\u003e\n \u003cp\u003e\u003cstrong\u003eII. Power Improvement (Power)\u003c/strong\u003e: The foundational benefit of the GAA structure is its ability to maintain performance at a significantly lower threshold voltage (V\u003csub\u003eth\u003c/sub\u003e) and supply voltage (V\u003csub\u003eDD\u003c/sub\u003e) without succumbing to leakage. Since dynamic power has a quadratic dependence on V\u003csub\u003eDD\u003c/sub\u003e, even a modest reduction in voltage yields substantial power savings. The 2nm node leverages this to operate at 0.55V, drastically cutting active power.\u003c/p\u003e\n\u003c/span\u003e\u003cspan\u003e\n \u003cp\u003e\u003cstrong\u003eIII. Efficiency Improvement (PDP)\u003c/strong\u003e: The PDP metric combines speed and power. The Nanosheet\u0026apos;s architecture delivers a \u0026quot;win-win\u0026quot; scenario: it is both faster and consumes less power per operation. This synergistic improvement makes the 2nm GAA technology vastly more energy-efficient than the 5nm FinFET node, which is essential for extending battery life in mobile devices and reducing the enormous energy footprint of data centers.\u003c/p\u003e\n\u003c/span\u003e\n\u003cp\u003e\u003c/p\u003e\n\u003cdiv id=\"Sec10\" class=\"Section2\"\u003e\n \u003ch2\u003e3.4 Implications for Emerging Technologies (AI, ML, IoT)\u003c/h2\u003e\n \u003cp\u003eThe results have profound implications:\u003c/p\u003e\n \u003cul\u003e\n \u003cli\u003e\n \u003cp\u003e\u003cstrong\u003eInternet of Things (IoT)\u003c/strong\u003e: Emerging technology Internet of Things (IoT) is widely used in many sectors. The ultra-low power consumption directly translates to extended battery life for edge devices, enabling more complex and always-on sensing and processing at the edge [\u003cspan class=\"CitationRef\"\u003e24\u003c/span\u003e, \u003cspan class=\"CitationRef\"\u003e33\u003c/span\u003e].\u003c/p\u003e\n \u003c/li\u003e\n \u003cli\u003e\n \u003cp\u003e\u003cstrong\u003eArtificial Intelligence/Machine Learning\u003c/strong\u003e: AI chips, particularly those performing inference, are power-bound. A reduction in PDP allows for either more operations per second (higher performance) within the same thermal envelope or the same performance at a drastically reduced power budget, enabling AI on mobile and embedded devices [\u003cspan class=\"CitationRef\"\u003e2\u003c/span\u003e, \u003cspan class=\"CitationRef\"\u003e25\u003c/span\u003e]. The faster delay also improves the clock frequency potential of AI accelerators.\u003c/p\u003e\n \u003c/li\u003e\n \u003c/ul\u003e\n\u003c/div\u003e"},{"header":"4. Challenges in Nanosheet Fabrication","content":"\u003cp\u003eThe transition to NSFETs introduces significant fabrication complexities, which are a major focus of current research:\u003c/p\u003e\u003cp\u003e\u003cul\u003e\u003cli\u003e\u003cp\u003eInner Spacer Formation: A critical innovation in NSFETs is the inner spacer, which isolates the source/drain epitaxy from the gate to reduce parasitic capacitance. Precise deposition and etchback of dielectric materials like silicon nitride (SiN) in the narrow gaps between nanosheets are extremely challenging [\u003cspan citationid=\"CR25\" class=\"CitationRef\"\u003e26\u003c/span\u003e].\u003c/p\u003e\u003c/li\u003e\u003cli\u003e\u003cp\u003eChannel Release: Forming the GAA structure requires selectively etching away the sacrificial silicon-germanium (SiGe) layers from between the silicon nanosheets without damaging the Si channels or collapsing the stack. This requires highly selective etch chemistries [\u003cspan citationid=\"CR26\" class=\"CitationRef\"\u003e27\u003c/span\u003e].\u003c/p\u003e\u003c/li\u003e\u003cli\u003e\u003cp\u003eNanosheet Width Scaling and Strain: As the width of the nanosheets is reduced to improve electrostatics, the benefits of uniaxial strain from the source/drain stressors diminish, potentially impacting carrier mobility [\u003cspan citationid=\"CR27\" class=\"CitationRef\"\u003e28\u003c/span\u003e].\u003c/p\u003e\u003c/li\u003e\u003cli\u003e\u003cp\u003eMorphological Stability: The mechanical stability of long, thin, and released silicon nanosheets is a concern, requiring robust processes to prevent deformation or collapse during fabrication [\u003cspan citationid=\"CR28\" class=\"CitationRef\"\u003e29\u003c/span\u003e].\u003c/p\u003e\u003c/li\u003e\u003c/ul\u003e\u003c/p\u003e"},{"header":"5. Future Outlook: Beyond Nanosheets","content":"\u003cp\u003eResearch is already looking beyond the NSFET. The Forksheet FET introduces a dielectric wall between the n-type and p-type nanosheets to reduce the n-p spacing further, enabling continued pitch scaling and reduced variability [\u003cspan citationid=\"CR29\" class=\"CitationRef\"\u003e30\u003c/span\u003e]. Further ahead, the Complementary FET (CFET) takes 3D integration to its logical conclusion by stacking nFETs on top of pFETs, effectively doubling the transistor density without increasing the silicon footprint [\u003cspan citationid=\"CR30\" class=\"CitationRef\"\u003e31\u003c/span\u003e].\u003c/p\u003e"},{"header":"6. Conclusion","content":"\u003cp\u003eThe proliferation of AI and IoT applications across critical sectors including agriculture, healthcare, and manufacturing [\u003cspan additionalcitationids=\"CR33 CR34\" citationid=\"CR31\" class=\"CitationRef\"\u003e32\u003c/span\u003e\u0026ndash;\u003cspan citationid=\"CR34\" class=\"CitationRef\"\u003e35\u003c/span\u003e] has intensified the demand for high-performance computing architectures that operate under stringent power constraints.\u003c/p\u003e\u003cp\u003eThe transition from FinFETs to Nanosheet FETs represents a necessary architectural shift to maintain the pace of Moore's Law. While FinFETs solved the SCE problems of planar devices, their limitations at ultra-scaled nodes have made the superior electrostatic control of the GAA Nanosheet essential. Although NSFET fabrication presents significant challenges in areas like inner spacer formation and channel release, the industry has identified pathways to overcome these hurdles. Nanosheet technology is now in early production at the 3 nm/2 nm nodes, establishing itself as the workhorse for the next decade of advanced CMOS, while research continues into more advanced architectures like the Forksheet and CFET. This study utilized the Microwind 3.9 simulation environment to perform a comparative analysis of 5nm FinFET and 2nm GAA Nanosheet technologies. The results conclusively demonstrate the superior performance of the Nanosheet architecture, showcasing improvement in speed and reduction in power consumption.These improvements are fundamentally linked to the enhanced electrostatic control of the GAA structure, which permits aggressive scaling of the supply voltage without sacrificing performance. This transition is not merely an incremental improvement but a necessary architectural shift to sustain the progress of Moore's Law. The findings underscore why the semiconductor industry is adopting GAA Nanosheet technology at the 3nm/2nm nodes to power the next generation of ultra-low-power, high-performance computing applications, from ubiquitous IoT sensors to powerful AI accelerators. Future work would involve using more advanced simulation tools with industry-standard compact models (e.g., BSIM-CMG) for greater accuracy.\u003c/p\u003e"},{"header":"Declarations","content":"\u003cp\u003e\u003ch2\u003eAuthors Declaration\u003c/h2\u003e\u003cp\u003eAuthors declare no conflict of interest\u003c/p\u003e\u003c/p\u003e\u003ch2\u003eFunding:\u003c/h2\u003e\u003cp\u003eNo funding received for this work\u003c/p\u003e\u003ch2\u003eAcknowledgement:\u003c/h2\u003e\u003cp\u003eThe authors would like to acknowledge Microwind Simulation tool for its use in simulation and layout generation.\u003c/p\u003e"},{"header":"References","content":"\u003col\u003e\n \u003cli\u003eW. Haensch et al., \u0026quot;The next wave of computing: A world of intelligent things,\u0026quot; IBM Journal of Research and Development, vol. 63, no. 6, pp. 1:1-1:10, 2019.\u003c/li\u003e\n \u003cli\u003eM. Horowitz, \u0026quot;1.1 Computing\u0026apos;s energy problem (and what we can do about it),\u0026quot; IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, pp. 10-14, 2014.\u003c/li\u003e\n \u003cli\u003eR. H. Dennard et al., \u0026quot;Design of ion-implanted MOSFET\u0026apos;s with very small physical dimensions,\u0026quot; IEEE Journal of Solid-State Circuits, vol. 9, no. 5, pp. 256-268, Oct. 1974.\u003c/li\u003e\n \u003cli\u003eD. Hisamoto et al., \u0026quot;A folded-channel MOSFET for deep-sub-tenth micron era,\u0026quot; International Electron Devices Meeting (IEDM) Technical Digest, pp. 1032-1034, 1998.\u003c/li\u003e\n \u003cli\u003eC. Auth et al., \u0026quot;A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors,\u0026quot; Symposium on VLSI Technology (VLSIT), pp. 131-132, 2012.\u003c/li\u003e\n \u003cli\u003eS. Natarajan et al., \u0026quot;A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 \u0026micro;m\u0026sup2; SRAM cell size,\u0026quot; IEEE International Electron Devices Meeting (IEDM), pp. 3.7.1-3.7.3, 2014.\u003c/li\u003e\n \u003cli\u003eN. Loubet et al., \u0026quot;Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET,\u0026quot; Symposium on VLSI Technology, pp. T230-T231, 2017.\u003c/li\u003e\n \u003cli\u003eG. Bae et al., \u0026quot;3nm GAA technology featuring multi-bridge-channel FET for low power and high performance applications,\u0026quot; IEEE International Electron Devices Meeting (IEDM), pp. 28.7.1-28.7.4, 2018.\u003c/li\u003e\n \u003cli\u003eA. P. Chandrakasan and R. W. Brodersen, \u0026quot;Minimizing power consumption in digital CMOS circuits,\u0026quot; Proceedings of the IEEE, vol. 83, no. 4, pp. 498-523, 1995.\u003c/li\u003e\n \u003cli\u003eS. Barraud et al., \u0026quot;Performance and design considerations for Gate-All-Around stacked-NanoWires FETs,\u0026quot; \u003cem\u003eInternational Electron Devices Meeting (IEDM) Technical Digest\u003c/em\u003e, pp. 769-772, 2016.\u003c/li\u003e\n \u003cli\u003eN. Loubet et al., \u0026quot;Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET,\u0026quot; \u003cem\u003eSymposium on VLSI Technology\u003c/em\u003e, pp. T230-T231, 2017.\u003c/li\u003e\n \u003cli\u003eJ. Zhang et al., \u0026quot;Full bottom dielectric isolation to enable stacked nanosheet transistor for low power and high performance applications,\u0026quot; \u003cem\u003eInternational Electron Devices Meeting (IEDM) Technical Digest\u003c/em\u003e, pp. 635-638, 2019.\u003c/li\u003e\n \u003cli\u003eM. Guillorn et al., \u0026quot;Power performance benchmarking of nanosheet FETs for future technology nodes,\u0026quot; \u003cem\u003eIEEE Transactions on Electron Devices\u003c/em\u003e, vol. 67, no. 10, pp. 4053-4058, Oct. 2020.\u003c/li\u003e\n \u003cli\u003eG. Bae et al., \u0026quot;3nm GAA technology featuring multi-bridge-channel FET for low power and high performance applications,\u0026quot; \u003cem\u003eInternational Electron Devices Meeting (IEDM) Technical Digest\u003c/em\u003e, pp. 28.7.1-28.7.4, 2018.\u003c/li\u003e\n \u003cli\u003eS.-Y. Wu et al., \u0026quot;A 7nm CMOS platform technology featuring 4th generation FinFET transistors with a 0.027um\u0026sup2; high density 6-T SRAM cell for mobile SoC applications,\u0026quot; \u003cem\u003eInternational Electron Devices Meeting (IEDM) Technical Digest\u003c/em\u003e, pp. 2.6.1-2.6.4, 2016.\u003c/li\u003e\n \u003cli\u003eH. Mertens et al., \u0026quot;Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates,\u0026quot; \u003cem\u003eSymposium on VLSI Technology\u003c/em\u003e, pp. 1-2, 2016.\u003c/li\u003e\n \u003cli\u003eSamsung Foundry, \u0026quot;Samsung Unveils Plans for 3nm GAA Technology Mass Production in 2022,\u0026quot; Samsung Newsroom, 2021.\u003c/li\u003e\n \u003cli\u003eG. Bae et al., \u0026quot;3nm GAA Technology Featuring Multi-Bridge-Channel FET for Low Power and High Performance Applications,\u0026quot; in IEEE International Electron Devices Meeting (IEDM), 2018.\u003c/li\u003e\n \u003cli\u003eTSMC, \u0026quot;TSMC Symposium 2023: N2 Technology Update,\u0026quot; 2023.\u003c/li\u003e\n \u003cli\u003eIntel Corporation, \u0026quot;Intel Accelerated Event,\u0026quot; 2021.\u003c/li\u003e\n \u003cli\u003eE. Sicard, \u0026quot;Microwind \u0026amp; Dsch Version 3.5 - A Tutorial,\u0026quot; INSA, Toulouse, France, 2007.\u003c/li\u003e\n \u003cli\u003eM. Bohr, \u0026quot;A 30 Year Retrospective on Dennard\u0026apos;s MOSFET Scaling Paper,\u0026quot; IEEE Solid-State Circuits Society Newsletter, vol. 12, no. 1, pp. 11-13, 2007.\u003c/li\u003e\n \u003cli\u003eN. Loubet et al., \u0026quot;Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET,\u0026quot; \u003cem\u003eSymposium on VLSI Technology\u003c/em\u003e, pp. T230-T231, 2017.\u003c/li\u003e\n \u003cli\u003eR. Divakaruni and V. Narayanan, \u0026ldquo;Challenges of 10 nm and 7 nm CMOS for server and mobile applications,\u0026rdquo; \u003cem\u003eECS Trans.\u003c/em\u003e, vol. 72, no. 4, pp. 3\u0026ndash;14, May 2016.\u003c/li\u003e\n \u003cli\u003eRadamson HH, Zhu H, Wu Z, He X, Lin H, Liu J, Xiang J, Kong Z, Xiong W, Li J, Cui H, Gao J, Yang H, Du Y, Xu B, Li B, Zhao X, Yu J, Dong Y, Wang G. State of the Art and Future Perspectives in Advanced CMOS Technology. Nanomaterials (Basel). 2020 Aug 7;10(8):1555. doi: 10.3390/nano10081555. PMID: 32784801; PMCID: PMC7466708.\u003c/li\u003e\n \u003cli\u003eYang J, Huang Z, Wang D, Liu T, Sun X, Qian L, Pan Z, Xu S, Wang C, Wu C, et al. A Novel Scheme for Full Bottom Dielectric Isolation in Stacked Si Nanosheet Gate-All-Around Transistors. \u003cem\u003eMicromachines\u003c/em\u003e. 2023; 14(6):1107. https://doi.org/10.3390/mi14061107\u003c/li\u003e\n \u003cli\u003eP. K. Dubey, D. Marian, A. Toral-Lopez, T. Knobloch, T. Grasser, and G. Fiori, \u0026quot;Simulation of Vertically Stacked 2-D Nanosheet FETs,\u0026quot; \u003cem\u003eIEEE Trans. Electron Devices\u003c/em\u003e, vol. 72, no. 3, pp. 1200-1207, Mar. 2025.\u003c/li\u003e\n \u003cli\u003eP. Weckx \u003cem\u003eet al\u003c/em\u003e., \u0026quot;Novel forksheet device architecture as ultimate logic scaling device towards 2nm,\u0026quot; \u003cem\u003e2019 IEEE International Electron Devices Meeting (IEDM)\u003c/em\u003e, San Francisco, CA, USA, 2019, pp. 36.5.1-36.5.4, doi: 10.1109/IEDM19573.2019.8993635.\u003c/li\u003e\n \u003cli\u003eJ. Ryckaert \u003cem\u003eet al\u003c/em\u003e., \u0026quot;The Complementary FET (CFET) for CMOS scaling beyond N3,\u0026quot; \u003cem\u003e2018 IEEE Symposium on VLSI Technology\u003c/em\u003e, Honolulu, HI, USA, 2018, pp. 141-142, doi: 10.1109/VLSIT.2018.8510618.\u003c/li\u003e\n \u003cli\u003eWeckx, P., Gupta, M.K., Oniki, Y., Ragnarsson, L., Horiguchi, N., Spessot, A., Verkest, D., Ryckaert, J., Litta, E.D., Yakimets, D., Matagne, P., Schuddinck, P., Jang, D., Chehab, B., \u0026amp; Baert, R. (2019). Novel forksheet device architecture as ultimate logic scaling device towards 2nm. \u003cem\u003e2019 IEEE International Electron Devices Meeting (IEDM)\u003c/em\u003e, 36.5.1-36.5.4.\u003c/li\u003e\n \u003cli\u003eP. Schuddinck \u003cem\u003eet al.\u003c/em\u003e, \u0026quot;The Complementary FET (CFET) for CMOS Scaling Beyond N3,\u0026quot; in \u003cem\u003eSymposium on VLSI Technology\u003c/em\u003e, Honolulu, HI, USA, 2018, pp. 141-142.\u003c/li\u003e\n \u003cli\u003eRitu Raj Lamsal, Prahlad Acharya, Rijan Pokhrel et al. Integrating Machine Learning and RAG-Based Chatbot for Mandarin Orange Disease Detection in Hilly Region of Nepal, 27 February 2025, PREPRINT (Version 1) available at Research Square [https://doi.org/10.21203/rs.3.rs-6105402/v1]\u003c/li\u003e\n \u003cli\u003eLamsal, Ritu Raj. \u0026quot;A Review on Advancing Digital Transformation in Agritech: Focus on Nepal.\u0026quot; \u003cem\u003eInternational conference on Recent Trends in AI ICRTAI-2025, http://dx. doi. org/10.13140/RG\u003c/em\u003e. Vol. 2.\u003c/li\u003e\n \u003cli\u003eG. Poornima, S. G. M. A., and R. R. Lamsal, \u0026quot;Revolutionizing Healthcare: The Synergy of Computer Vision and IoT Integration,\u0026quot; in \u003cem\u003eFuture Innovations in the Convergence of AI and Internet of Things in Medicine\u003c/em\u003e, 1st ed., IGI Global, 2025, ch. 13, pp. 1-20, doi: 10.4018/979-8-3693-7703-1.ch013.\u003c/li\u003e\n \u003cli\u003eLamsal, R.R., Devkota, A. \u0026amp; Bhusal, M.S. Navigating Global Challenges: The Crucial Role of Semiconductors in Advancing Globalization. \u003cem\u003eJ. Inst. Eng. India Ser. B\u003c/em\u003e \u003cstrong\u003e104\u003c/strong\u003e, 1389\u0026ndash;1399 (2023). https://doi.org/10.1007/s40031-023-00938-4\u003c/li\u003e\n\u003c/ol\u003e"}],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":true,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":true,"hideJournal":true,"highlight":"","institution":"Madan Bhandari University Of Science and Technology","isAcceptedByJournal":false,"isAuthorSuppliedPdf":false,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":false,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"CMOS, FinFET, Nanosheet FET, Gate All Around, Low-Power Design, AIoT Hardware","lastPublishedDoi":"10.21203/rs.3.rs-7705956/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-7705956/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eThe relentless scaling of complementary metal-oxide-semiconductor (CMOS) technology, as dictated by Moore's Law, has driven the semiconductor industry through multiple transistor architecture revolutions. The planar bulk MOSFET, after decades of dominance, was succeeded by the three-dimensional FinFET at the 22/16 nm node to overcome severe short-channel effects (SCEs). However, as scaling continues to the 5 nm node and beyond, the limitations of the FinFET have become apparent. This literature review examines the journey from FinFETs to the next-generation architecture: the Gate-All-Around (GAA) Nanosheet Field-Effect Transistor (NSFET). It covers the motivations for this transition, the advantages and challenges of nanosheet technology, and the future roadmap towards forksheet and complementary FET (CFET) architectures. This paper presents a comparative analysis of power and delay characteristics between 5nm FinFET and 3nm Gate All Around (GAA) Nanosheet technologies using the educational EDA tool. A standard CMOS inverter is used as a test vehicle for this analysis. Simulation results demonstrate a significant improvement in the power-delay product (PDP) for the 3nm Nanosheet technology, improvement in propagation delay compared to the 5nm FinFET, primarily due to superior electrostatic control enabling lower supply voltage operation. The findings underscore the critical importance of the transition to GAA architectures for next-generation applications in Artificial Intelligence (AI), Machine Learning (ML), and the Internet of Things (IoT), where computational efficiency and ultra-low power consumption are paramount.\u003c/p\u003e","manuscriptTitle":"The FinFET to Nanosheet Transition: A Critical Enabler for Energy-Efficient AIoT Applications","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2025-09-26 08:04:10","doi":"10.21203/rs.3.rs-7705956/v1","editorialEvents":[{"type":"communityComments","content":0}],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true}}],"origin":"","ownerIdentity":"34b2c033-3a56-47f8-9a0a-824e6e33bedc","owner":[],"postedDate":"September 26th, 2025","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"posted","subjectAreas":[{"id":55286341,"name":"Electronic Materials and Devices"}],"tags":[],"updatedAt":"2025-09-26T08:04:10+00:00","versionOfRecord":[],"versionCreatedAt":"2025-09-26 08:04:10","video":"","vorDoi":"","vorDoiUrl":"","workflowStages":[]},"version":"v1","identity":"rs-7705956","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-7705956","identity":"rs-7705956","version":["v1"]},"buildId":"8U1c8b4HqxoKbykW_rLl7","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}