High-resolution Environmental Monitoring Adc’s Empowered by 18nm Finfet Technology

High-resolution Environmental Monitoring Adc’s Empowered by 18nm Finfet Technology | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article High-resolution Environmental Monitoring Adc’s Empowered by 18nm Finfet Technology D Malathi, S Malavika This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-3833791/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract Analog-to-digital converters (ADCs) are essential components in contemporary electronic systems for translating continuous analog signals into digital formats. Emphasizing low power consumption and high conversion efficiency, the project addresses the escalating demand for high-resolution electronic devices. The primary objective is to achieve optimal resolution, crucial for environmental monitoring which demands precision. ADC architecture Ramp ADC is the focal point of the design, implemented within an 18nm FinFET technology framework. The Ramp ADC, with its comparator array and ramp generator, offers simplicity and potential for high-speed applications. The primary objective of this project is to employ a range of design techniques and modifications aimed at reducing power consumption in ADC architecture, all while minimizing the impact on crucial performance metrics, including resolution, speed, and complexity. The comparative analysis focuses on the average power of the ADC, each possessing a resolution of 13 bits. Specifically, modifications applied to the Ramp ADC yield an impressive 47% reduction in average dynamic power, coupled with a notable 28% reduction in static power compared with the existing. Analog to Digital converter FinFET Technology Ramp ADC power consumption Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 INTRODUCTION In the ever-evolving realm of electronics, Analog-to-Digital Converters (ADCs), stand as crucial components that facilitate the seamless integration of the analog and digital domains. They play a fundamental role in translating real-world analog signals into digital format, which is the lifeblood of modern digital technology. In a world where computers, microcontrollers, and digital devices reign supreme, ADCs serve as the essential bridge connecting the continuous analog realm, which encompasses phenomena like sound, temperature, and voltage, with the discrete, binary-based digital world. ADCs enable the conversion of continuous analog data into discrete digital representations. This is a fundamental process because most electronic systems, including computers and digital devices, primarily operate with digital data, represented as binary values (0s and 1s). ADCs bridge this gap by sampling analog signals and quantizing them into digital values, making it possible for these systems to understand, process, store, and manipulate real-world information. The TS-SS ADC employs a differential topology in the ramp generator for efficient coarse and fine conversion. During coarse conversion, half-ramping of the full analog-to-digital reference resolves the most significant bit (MSB), while differential slope ramping signals from the ramp generator handle the remaining least significant bits (LSBs) during fine conversion [1]. The differential continuous-time ramp generator described incorporates error correction capability, potentially introducing complexity and increasing fabrication costs due to its intricate circuitry. The implementation of error correction circuits with negative feedback adds further complexity, making the circuit design challenging to troubleshoot and maintain while potentially raising manufacturing costs [2]. The on-chip ramp generator employs a fully-differential switched-capacitor integrator and operates within a servo-loop configuration, necessitating feedback control for performance optimization. Achieving a minimal ramp step size relative to the least significant bit may require careful tuning, introducing potential trade-offs like increased complexity and sensitivity to noise. Additionally, the on-chip ramp generator's efficiency and Built-In Self-Test (BIST) technique may be susceptible to variations in semiconductor manufacturing processes [3]. The ramp generator employs endpoint error correction to minimize errors at the start and end of the ramp signal, crucial for stable and accurate analog-to-digital conversion. However, the incorporation of advanced error correction techniques and optimizations in the designed ramp generator using standard 180 nm CMOS technology may lead to a more complex circuit design, potentially resulting in increased power consumption and higher implementation costs [4]. Section I provides a detailed description of the technology being used, offering a comprehensive overview. In Section II, the existing ramp generator's operation is explained, providing insight into its functioning. Section III delves into the circuit design of the proposed ramp ADC, comparing it with existing solutions. Finally, Section IV presents simulation results, providing empirical evidence and analysis to support and evaluate the proposed design. I. FINFET TECHNOLOGY The technology used for the construction of a ramp-type ADC is 18nm FinFET Technology. A. 18NM FINFET TECHNOLOGY Figure 1 shows the 18nm FinFET technology which marks a significant milestone in semiconductor manufacturing, where the nominal feature size of 18 nanometres allows for highly advanced and compact integrated circuits [5]. FinFET, short for Fin Field- Effect Transistor, is a revolutionary transistor design that departs from traditional planar architectures. The distinguishing feature is the three-dimensional fin structure that rises vertically from the silicon substrate. B. FINFET TYPES The standard FinFET transistor is characterized by its three-dimensional fin structure rising vertically from the semiconductor substrate. The gate electrode surrounds the fin, forming a gate-all-around (GAA) configuration. Bulk FinFET In the bulk FinFET, the fin structure is built directly on the silicon substrate. It represents the fundamental FinFET design with the vertical fin providing the conducting channel. Fully Depleted SOI (Silicon-on-Insulator) FinFET The fully depleted SOI FinFET introduces an insulating layer beneath the fin, preventing charge carriers from interacting with the substrate. This enhances electrostatic control and reduces leakage currents. Double-Gate FinFET The double-gate FinFET features gates on opposite sides of the fin. This dual-gate configuration provides enhanced control over the channel, improving overall transistor characteristics. Tri-Gate FinFET The tri-gate FinFET takes the double-gate concept further by surrounding the fin with gates on three sides. This 3D design provides superior electrostatic control and performance. Nano-Sheet (or Multi-Bridge Channel) FinFET The nano-sheet FinFET introduces a horizontal layer (nano-sheet) on top of the fin. This additional layer contributes to better control over the channel. Gate-All-Around (GAA) FinFET In the GAA FinFET, the gate surrounds the fin, providing ultimate control over the channel. This configuration maximizes electrostatic control. C. OPERATION OF 18NM FINFET TECHNOLOGY The operation of an 18nm FinFET is grounded in its three-dimensional structure. As an improvement over planar transistors, the vertical fin structure allows for enhanced electrostatic control. The gate electrode, surrounding the fin, forms a gate-all-around configuration, providing precise modulation of the channel. During operation, a voltage applied to the gate controls the flow of current between the source and drain terminals through the fin. The three-dimensional nature minimizes short-channel effects and leakage currents, resulting in improved transistor performance and power efficiency. The operation of an 18nm FinFET is intricately tied to the efficient control of the three-dimensional fin structure and the gate-all-around design. II. RAMP GENERATOR The ramp generator is a crucial component in a Ramp-type ADC shown in Fig. 2 and is responsible for producing a linearly increasing or decreasing voltage ramp. This ramp serves as a reference signal for the conversion process. The generation of the ramp typically involves charging or discharging a capacitor at a constant rate. This process is often controlled by a current source or a voltage source connected to the capacitor. The key is to ensure that the voltage across the capacitor changes linearly over time, creating a predictable and well-controlled ramp signal. The linearity and stability of the ramp generator are critical for the accuracy of the Ramp ADC, as any deviation from linearity could introduce errors in the conversion process. The ramp generator has a transistor count of about 14 transistors [6]. III. RAMP ADC The ramp-type ADC operates by generating a linear ramp waveform, which is a continuously increasing voltage. A. Comparator In a ramp-type ADC, the comparator plays a pivotal role in the conversion process [9]. The ADC generates a linearly increasing (or decreasing) ramp voltage and continuously compares it with the input analog voltage. The comparator detects the point at which the ramp voltage matches the amplitude of the input signal, signifying a crossing point. The time it takes for this crossing to occur is directly proportional to the magnitude of the input voltage. Once the comparison is made, the time measurement is converted into a digital code, forming the output of the ADC. B. Ramp Generator A ramp generator is a circuit that produces a voltage signal with linearly changing amplitude over time, typically in a continuous and controlled manner. This generated ramp signal is employed in various applications, including its crucial role in the operation of ramp-type ADCs [7]. In a ramp-type ADC, the ramp generator shown in Fig. 3is employed to create a reference voltage that linearly increases during each conversion cycle. The transistor count of the ramp generator is 7 which is reduced from the existing ramp generator. The generated ramp signal is then continuously compared with the input analog voltage using a comparator. The comparison process involves monitoring the point at which the ramp voltage matches the amplitude of the input signal. The time it takes for this match to occur is measured, providing a time-based representation of the input voltage. The output of the comparator, along with additional control logic, is used to convert this time measurement into a digital code, ultimately representing the magnitude of the input analog signal. Figure 4 illustrates the output of the Ramp generator where it is employed to create a reference voltage that linearly increases or decreases during each conversion cycle. The count of the transistor in the proposed ramp generator is 7. C. Clock Generator The start signal acts as a command to commence the clock generator's predefined function, ensuring controlled and synchronized operation. Whether it's a waveform generator, clock generator, or any other device producing output, the initiation process allows for flexibility and precision, permitting users or systems to trigger the generator's output precisely when needed. This mechanism enables the repetitive and controlled generation of signals. D. Counter In a ramp-type ADC, a counter is often employed as a crucial component. The 13-bit counter is used to measure the time it takes for a generated ramp signal to reach a level that equals the amplitude of the input analog signal [8]. At the beginning of each conversion cycle, the counter is reset, and the ramp signal starts increasing in voltage. The counter then increments with each clock pulse, and its value is continuously compared with the amplitude of the ramp signal using a comparator. When the counter's value matches the ramp signal's amplitude, the comparator signals that the conversion is complete. The counter is designed as shown in Fig. 5. The counter has a 13-bit resolution. As the ramp signal increases, the 13-bit counter increments or decrements with each clock pulse. The count value in the counter at the end of the conversion cycle is proportional to the magnitude of the input analog signal. Figure 6 gives the schematic of the 13-bit Counter. E. RAMP ADC The resolution of a Ramp ADC depends on the reference voltage's change rate (ramp rate), the duration of the ramp, and the counter's bit width. The speed of conversion depends on the ramp rate and the maximum range of the input signal A Ramp ADC, shown in Fig. 8, is a type of ADC that employs a linear ramp signal for the conversion process. The fundamental principle behind a Ramp ADC is to compare an input analog signal against a linearly increasing (or decreasing) ramp voltage. The conversion is achieved by determining the moment when the ramp voltage matches the amplitude of the input signal. This comparison yields a digital code that represents the input voltage. In the operation of a ramp-type ADC, the process begins with the analog input voltage and the linearly increasing (or decreasing) ramp signal generated by the ramp generator being fed into the comparator. As long as these two inputs to the comparator differ in magnitude, the clock pulse generator is permitted to transmit pulses at a constant repetition rate through the AND gate into the counter. Fig 8 Ramp type ADC The clock pulses serve as a reference for timing, allowing for the controlled incrementation of the counter. The comparator continuously compares the amplitudes of the analog input and the ramp signal, enabling a continuous flow of clock pulses as long as a discrepancy exists. When the rising sawtooth waveform of the ramp signal eventually reaches a magnitude equal to that of the analog input, the comparator generates a stop signal. This stop signal promptly disables the gate circuit, halting the flow of clock pulses to the counter and concluding the comparison time interval. The number of accumulated pulses in the counter during this interval becomes proportional to the amplitude of the analog input voltage, and the counter's indication at this point represents the desired digital representation of the input signal. Figure 7 gives the exact implementation of ramp ADC. IV. SIMULATION RESULT Figure 9 illustrates the output of the Ramp generator where it is employed to create a reference voltage that linearly increases or decreases during each conversion cycle. The count of the transistor in the proposed ramp generator is 7. The number of accumulated pulses in the counter during this interval becomes proportional to the amplitude of the analog input voltage, and the counter's indication at this point represents the desired digital representation of the input signal. Figure 7gives the exact implementation of ramp ADC. In the operation of a ramp-type ADC, the comparator continuously compares the amplitudes of the analog input and the linearly rising sawtooth waveform generated by the ramp generator. As long as the analog input and the ramp generator outputs differ in magnitude, the clock pulse generator is authorized to transmit pulses at a consistent repetition rate through the gate, allowing the counter to accumulate pulses. The comparison time interval persists until the inputs become equal, signifying that the rising sawtooth has reached the amplitude of the analog signal. At this point, the comparator generates a stop signal, deactivating the gate circuit and concluding the comparison interval. The disabled gate circuit interrupts the flow of pulses from the clock pulse generator to the counter. The count accumulated in the counter during this interval, directly influenced by the analog input's amplitude, serves as the desired digital representation of the input signal, embodying the fundamental principle of successive approximation in the ADC. Figure 10 and Fig. 11give the output of ramp ADC for two different input voltages ad 1.8V and 1V respectively. Table 2 Output Analysis INPUT OUTPUT 1V 1100100110101 1.8V 0011110111011 Table 2 gives the output of the Ramp ADC with the two different inputs 1V and 1.8V. PARAMETER ANALYSIS Table 5 Dynamic Power Analysis of Ramp Generators SUPPLY VOLTAGE (V) EXISTING RAMP GENERATOR (mW) PROPOSED RAMP GENERATOR (mW) 2 397.8 209.2 1.8 333.0 161.3 1.5 238.1 99.2 1 92.1 80.4 0.5 40.5 26.1 AVERAGE 220.3 115.2 Table 5 shows the static power calculation of ramp generators. From the table above proposed ramp generator has a 47% reduction in dynamic power consumption when compared to the existing ramp generator. Table 6 Static Power Analysis of Ramp Generators SUPPLY VOLTAGE (V) EXISTING RAMP GENERATOR (uW) PROPOSED RAMP GENERATOR (uW) 2 3.5 2.5 1.8 2.7 2 1.5 1.7 1.5 1 1.5 1 0.5 1.4 0.7 AVERAGE 2.16 1.54 Table 6 shows the static power calculation of ramp generators. From the table above proposed ramp generator has a 28% reduction in static power consumption when compared to the existing ramp generator. Table 7 Static and Dynamic Power Analysis of Ramp ADC SUPPLY VOLTAGE (V) EXISTING (uW) PROPOSED RAMP ADC (uW) 2 897.0 9.3 1.8 596.1 7.7 1.5 400.2 6.5 1 200.1 5.1 0.5 72.64 3.7 AVERAGE 433.2 6.4 CONCLUSION ADCs serve as indispensable components facilitating the transformation of analog signals from the real world into digital representations, enabling their processing by computers and other digital devices. With ongoing technological advancements, ADCs are evolving to become faster, more precise, and more cost-effective. The choice of the most suitable ADC for an environmental monitoring application hinges on various factors such as the requisite sampling rate, resolution, accuracy, power consumption, and cost considerations. The design of the Ramp ADC, innovation is introduced by significantly reducing the transistor count of the proposed ramp generator. This modification results in a streamlined and more efficient ramp generator, effectively cutting its transistor count by half compared to the existing configuration. The comparative analysis of the ADC with 13-bit resolution reveals significant achievements in power reduction. Specifically, modifications applied to the Ramp ADC yield an impressive 47% reduction in average dynamic power, coupled with a notable 28% reduction in static power compared with the existing ramp generator. Declarations Ethical Approval -Not Applicable Funding - Not Applicable Availability of data and materials -Not Applicable References Park, S. Y., & Kim, H. J. (2021). CMOS image sensor with two-step single-slope ADC using differential ramp generator. IEEE Transactions on Electron Devices , 68 (10), 4966-4971. Asish, L., Prasobh, S. R., Krishnan, A., & Bhuvan, B. (2019, October). High speed error correction in continuous-time ramp generators using loop gain optimization. In TENCON 2019-2019 IEEE Region 10 Conference (TENCON) (pp. 2538-2543). IEEE. Renaud, G., Barragan, M. J., Laraba, A., Stratigopoulos, H. G., Mir, S., Le-Gall, H., & Naudet, H. (2016). A 65nm CMOS ramp generator design and its application towards a BIST implementation of the reduced-code static linearity test technique for pipeline ADCs. Journal of Electronic Testing , 32 , 407-421. Sankar, R. P., Asish, L., & Bhuvan, B. (2019, November). Design of Stable Error-Correction Ramp Generators Considering Process and Run-Time Variations. In 2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) (pp. 257-260). IEEE. Vallabhuni, R. R., Sravya, D. V. L., Shalini, M. S., & Maheshwararao, G. U. (2020, July). Design of Comparator using 18nm FinFET Technology for Analog to Digital Converters. In 2020 7th International Conference on Smart Structures and Systems (ICSSS) (pp. 1-6). IEEE. Spasova, M., Brusev, T., Angelov, G., Radonov, R., & Hristov, M. (2019, September). Low Power Ramp Generator with MOSFET and CNTFET Transistors. In 2019 IEEE XXVIII International Scientific Conference Electronics (ET) (pp. 1-3). IEEE. Winkeler, B., & Freire, R. (2012). Ramp Generator for ADC Built-In-Self Test. Hiremath, Y., Kulkarni, A. L., & Baligar, J. S. (2014). Design and Implementation of Synchronous 4-Bit Up Counter Using 180 nm CMOS Process Technology. International Journal of Research in Engineering and Technology (IJRET) , 3 (5), 810-815. Hemalatha, B., & Dadoria, A. K. (2021). Design of Low-Power Dynamic Type Latch Comparator Using 18 nm FinFET Technology for SAR ADC. In Advances in Engineering Design: Select Proceedings of FLAME 2020 (pp. 603-609). Springer Singapore. Additional Declarations No competing interests reported. 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V\u003c/p\u003e","description":"","filename":"10.png","url":"https://assets-eu.researchsquare.com/files/rs-3833791/v1/48e4360bb50827c14d53fece.png"},{"id":49989716,"identity":"a51d4c1b-18b9-425f-8a70-215a23d13f11","added_by":"auto","created_at":"2024-01-22 18:20:17","extension":"png","order_by":11,"title":"Figure 11","display":"","copyAsset":false,"role":"figure","size":422106,"visible":true,"origin":"","legend":"\u003cp\u003eOutput of Ramp ADC at 1.8V\u003c/p\u003e","description":"","filename":"11.png","url":"https://assets-eu.researchsquare.com/files/rs-3833791/v1/0121b5f8d01bd7b5136e3ad7.png"},{"id":50052485,"identity":"a7cd5396-2b29-47df-b226-cd8886967caa","added_by":"auto","created_at":"2024-01-23 16:52:34","extension":"pdf","order_by":0,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":3934132,"visible":true,"origin":"","legend":"","description":"","filename":"manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-3833791/v1/e5ccbca8-6812-46eb-8d50-881ca4c8fdd7.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"\u003cp\u003eHigh-resolution Environmental Monitoring Adc’s Empowered by 18nm Finfet Technology\u003c/p\u003e","fulltext":[{"header":"INTRODUCTION","content":"\u003cp\u003eIn the ever-evolving realm of electronics, Analog-to-Digital Converters (ADCs), stand as crucial components that facilitate the seamless integration of the analog and digital domains. They play a fundamental role in translating real-world analog signals into digital format, which is the lifeblood of modern digital technology. In a world where computers, microcontrollers, and digital devices reign supreme, ADCs serve as the essential bridge connecting the continuous analog realm, which encompasses phenomena like sound, temperature, and voltage, with the discrete, binary-based digital world. ADCs enable the conversion of continuous analog data into discrete digital representations. This is a fundamental process because most electronic systems, including computers and digital devices, primarily operate with digital data, represented as binary values (0s and 1s). ADCs bridge this gap by sampling analog signals and quantizing them into digital values, making it possible for these systems to understand, process, store, and manipulate real-world information.\u003c/p\u003e \u003cp\u003eThe TS-SS ADC employs a differential topology in the ramp generator for efficient coarse and fine conversion. During coarse conversion, half-ramping of the full analog-to-digital reference resolves the most significant bit (MSB), while differential slope ramping signals from the ramp generator handle the remaining least significant bits (LSBs) during fine conversion [1]. The differential continuous-time ramp generator described incorporates error correction capability, potentially introducing complexity and increasing fabrication costs due to its intricate circuitry. The implementation of error correction circuits with negative feedback adds further complexity, making the circuit design challenging to troubleshoot and maintain while potentially raising manufacturing costs [2]. The on-chip ramp generator employs a fully-differential switched-capacitor integrator and operates within a servo-loop configuration, necessitating feedback control for performance optimization. Achieving a minimal ramp step size relative to the least significant bit may require careful tuning, introducing potential trade-offs like increased complexity and sensitivity to noise. Additionally, the on-chip ramp generator's efficiency and Built-In Self-Test (BIST) technique may be susceptible to variations in semiconductor manufacturing processes [3]. The ramp generator employs endpoint error correction to minimize errors at the start and end of the ramp signal, crucial for stable and accurate analog-to-digital conversion. However, the incorporation of advanced error correction techniques and optimizations in the designed ramp generator using standard 180 nm CMOS technology may lead to a more complex circuit design, potentially resulting in increased power consumption and higher implementation costs [4].\u003c/p\u003e \u003cp\u003eSection I provides a detailed description of the technology being used, offering a comprehensive overview. In Section II, the existing ramp generator's operation is explained, providing insight into its functioning. Section III delves into the circuit design of the proposed ramp ADC, comparing it with existing solutions. Finally, Section IV presents simulation results, providing empirical evidence and analysis to support and evaluate the proposed design.\u003c/p\u003e"},{"header":"I. FINFET TECHNOLOGY","content":"\u003cp\u003eThe technology used for the construction of a ramp-type ADC is 18nm FinFET Technology.\u003c/p\u003e\n\u003ch3\u003eA. 18NM FINFET TECHNOLOGY\u003c/h3\u003e\n\u003cp\u003eFigure \u003cspan class=\"InternalRef\"\u003e1\u003c/span\u003e shows the 18nm FinFET technology which marks a significant milestone in semiconductor manufacturing, where the nominal feature size of 18 nanometres allows for highly advanced and compact integrated circuits [5]. FinFET, short for Fin Field- Effect Transistor, is a revolutionary transistor design that departs from traditional planar architectures. The distinguishing feature is the three-dimensional fin structure that rises vertically from the silicon substrate.\u003c/p\u003e\n\u003cp\u003eB. FINFET TYPES\u003c/p\u003e\n\u003cp\u003eThe standard FinFET transistor is characterized by its three-dimensional fin structure rising vertically from the semiconductor substrate. The gate electrode surrounds the fin, forming a gate-all-around (GAA) configuration.\u003c/p\u003e\n\u003cdiv id=\"Sec5\"\u003e\n \u003ch2\u003eBulk FinFET\u003c/h2\u003e\n \u003cp\u003eIn the bulk FinFET, the fin structure is built directly on the silicon substrate. It represents the fundamental FinFET design with the vertical fin providing the conducting channel.\u003c/p\u003e\n\u003c/div\u003e\n\u003cdiv id=\"Sec6\"\u003e\n \u003ch2\u003eFully Depleted SOI (Silicon-on-Insulator) FinFET\u003c/h2\u003e\n \u003cp\u003eThe fully depleted SOI FinFET introduces an insulating layer beneath the fin, preventing charge carriers from interacting with the substrate. This enhances electrostatic control and reduces leakage currents.\u003c/p\u003e\n\u003c/div\u003e\n\u003cdiv id=\"Sec7\"\u003e\n \u003ch2\u003eDouble-Gate FinFET\u003c/h2\u003e\n \u003cp\u003eThe double-gate FinFET features gates on opposite sides of the fin. This dual-gate configuration provides enhanced control over the channel, improving overall transistor characteristics.\u003c/p\u003e\n\u003c/div\u003e\n\u003cdiv id=\"Sec8\"\u003e\n \u003ch2\u003eTri-Gate FinFET\u003c/h2\u003e\n \u003cp\u003eThe tri-gate FinFET takes the double-gate concept further by surrounding the fin with gates on three sides. This 3D design provides superior electrostatic control and performance.\u003c/p\u003e\n\u003c/div\u003e\n\u003cdiv id=\"Sec9\"\u003e\n \u003ch2\u003eNano-Sheet (or Multi-Bridge Channel) FinFET\u003c/h2\u003e\n \u003cp\u003eThe nano-sheet FinFET introduces a horizontal layer (nano-sheet) on top of the fin. This additional layer contributes to better control over the channel.\u003c/p\u003e\n\u003c/div\u003e\n\u003cdiv id=\"Sec10\"\u003e\n \u003ch2\u003eGate-All-Around (GAA) FinFET\u003c/h2\u003e\n \u003cp\u003eIn the GAA FinFET, the gate surrounds the fin, providing ultimate control over the channel. This configuration maximizes electrostatic control.\u003c/p\u003e\n\u003c/div\u003e\n\u003cdiv id=\"Sec11\"\u003e\n \u003ch2\u003eC. \u003cstrong\u003eOPERATION OF 18NM FINFET TECHNOLOGY\u003c/strong\u003e\u003c/h2\u003e\n \u003cp\u003eThe operation of an 18nm FinFET is grounded in its three-dimensional structure. As an improvement over planar transistors, the vertical fin structure allows for enhanced electrostatic control. The gate electrode, surrounding the fin, forms a gate-all-around configuration, providing precise modulation of the channel. During operation, a voltage applied to the gate controls the flow of current between the source and drain terminals through the fin. The three-dimensional nature minimizes short-channel effects and leakage currents, resulting in improved transistor performance and power efficiency. The operation of an 18nm FinFET is intricately tied to the efficient control of the three-dimensional fin structure and the gate-all-around design.\u003c/p\u003e\n\u003c/div\u003e"},{"header":"II. RAMP GENERATOR","content":"\u003cp\u003eThe ramp generator is a crucial component in a Ramp-type ADC shown in Fig. \u003cspan\u003e2\u003c/span\u003e and is responsible for producing a linearly increasing or decreasing voltage ramp. This ramp serves as a reference signal for the conversion process. The generation of the ramp typically involves charging or discharging a capacitor at a constant rate. This process is often controlled by a current source or a voltage source connected to the capacitor. The key is to ensure that the voltage across the capacitor changes linearly over time, creating a predictable and well-controlled ramp signal. The linearity and stability of the ramp generator are critical for the accuracy of the Ramp ADC, as any deviation from linearity could introduce errors in the conversion process. The ramp generator has a transistor count of about 14 transistors [6].\u003c/p\u003e"},{"header":"III. RAMP ADC","content":"\u003cp name=\"content\"\u003eThe ramp-type ADC operates by generating a linear ramp waveform, which is a continuously increasing voltage.\u003c/p\u003e\n\u003cp name=\"content\"\u003eA. Comparator\u003c/p\u003e\n\u003cp\u003eIn a ramp-type ADC, the comparator plays a pivotal role in the conversion process [9]. The ADC generates a linearly increasing (or decreasing) ramp voltage and continuously compares it with the input analog voltage. The comparator detects the point at which the ramp voltage matches the amplitude of the input signal, signifying a crossing point. The time it takes for this crossing to occur is directly proportional to the magnitude of the input voltage. Once the comparison is made, the time measurement is converted into a digital code, forming the output of the ADC.\u003c/p\u003e\n\u003cp name=\"content\"\u003eB. Ramp Generator\u003c/p\u003e\n\u003cp\u003eA ramp generator is a circuit that produces a voltage signal with linearly changing amplitude over time, typically in a continuous and controlled manner. This generated ramp signal is employed in various applications, including its crucial role in the operation of ramp-type ADCs [7].\u003c/p\u003e\n\u003cp\u003eIn a ramp-type ADC, the ramp generator shown in Fig. 3is employed to create a reference voltage that linearly increases during each conversion cycle. The transistor count of the ramp generator is 7 which is reduced from the existing ramp generator. The generated ramp signal is then continuously compared with the input analog voltage using a comparator. The comparison process involves monitoring the point at which the ramp voltage matches the amplitude of the input signal. The time it takes for this match to occur is measured, providing a time-based representation of the input voltage. The output of the comparator, along with additional control logic, is used to convert this time measurement into a digital code, ultimately representing the magnitude of the input analog signal.\u003c/p\u003e\n\u003cp name=\"content\"\u003eFigure 4 illustrates the output of the Ramp generator where it is employed to create a reference voltage that linearly increases or decreases during each conversion cycle. The count of the transistor in the proposed ramp generator is 7.\u003c/p\u003e\n\u003cp\u003e\u003cspan name=\"content\"\u003eC. Clock Generator\u003cbr\u003e\u003c/span\u003eThe start signal acts as a command to commence the clock generator\u0026apos;s predefined function, ensuring controlled and synchronized operation. Whether it\u0026apos;s a waveform generator, clock generator, or any other device producing output, the initiation process allows for flexibility and precision, permitting users or systems to trigger the generator\u0026apos;s output precisely when needed. This mechanism enables the repetitive and controlled generation of signals.\u003c/p\u003e\n\u003cp\u003e\u003cbr\u003e\u003c/p\u003e\n\u003cp\u003eD. Counter\u003c/p\u003e\n\u003cp\u003eIn a ramp-type ADC, a counter is often employed as a crucial component. The 13-bit counter is used to measure the time it takes for a generated ramp signal to reach a level that equals the amplitude of the input analog signal [8]. At the beginning of each conversion cycle, the counter is reset, and the ramp signal starts increasing in voltage. The counter then increments with each clock pulse, and its value is continuously compared with the amplitude of the ramp signal using a comparator. When the counter\u0026apos;s value matches the ramp signal\u0026apos;s amplitude, the comparator signals that the conversion is complete. The counter is designed as shown in Fig. 5.\u003c/p\u003e\n\u003cp\u003eThe counter has a 13-bit resolution. As the ramp signal increases, the 13-bit counter increments or decrements with each clock pulse. The count value in the counter at the end of the conversion cycle is proportional to the magnitude of the input analog signal. Figure\u0026nbsp;6 gives the schematic of the 13-bit Counter.\u003c/p\u003e\n\u003ch2\u003eE. RAMP ADC\u003c/h2\u003e\n\u003cp\u003eThe resolution of a Ramp ADC depends on the reference voltage\u0026apos;s change rate (ramp rate), the duration of the ramp, and the counter\u0026apos;s bit width. The speed of conversion depends on the ramp rate and the maximum range of the input signal\u003c/p\u003e\n\u003cp\u003eA Ramp ADC, shown in Fig. 8, is a type of ADC that employs a linear ramp signal for the conversion process. The fundamental principle behind a Ramp ADC is to compare an input analog signal against a linearly increasing (or decreasing) ramp voltage. The conversion is achieved by determining the moment when the ramp voltage matches the amplitude of the input signal. This comparison yields a digital code that represents the input voltage.\u003c/p\u003e\n\u003cp\u003eIn the operation of a ramp-type ADC, the process begins with the analog input voltage and the linearly increasing (or decreasing) ramp signal generated by the ramp generator being fed into the comparator. As long as these two inputs to the comparator differ in magnitude, the clock pulse generator is permitted to transmit pulses at a constant repetition rate through the AND gate into the counter.\u003c/p\u003e\n\u003cp\u003eFig 8 Ramp type ADC\u003c/p\u003e\n\u003cp\u003eThe clock pulses serve as a reference for timing, allowing for the controlled incrementation of the counter. The comparator continuously compares the amplitudes of the analog input and the ramp signal, enabling a continuous flow of clock pulses as long as a discrepancy exists. When the rising sawtooth waveform of the ramp signal eventually reaches a magnitude equal to that of the analog input, the comparator generates a stop signal. This stop signal promptly disables the gate circuit, halting the flow of clock pulses to the counter and concluding the comparison time interval.\u003c/p\u003e\n\u003cp\u003eThe number of accumulated pulses in the counter during this interval becomes proportional to the amplitude of the analog input voltage, and the counter\u0026apos;s indication at this point represents the desired digital representation of the input signal. Figure 7 gives the exact implementation of ramp ADC.\u003c/p\u003e"},{"header":"IV. SIMULATION RESULT","content":"\u003cp\u003eFigure 9 illustrates the output of the Ramp generator where it is employed to create a reference voltage that linearly increases or decreases during each conversion cycle. The count of the transistor in the proposed ramp generator is 7.\u003c/p\u003e\n\u003cp\u003eThe number of accumulated pulses in the counter during this interval becomes proportional to the amplitude of the analog input voltage, and the counter\u0026apos;s indication at this point represents the desired digital representation of the input signal. Figure 7gives the exact implementation of ramp ADC.\u003c/p\u003e\n\u003cp\u003eIn the operation of a ramp-type ADC, the comparator continuously compares the amplitudes of the analog input and the linearly rising sawtooth waveform generated by the ramp generator. As long as the analog input and the ramp generator outputs differ in magnitude, the clock pulse generator is authorized to transmit pulses at a consistent repetition rate through the gate, allowing the counter to accumulate pulses. The comparison time interval persists until the inputs become equal, signifying that the rising sawtooth has reached the amplitude of the analog signal.\u003c/p\u003e\n\u003cp\u003eAt this point, the comparator generates a stop signal, deactivating the gate circuit and concluding the comparison interval. The disabled gate circuit interrupts the flow of pulses from the clock pulse generator to the counter. The count accumulated in the counter during this interval, directly influenced by the analog input\u0026apos;s amplitude, serves as the desired digital representation of the input signal, embodying the fundamental principle of successive approximation in the ADC. Figure 10 and Fig. 11give the output of ramp ADC for two different input voltages ad 1.8V and 1V respectively.\u003c/p\u003e\n\u003cdiv\u003e\u0026nbsp;\u003ctable border=\"1\"\u003e\n \u003ccaption language=\"En\"\u003e\n \u003cdiv\u003eTable 2\u003c/div\u003e\n \u003cdiv\u003e\n \u003cp\u003eOutput Analysis\u003c/p\u003e\n \u003c/div\u003e\n \u003c/caption\u003e\n \u003cthead\u003e\n \u003ctr\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eINPUT\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eOUTPUT\u003c/p\u003e\n \u003c/th\u003e\n \u003c/tr\u003e\n \u003c/thead\u003e\n \u003ctbody\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1V\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e1100100110101\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1.8V\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e0011110111011\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003c/tbody\u003e\n \u003c/table\u003e\n\u003c/div\u003e\n\u003cp\u003eTable 2 gives the output of the Ramp ADC with the two different inputs 1V and 1.8V.\u003c/p\u003e"},{"header":"PARAMETER ANALYSIS","content":"\u003cdiv\u003e\u0026nbsp;\u003ctable border=\"1\"\u003e\n \u003ccaption language=\"En\"\u003e\n \u003cdiv\u003eTable 5\u003c/div\u003e\n \u003cdiv\u003e\n \u003cp\u003eDynamic Power Analysis of Ramp Generators\u003c/p\u003e\n \u003c/div\u003e\n \u003c/caption\u003e\n \u003cthead\u003e\n \u003ctr\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eSUPPLY VOLTAGE\u003c/p\u003e\n \u003cp\u003e(V)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eEXISTING RAMP GENERATOR (mW)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003ePROPOSED RAMP GENERATOR (mW)\u003c/p\u003e\n \u003c/th\u003e\n \u003c/tr\u003e\n \u003c/thead\u003e\n \u003ctbody\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e2\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e397.8\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e209.2\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1.8\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e333.0\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e161.3\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1.5\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e238.1\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e99.2\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e92.1\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e80.4\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0.5\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e40.5\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e26.1\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eAVERAGE\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e220.3\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e115.2\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003c/tbody\u003e\n \u003c/table\u003e\n\u003c/div\u003e\n\u003cp\u003eTable 5 shows the static power calculation of ramp generators. From the table above proposed ramp generator has a 47% reduction in dynamic power consumption when compared to the existing ramp generator.\u003c/p\u003e\n\u003cdiv\u003e\u0026nbsp;\u003ctable border=\"1\"\u003e\n \u003ccaption language=\"En\"\u003e\n \u003cdiv\u003eTable 6\u003c/div\u003e\n \u003cdiv\u003e\n \u003cp\u003eStatic Power Analysis of Ramp Generators\u003c/p\u003e\n \u003c/div\u003e\n \u003c/caption\u003e\n \u003cthead\u003e\n \u003ctr\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eSUPPLY VOLTAGE (V)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eEXISTING RAMP GENERATOR (uW)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003ePROPOSED RAMP GENERATOR (uW)\u003c/p\u003e\n \u003c/th\u003e\n \u003c/tr\u003e\n \u003c/thead\u003e\n \u003ctbody\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e2\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e3.5\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e2.5\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1.8\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e2.7\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e2\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1.5\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e1.7\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1.5\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e1.5\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0.5\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e1.4\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0.7\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eAVERAGE\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e2.16\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1.54\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003c/tbody\u003e\n \u003c/table\u003e\n\u003c/div\u003e\n\u003cp\u003eTable 6 shows the static power calculation of ramp generators. From the table above proposed ramp generator has a 28% reduction in static power consumption when compared to the existing ramp generator.\u003c/p\u003e\n\u003cdiv\u003e\u0026nbsp;\u003ctable border=\"1\"\u003e\n \u003ccaption language=\"En\"\u003e\n \u003cdiv\u003eTable 7\u003c/div\u003e\n \u003cdiv\u003e\n \u003cp\u003eStatic and Dynamic Power Analysis of Ramp ADC\u003c/p\u003e\n \u003c/div\u003e\n \u003c/caption\u003e\n \u003cthead\u003e\n \u003ctr\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eSUPPLY VOLTAGE (V)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eEXISTING\u003c/p\u003e\n \u003cp\u003e(uW)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003ePROPOSED RAMP ADC\u003c/p\u003e\n \u003cp\u003e(uW)\u003c/p\u003e\n \u003c/th\u003e\n \u003c/tr\u003e\n \u003c/thead\u003e\n \u003ctbody\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e2\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e897.0\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e9.3\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1.8\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e596.1\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e7.7\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1.5\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e400.2\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e6.5\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e200.1\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e5.1\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0.5\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e72.64\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e3.7\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eAVERAGE\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e433.2\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e6.4\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003c/tbody\u003e\n \u003c/table\u003e\n\u003c/div\u003e"},{"header":"CONCLUSION","content":"\u003cp\u003eADCs serve as indispensable components facilitating the transformation of analog signals from the real world into digital representations, enabling their processing by computers and other digital devices. With ongoing technological advancements, ADCs are evolving to become faster, more precise, and more cost-effective. The choice of the most suitable ADC for an environmental monitoring application hinges on various factors such as the requisite sampling rate, resolution, accuracy, power consumption, and cost considerations. The design of the Ramp ADC, innovation is introduced by significantly reducing the transistor count of the proposed ramp generator. This modification results in a streamlined and more efficient ramp generator, effectively cutting its transistor count by half compared to the existing configuration. The comparative analysis of the ADC with 13-bit resolution reveals significant achievements in power reduction. Specifically, modifications applied to the Ramp ADC yield an impressive 47% reduction in average dynamic power, coupled with a notable 28% reduction in static power compared with the existing ramp generator.\u003c/p\u003e"},{"header":"Declarations","content":"\u003cp\u003e\u003cstrong\u003eEthical Approval\u003c/strong\u003e\u0026nbsp; -Not Applicable\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003e\u0026nbsp;\u003c/strong\u003e\u003cstrong\u003eFunding \u0026nbsp;- Not Applicable\u0026nbsp;\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003e\u0026nbsp;\u003cstrong\u003eAvailability of data and materials\u003c/strong\u003e\u0026nbsp; -Not Applicable\u003c/p\u003e\n\u003cp\u003e\u0026nbsp;\u003c/p\u003e"},{"header":"References","content":"\u003col\u003e\n\u003cli\u003ePark, S. Y., \u0026amp; Kim, H. J. (2021). CMOS image sensor with two-step single-slope ADC using differential ramp generator. \u003cem\u003eIEEE Transactions on Electron Devices\u003c/em\u003e, \u003cem\u003e68\u003c/em\u003e(10), 4966-4971. \u003c/li\u003e\n\u003cli\u003eAsish, L., Prasobh, S. R., Krishnan, A., \u0026amp; Bhuvan, B. (2019, October). High speed error correction in continuous-time ramp generators using loop gain optimization. In \u003cem\u003eTENCON 2019-2019 IEEE Region 10 Conference (TENCON)\u003c/em\u003e (pp. 2538-2543). IEEE.\u003c/li\u003e\n\u003cli\u003eRenaud, G., Barragan, M. J., Laraba, A., Stratigopoulos, H. G., Mir, S., Le-Gall, H., \u0026amp; Naudet, H. (2016). A 65nm CMOS ramp generator design and its application towards a BIST implementation of the reduced-code static linearity test technique for pipeline ADCs. \u003cem\u003eJournal of Electronic Testing\u003c/em\u003e, \u003cem\u003e32\u003c/em\u003e, 407-421.\u003c/li\u003e\n\u003cli\u003eSankar, R. P., Asish, L., \u0026amp; Bhuvan, B. (2019, November). Design of Stable Error-Correction Ramp Generators Considering Process and Run-Time Variations. In \u003cem\u003e2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)\u003c/em\u003e (pp. 257-260). IEEE.\u003c/li\u003e\n\u003cli\u003eVallabhuni, R. R., Sravya, D. V. L., Shalini, M. S., \u0026amp; Maheshwararao, G. U. (2020, July). Design of Comparator using 18nm FinFET Technology for Analog to Digital Converters. In \u003cem\u003e2020 7th International Conference on Smart Structures and Systems (ICSSS)\u003c/em\u003e (pp. 1-6). IEEE.\u003c/li\u003e\n\u003cli\u003eSpasova, M., Brusev, T., Angelov, G., Radonov, R., \u0026amp; Hristov, M. (2019, September). Low Power Ramp Generator with MOSFET and CNTFET Transistors. In \u003cem\u003e2019 IEEE XXVIII International Scientific Conference Electronics (ET)\u003c/em\u003e (pp. 1-3). IEEE.\u003c/li\u003e\n\u003cli\u003eWinkeler, B., \u0026amp; Freire, R. (2012). Ramp Generator for ADC Built-In-Self Test.\u003c/li\u003e\n\u003cli\u003eHiremath, Y., Kulkarni, A. L., \u0026amp; Baligar, J. S. (2014). Design and Implementation of Synchronous 4-Bit Up Counter Using 180 nm CMOS Process Technology. \u003cem\u003eInternational Journal of Research in Engineering and Technology (IJRET)\u003c/em\u003e, \u003cem\u003e3\u003c/em\u003e(5), 810-815.\u003c/li\u003e\n\u003cli\u003eHemalatha, B., \u0026amp; Dadoria, A. K. (2021). Design of Low-Power Dynamic Type Latch Comparator Using 18 nm FinFET Technology for SAR ADC. In \u003cem\u003eAdvances in Engineering Design: Select Proceedings of FLAME 2020\u003c/em\u003e (pp. 603-609). Springer Singapore.\u003c/li\u003e\n\u003c/ol\u003e"}],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":true,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":true,"highlight":"","institution":"","isAcceptedByJournal":false,"isAuthorSuppliedPdf":false,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":false,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"Analog to Digital converter, FinFET Technology, Ramp ADC, power consumption","lastPublishedDoi":"10.21203/rs.3.rs-3833791/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-3833791/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eAnalog-to-digital converters (ADCs) are essential components in contemporary electronic systems for translating continuous analog signals into digital formats. Emphasizing low power consumption and high conversion efficiency, the project addresses the escalating demand for high-resolution electronic devices. The primary objective is to achieve optimal resolution, crucial for environmental monitoring which demands precision. ADC architecture Ramp ADC is the focal point of the design, implemented within an 18nm FinFET technology framework. The Ramp ADC, with its comparator array and ramp generator, offers simplicity and potential for high-speed applications. The primary objective of this project is to employ a range of design techniques and modifications aimed at reducing power consumption in ADC architecture, all while minimizing the impact on crucial performance metrics, including resolution, speed, and complexity. The comparative analysis focuses on the average power of the ADC, each possessing a resolution of 13 bits. Specifically, modifications applied to the Ramp ADC yield an impressive 47% reduction in average dynamic power, coupled with a notable 28% reduction in static power compared with the existing.\u003c/p\u003e","manuscriptTitle":"High-resolution Environmental Monitoring Adc’s Empowered by 18nm Finfet Technology","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2024-01-22 18:12:12","doi":"10.21203/rs.3.rs-3833791/v1","editorialEvents":[{"type":"communityComments","content":0}],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true}}],"origin":"","ownerIdentity":"d3573432-a166-43a7-a5c6-19ec19fcf980","owner":[],"postedDate":"January 22nd, 2024","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"posted","subjectAreas":[],"tags":[],"updatedAt":"2024-01-23T16:44:25+00:00","versionOfRecord":[],"versionCreatedAt":"2024-01-22 18:12:12","video":"","vorDoi":"","vorDoiUrl":"","workflowStages":[]},"version":"v1","identity":"rs-3833791","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-3833791","identity":"rs-3833791","version":["v1"]},"buildId":"qtupq5eGEP_6zYnWcrvyt","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}