Interface trap states induced underestimation of Schottky barrier height in Metal-MX2 Junctions

Interface trap states induced underestimation of Schottky barrier height in Metal-MX2 Junctions | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Article Interface trap states induced underestimation of Schottky barrier height in Metal-MX 2 Junctions Himani Jawa, Devin Verreck, Zheng Sun, Surajit Sutar, Cesar Javier Lockhart Rosa, and 2 more This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-5897670/v1 This work is licensed under a CC BY 4.0 License Status: Published Journal Publication published 01 Jul, 2025 Read the published version in npj 2D Materials and Applications → Version 1 posted 10 You are reading this latest preprint version Abstract Understanding the interfaces between a contact metal and a two-dimensional (2D) semiconductor as well as the dielectric gate stack and the same 2D material in transition metal dichalcogenide (TMD) based transistors is a crucial step towards the introduction of TMD materials into advanced logic nodes. In particular, for the contact metal/2D interface, one of the key parameters is the Schottky barrier height (SBH), which is frequently extracted based on temperature-dependent subthreshold characteristics of TMD field-effect transistors (FETs). However, recently, using this methodology has resulted in rather low extracted SBH values for TMD based transistors, which seems inconsistent with the low on-current levels in said devices. Here, we therefore connect measured device characteristics on monolayer (ML) MoS 2 transistors with technology computer-aided design (TCAD) simulations. In particular, our analysis shows that low SBHs can incorrectly be extracted when the interface trap density D it is substantial and exhibits at the same time a significant temperature dependence as is the case for TMDs. In fact, TCAD simulations and comparison with the obtained electrical data reveals that the actual SBH is substantially larger than what is extracted when ignoring the above mentioned details of D it . Physical sciences/Nanoscience and technology/Nanoscale devices Physical sciences/Nanoscience and technology/Nanoscale materials Physical sciences/Physics/Electronics photonics and device physics ML MoS2 field-effect transistors interface trap density subthreshold slope Schottky barrier height TCAD Figures Figure 1 Figure 2 Figure 3 Figure 4 1. Introduction Frequently, field-effect transistors based on novel semiconducting channel materials are built without mimicking the n/p/n or p/n/p doping profile of a conventional silicon-based metal oxide semiconductor field-effect transistor (MOSFET). In fact, the most common way of building prototype FETs is to employ metal source/drain contacts in conjunction with a gating scheme that controls the entire semiconducting channel. In most instances, a Si/SiO 2 substrate with a thick dielectric layer is used as a global back gate, allowing for quick access to some basic device characteristics. For devices of this type, the contact resistance is dominated by the Schottky barrier at the source/drain-to-channel interfaces. In 2004 [ 1 ], we discussed a novel approach to extract information, in particular the Schottky barrier height (SBH), using carbon nanotubes as an example. The idea was that the ultra-thin body of the channel material impacts, i.e. reduces the Schottky barrier thickness (SBT) in the gated channel region. This change in turn allows for substantial thermal assisted tunneling between the contacts and the channel, impacting the inverse subthreshold slope (SS) of the device in its off-state. In fact, for gate voltages in the device off-state close to threshold, SS cannot reach the thermal limit, e.g. ∼60 mV/dec at room temperature, irrespective of the chosen gate oxide thickness, since this regime is impacted by the gate voltage response of the Schottky barrier thickness (SBT). Through a careful analysis of the “effective barrier height” ϕ B , the one that can be extracted from an Arrhenius plot of device current versus inverse temperature T for different gate voltages V GS , the actual Schottky barrier height can be identified [ 1 ]. Our method has since been used frequently, including for ultra-thin body devices from transition metal dichalcogenides (TMDs). In a number of instances very small extracted Schottky barrier heights of 12.5 meV, 64 meV, and 16 meV were reported [ 2 – 4 ]. As we discussed in our original paper, there are a couple of signatures that need to be present to ensure that the extracted SBH is indeed the one that actually determines the current transport. For example, (1) SS needs to be proportional to T in the thermal regime – i.e. in the deep off-state of the device – for our analysis to be applicable. Another sanity check is (2) the expected correlation between log(I DS ) vs. V GS and ϕ B vs. V GS in the thermal regime. In fact, for fully depleted devices (C D = 0), SS in the thermal regime should be (k B T/q) ∗ ln(10) ∗ m with m = 1 + C it /C ox for constant C it and C ox and −(dϕ B /dV GS ) −1 = m. In case of reference [ 4 ] condition (1) does not apply, as apparent from Fig. 9b in [ 4 ]. Condition (2) is clearly violated in [ 2 – 4 ] as evident from Fig. 3 if compared to Fig. 4 b in reference [ 2 ], from the absence of any ϕ B -dependence in figure S3 in [ 3 ], and from Fig. 9b, if compared to Fig. 9d in reference [ 4 ], where “m” is labeled as “γ -1 ”, respectively. In the following, we will elucidate why above articles presumably vastly underestimated the actual SBH by comparing our own data with those previously published. In particular, we will identify a strong temperature dependence of C it as the culprit for why our previously proposed SBH extraction method [ 1 ] cannot be applied. To do that, we fabricated monolayer MoS 2 transistors and electrically characterized the devices at different temperatures to extract the SBH and to understand the effect of the interface traps on the transfer characteristics, especially in the subthreshold regime. Additionally, TCAD simulations are employed to model the distribution of interface traps which explain the change in subthreshold slope with temperature and underestimation of extracted SBH. 2. Results 2.1 Device fabrication and electrical characteristics Figure 1 a shows the schematic of the as-fabricated MoS 2 transistor. The local bottom gates (LBGs) were first fabricated on a Si/SiO 2 substrate by lithography and metallization, followed by the deposition of 5.5 nm ALD HfO 2 and 3.6 nm amorphous Boron Nitride (aBN), serving as the bottom gate dielectric. Next, a monolayer MoS 2 film was wet transferred onto the LBG substrate and etched by reactive ion etching with Cl 2 /O 2 at a power of 40 W for 15 seconds. Finally, Ni source/drain (S/D) contacts were patterned using e-beam lithography and e-beam evaporation. Figure 1 b and 1 c show the transfer and output characteristics of an exemplary MoS 2 transistor with a channel length of 200 nm. The device shows good off-state behavior, such as negligible drain-induced barrier lowering (DIBL) and low inverse subthreshold slope (SS ∼ 100 mV/decade, extracted between 1e-3 to 1e-4 µ A/ µ m), and a high on-state current of ∼ 180 µ A/ µ m at V DS = 1 V. To study the impact of the interface trap density on the SBH extraction, we measured the transfer characteristics of ML MoS 2 transistors at different temperatures for V D = 0.1 V as shown in Fig. 1 d. At gate biases below flatband voltage ( V GS ≤ V FB , here at current values of around 1e-3 µ A/ µ m) the thermionic current determines the current through the device, with I DS given by [ 1 ]: $$\:{I}_{DS}A{T}^{2}{e}^{\frac{-q{\varPhi\:}_{B}}{{k}_{B}T}}$$ 1 where A is the Richardson’s constant, ϕ B is the effective barrier height, k B is the Boltzmann constant, q is the electronic charge, and T is the temperature. In order to extract the actual SBH ( ϕ SB ), the temperature dependent current values (shown in Fig. 1 d) are used to generate an Arrhenius plot (log( I DS /T 2 ) vs. 1000/T), and the slope of the Arrhenius plot results in a ϕ B vs. V GS plot, as shown in 1e. Note that using this technique over the entire gate voltage range means that ϕ B is only capturing the “actual” barrier height for V GS ≤ V FB which allows to identify the Schottky barrier height ϕ SB , given that for gate biases lower than V FB the effective barrier height ϕ B varies linearly with V GS in the thermionic transport regime. This leads to the extraction of a Schottky barrier height, SBH ∼ 90 ± 10 meV. It is important to note that (1) this value of SBH extracted from the transfer characteristics is significantly lower than the SBH obtained from TCAD simulations by fitting our experimental data, which will be discussed later in this paper and (2) the calculations have not been corrected for threshold voltage shifts in transfer characteristics at different temperatures, which is a common practice found in the literature [ 4 , 5 ]. Hence, to understand the effect of threshold voltage (V T ) correction on the SBH extraction and the underlying reason behind the V T shift, the transfer characteristics are adjusted, as shown in Fig. 2 a. Using these corrected current values, the Arrhenius plot (log( I DS /T 2 ) vs. 1000/T) is again generated. This time the slopes (-q ϕ B /k B ) are positive as shown in Fig. 2 b, resulting in a negative SBH extraction, which is also not consistent with our TCAD simulations. This erroneous SBH value extracted post V T correction is a result of the fact that in reality, the V T shifts with temperature in this device originate from a varying interface trap density profile, which we will demonstrate from our TCAD simulations in the next section. Noticing that the small extracted Schottky barrier height (without any V T correction) is a result of the very small temperature dependence of the subthreshold currents, we next extracted the inverse subthreshold slope (SS) in the deep off state for currents between 1e-3 to 1e-4 µ A/ µ m that correspond to the thermionic emission regime. Under these conditions SS is expected to exhibit the following temperature dependence: $$\:SS=\:\frac{{k}_{B}T}{q}(1+\frac{{C}_{D}+{C}_{it}}{{C}_{ox}})$$ 2 where C D is the depletion capacitance, C it is the capacitance due to a finite interface trap density (D it ), given by C it = q 2 ∗ D it and C ox is the gate oxide capacitance. Given the absence of any variation of depletion charge in the MoS 2 channel to the applied gate bias, C D is zero in our fully depleted devices. Assuming no dependence of D it on temperature, the subthreshold slope should linearly increase as the temperature rises, as represented by the black dots in Fig. 2 c, assuming that at 300 K the actual D it value had been extracted. However, the extracted SS-values from the subthreshold characteristics at different temperatures as shown by red dots in Fig. 2 c are almost temperature independent. To explain the apparent absence of the expected temperature dependent trend from Eq. ( 2 ), one has to conclude that C it is a function of T. The resulting D it (T) is plotted in Fig. 2 d. Interestingly, D it increases with decreasing temperature, reaching a maximum value of 3*10 13 eV -1 cm -2 at 80 K. This finding is consistent with previous results by the IMEC group [ 6 ] which show higher trap densities at lower temperatures from detailed capacitance measurements on TMDs as a function of T. The study combines the static model in the small signal regime with the distributed R-C network of the semiconductor to understand the dynamic nature of the MOS capacitor, focusing on segregating the effects of channel resistance from interface traps. The interface traps in such a way extracted for a 4 nm HfO 2 /3–5 ML MoS 2 stack show an exponentially increasing amount of defect states originating from the conduction band of MoS 2 . In short, despite using different methodologies (temperature dependent transfer characteristics in this study and C-V characteristics used in IMEC study [ 6 ]), both studies obtain an interface trap density distribution that increases approximately exponentially towards the MoS 2 conduction band edge at the MoS 2 -dielectric interface. Hence, the expected decrease of SS with decreasing T is compensated for by an increase of D it (T) for decreasing temperature. This implies that similar to references [ 3 ] and [ 4 ] our own MoS 2 data cannot be used to extract the Schottky barrier height at the source/drain metal to TMD channel interface employing the methodology proposed in reference [ 1 ]. Also, similar to references [ 2 – 4 ], when using the extraction methodology nonetheless, a vastly underestimated ϕ SB -value is extracted. One may ask the question whether the strong dependence of our D it on temperature is a unique result of the TMD-to-gate stack interface. The answer is “no”. In fact, the observed temperature dependence can be translated into a D it profile inside the TMD bandgap as a function of the energetic position relative to the band edges as discussed in the next section and that is qualitatively consistent with what has been previously reported for other semiconducting channels, e.g. III-V [ 7 , 8 ] and silicon [ 9 – 11 ]. The difference, however, lies in the magnitude of D it . While silicon technology has achieved D it -values in the 10 10 eV -1 cm -2 to 10 11 eV -1 cm -2 range, our extracted D it -values at room temperature are substantially higher. This is also the reason why the methodology in reference [ 1 ] can readily be applied to other transistor materials for Schottky barrier extraction as long as C it is sufficiently smaller than C ox . To further understand the exact distribution of trap densities in MoS 2 devices, TCAD simulations are employed. 2.2 Dit distribution extraction with TCAD Using TCAD simulations, we have extracted a D it (E) distribution that is consistent with the experimental temperature dependence of SS. The simulations are carried out with Synopsys Sentaurus Device (SDevice), in which the 2-D material channel is represented as a bulk semiconductor with a 2-D density of states [ 12 ]. Figure 3 a shows the simulated structure, which mimics the experimental device. The source and drain contacts are modeled with a non-local Schottky barrier tunneling model [ 13 ]. An energy dependent D it distribution is assumed at the MoS 2 -aBN interface and specified in SDevice, using an energy dependent-D it lookup table with an overall resolution of 50 meV and a 15 meV refinement for the first point. To capture in particular the on-state performance of our devices, a temperature dependent mobility, µ has been used as obtained from our earlier extraction on the same gate stack [ 14 ] (see Fig. 3 b). Other material parameters for MoS 2 are obtained from [ 15 ]. The remaining calibration parameters are the values of the D it distribution at each energy inside the TMD bandgap (independent of temperature) and the contact Schottky barrier height. While the deep off-state in the thermionic transport regime is used to determine D it (E) from the various temperature dependent measurements, the actual on-state performance is captured by the Schottky barrier height. Note that D it (T) in Fig. 2 d is the result of the integrated impact of D it (E) for a particular temperature. Figure 3 c shows that the temperature dependence of the transfer characteristics can be well captured with a SBH of 180 meV and a D it distribution that peaks towards the conduction band edge (E C ) as shown in Fig. 3 d. It should be noted that the simulations also show a V T -variation with temperature, even though no additional parameter had been varied with temperature, indicating that the shift between the 200 K and the 300 K curves arises from the interface trap density profile. The calibrated SBH of 180 meV is substantially larger than that obtained from the extraction methodology in the previous section, and Fig. 4 a shows that the previously extracted value of 90 meV (calculated without threshold voltage correction of transfer characteristics) would result in a significant overestimation of the device currents, in particular for lower temperatures. For completeness, we also include the case of a higher SBH of 270 meV, showing the uniqueness of the calibrated value of 180 meV mentioned before. We further demonstrate that the experimental temperature dependence of the SS cannot be captured using a uniform D it energy distribution. Figure 4 b shows that for any given value of the uniform D it , the simulated SS increases with temperature as discussed above in the context of Eq. ( 2 ), in contrast to the relatively constant experimental SS values of Fig. 2 a. On the other hand, Fig. 4 c shows that with a temperature independent peaked D it (E) distribution, the temperature-induced SS increase is compensated as the Fermi-level shifts away from E C and toward lower values of D it . For the calibrated D it distribution, the SS is nearly constant within the considered temperature range, which corresponds to the experimentally observed trend. 3. Conclusions In this study, the effect of interface traps on the extraction of Schottky barrier height is investigated. The SBH extracted from temperature dependent transfer characteristics of MoS 2 transistors is significantly lower than the value extracted from TCAD simulations. TCAD simulations reveal that the calibrated SBH is two times higher than the experimentally extracted SBH using the approach described in [ 1 ]. This is due to the high interface trap densities at the 2D material/dielectric (MoS 2 /a-BN/HfO 2 ) interface which results in underestimation of the SBH. The interface trap density is not only high, of the order of 10 14 cm − 2 eV − 1 at the band edge, but also changes over an appreciable energy range inside the bandgap of MoS 2 . Declarations Author Contribution H.J. and D.V. contributed equally. H.J. analyzed the experimental data and results. D.V., S.S., C.J.L.R., and G.S.K. discussed SBH extraction method using TCAD and D.V. performed the TCAD simulations. Z.S. fabricated the device and conducted the electrical characterization. H.J., D.V., Z.S., and J.A. wrote the manuscript. All authors reviewed the manuscript. References Appenzeller, J., Radosavljevi´c, M., Knoch, J., Avouris, P.: Tunneling versus thermionic emission in one-dimensional semiconductors. Physical review letters 92(4), 048301 (2004) Zheng, X., Cal`o, A., Albisetti, E., Liu, X., Alharbi, A.S.M., Arefe, G., Liu, X., Spieser, M., Yoo, W.J., Taniguchi, T., et al.: Patterning metal contacts on monolayer MoS 2 with vanishing Schottky barriers using thermal nanolithography. Nature Electronics 2(1), 17–25 (2019) Kwon, J., Lee, J.-Y., Yu, Y.-J., Lee, C.-H., Cui, X., Hone, J., Lee, G.-H.: Thickness-dependent Schottky barrier height of MoS 2 field-effect transistors. Nanoscale 9(18), 6151–6157 (2017) Mitta, S.B., Choi, M.S., Nipane, A., Ali, F., Kim, C., Teherani, J.T., Hone, J., Yoo, W.J.: Electrical characterization of 2D materials-based field-effect transistors. 2D Materials 8(1), 012002 (2020) Kaushik, N., Nipane, A., Basheer, F., Dubey, S., Grover, S., Deshmukh, M.M., Lodha, S.: Schottky barrier heights for Au and Pd contacts to MoS 2 . Applied Physics Letters 105(11) (2014) Gaur, A., Agarwal, T., Asselberghs, I., Radu, I., Heyns, M., Lin, D.: A MOS capacitor model for ultra-thin 2D semiconductors: the impact of interface defects and channel resistance. 2D Materials 7(3), 035018 (2020) Wang, S.-K., Cao, M., Sun, B., Li, H., Liu, H.: Reducing the interface trap density in Al 2 O 3 /InP stacks by low-temperature thermal process. Applied Physics Express 8(9), 091201 (2015) Kaneki, S., Hashizume, T.: Interface characterization of Al 2 O 3 /m-plane GaN structure. AIP Advances 11(1) (2021) Thomas, S.M.: Electrical characterisation of novel silicon MOSFETs and finFETs. PhD thesis, University of Warwick (2011) Cheng, J.-Y., Yeung, C.W., Hu, C.: Extraction of front and buried oxide interface trap densities in fully depleted silicon-on-insulator metal-oxide-semiconductor field-effect transistor. ECS Solid State Letters 2(5), 32 (2013) Novkovski, N.: Modification of the Terman method for determination of interface states in metal–insulator–semiconductor structures. Journal of Physics Communications 1(3), 035006 (2017) Verreck, D., Arutchelvan, G., Lockhart De La Rosa, C.J., Leonhardt, A., Chiappe, D., Lu, A.K.A., Pourtois, G., Matagne, P., Heyns, M.M., De Gendt, S., Mocuta, A., Radu, I.P.: The role of nonidealities in the scaling of MoS 2 FETs. IEEE Transactions on Electron Devices 65(10), 4635–4640 (2018) Synopsys: Sentaurus Device User Guide. (T-2022.03). p. 852 Sun, Z., Chen, C., Robinson, J.A., Chen, Z., Appenzeller, J.: A mobility study of monolayer MoS 2 on low-κ/high-κ dielectrics. In: 2023 Device Research Conference (DRC), pp. 1–2 (2023). IEEE Laturia, A., Put, M.L., Vandenberghe, W.G.: Dielectric properties of hexagonal boron nitride and transition metal dichalcogenides: from monolayer to bulk. Npj 2D Materials and Applications 2(1), 6 (2018). Publisher: Springer US ISBN:4169901800 Additional Declarations No competing interests reported. Cite Share Download PDF Status: Published Journal Publication published 01 Jul, 2025 Read the published version in npj 2D Materials and Applications → Version 1 posted Editorial decision: Revision requested 02 Apr, 2025 Reviews received at journal 16 Mar, 2025 Reviews received at journal 12 Mar, 2025 Reviewers agreed at journal 24 Feb, 2025 Reviewers agreed at journal 20 Feb, 2025 Reviewers agreed at journal 18 Feb, 2025 Reviewers invited by journal 18 Feb, 2025 Editor assigned by journal 18 Feb, 2025 Submission checks completed at journal 31 Jan, 2025 First submitted to journal 24 Jan, 2025 You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. 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Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-5897670","acceptedTermsAndConditions":true,"allowDirectSubmit":false,"archivedVersions":[],"articleType":"Article","associatedPublications":[],"authors":[{"id":409550954,"identity":"f32a4020-bc38-4360-bbb3-d6d733cba2ae","order_by":0,"name":"Himani Jawa","email":"","orcid":"","institution":"Purdue University","correspondingAuthor":false,"prefix":"","firstName":"Himani","middleName":"","lastName":"Jawa","suffix":""},{"id":409550959,"identity":"6133468c-8798-4651-8288-ba3265d16b47","order_by":1,"name":"Devin Verreck","email":"","orcid":"","institution":"IMEC","correspondingAuthor":false,"prefix":"","firstName":"Devin","middleName":"","lastName":"Verreck","suffix":""},{"id":409550960,"identity":"93e78a4d-b2ab-4a65-ad0a-7ccad1e36005","order_by":2,"name":"Zheng Sun","email":"","orcid":"","institution":"Purdue University","correspondingAuthor":false,"prefix":"","firstName":"Zheng","middleName":"","lastName":"Sun","suffix":""},{"id":409550963,"identity":"636a519f-80fe-4d40-a65f-0dc2b6ede6aa","order_by":3,"name":"Surajit Sutar","email":"","orcid":"","institution":"IMEC","correspondingAuthor":false,"prefix":"","firstName":"Surajit","middleName":"","lastName":"Sutar","suffix":""},{"id":409550965,"identity":"a6e8c20a-c5e1-47c6-8d88-82a2ba17b74a","order_by":4,"name":"Cesar Javier Lockhart Rosa","email":"","orcid":"","institution":"IMEC","correspondingAuthor":false,"prefix":"","firstName":"Cesar","middleName":"Javier Lockhart","lastName":"Rosa","suffix":""},{"id":409550969,"identity":"00261039-fb0d-486f-a075-b5845eec079a","order_by":5,"name":"Gouri Sankar Kar","email":"","orcid":"","institution":"IMEC","correspondingAuthor":false,"prefix":"","firstName":"Gouri","middleName":"Sankar","lastName":"Kar","suffix":""},{"id":409550972,"identity":"133620bf-c8bc-4d33-9998-8c869a5aabb9","order_by":6,"name":"Joerg Appenzeller","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAAA9UlEQVRIiWNgGAWjYBADGT4GBsYHQAZjA4jLQ4QWHjYGBmYDkrWwSRClhX9278HHBX9seNjYe59VF7bdk91wvIHxwds23Fok7pxLNp7Bk8bDxnPc7PbMtmLjDWcOMBvOxaOF4UaOmTSPxGEeNok0ttu8bQmJG24ksEnz4tEifyPH/DePwX8eNvlnbMVgLfcfsP/Gp8UAaAszT8IBoC1sbMwQWxhADNxaDIF+keY5kAz0Sxqz9IxzCcYzzyQ2S845h1uL3O3eg595/tjJ8bMfY/xcUJYg23f88MEPb8rweF8CKQqYIRQkakjSMgpGwSgYBaMAFQAA7M1LeBdaXE0AAAAASUVORK5CYII=","orcid":"","institution":"Purdue University","correspondingAuthor":true,"prefix":"","firstName":"Joerg","middleName":"","lastName":"Appenzeller","suffix":""}],"badges":[],"createdAt":"2025-01-24 18:08:15","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-5897670/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-5897670/v1","draftVersion":[],"editorialEvents":[{"content":"https://doi.org/10.1038/s41699-025-00576-y","type":"published","date":"2025-07-01T15:58:34+00:00"}],"editorialNote":"","failedWorkflow":false,"files":[{"id":75409323,"identity":"fb75af8a-1942-4d87-9871-7e4d903c7e82","added_by":"auto","created_at":"2025-02-04 09:03:23","extension":"png","order_by":1,"title":"Figure 1","display":"","copyAsset":false,"role":"figure","size":176115,"visible":true,"origin":"","legend":"\u003cp\u003e(a) Schematic diagram of an as-fabricated device. (b) Transfer and (c) output characteristics of an exemplary transistor with a channel length of L= 200 nm. (d) Temperature dependent transfer characteristics and (e) extracted effective barrier height (\u003cem\u003eϕ\u003c/em\u003e\u003csub\u003e\u003cem\u003eB\u003c/em\u003e\u003c/sub\u003e) as a function of applied gate voltage.\u003c/p\u003e","description":"","filename":"floatimage1.png","url":"https://assets-eu.researchsquare.com/files/rs-5897670/v1/4fab069c776c46c4606f588a.png"},{"id":75409322,"identity":"1989f248-cc0c-4917-8395-3f1f2a958903","added_by":"auto","created_at":"2025-02-04 09:03:22","extension":"png","order_by":2,"title":"Figure 2","display":"","copyAsset":false,"role":"figure","size":116386,"visible":true,"origin":"","legend":"\u003cp\u003e(a) Temperature dependent transfer characteristics after correcting for the apparent threshold voltage shifts and (b) Arrhenius plot (log(I\u003csub\u003eDS\u003c/sub\u003e/T\u003csup\u003e2\u003c/sup\u003e) vs. 1000/T) showing positive slope (c). Expected and extracted inverse subthreshold slope of the transistor in figure 1. (d) Interface trap density vs. temperature extracted from SS, evaluated between 1e-3 to 1e-4 \u003cem\u003eµ\u003c/em\u003eA/\u003cem\u003eµ\u003c/em\u003em.\u003c/p\u003e","description":"","filename":"floatimage2.png","url":"https://assets-eu.researchsquare.com/files/rs-5897670/v1/611732e75a10f35b461e6e1a.png"},{"id":75409328,"identity":"0bc3bdd8-47a9-43f4-a0be-0639482f7e52","added_by":"auto","created_at":"2025-02-04 09:03:23","extension":"png","order_by":3,"title":"Figure 3","display":"","copyAsset":false,"role":"figure","size":157682,"visible":true,"origin":"","legend":"\u003cp\u003e(a) Simulated structure mimicking the experimental structure of Figure \u003ca href=\"#_bookmark0\"\u003e1\u003c/a\u003e(a), with a 0.2 nm van der Waals gap between the MoS\u003csub\u003e2\u003c/sub\u003e and a-BN (b) temperature dependent mobility impacted by phonon scattering as used in these simulations, (c) calibration of temperature dependent simulated transfer characteristics to experimental measurements of Figure \u003ca href=\"#_bookmark1\"\u003e1\u003c/a\u003ed, (d) resulting calibrated D\u003csub\u003e\u003cem\u003eit\u003c/em\u003e\u003c/sub\u003e distribution.\u003c/p\u003e","description":"","filename":"floatimage3.png","url":"https://assets-eu.researchsquare.com/files/rs-5897670/v1/a51c5d98a8c284f01e111572.png"},{"id":75409327,"identity":"31a5df01-5fd0-46f9-b48f-7d523b8629da","added_by":"auto","created_at":"2025-02-04 09:03:23","extension":"png","order_by":4,"title":"Figure 4","display":"","copyAsset":false,"role":"figure","size":267478,"visible":true,"origin":"","legend":"\u003cp\u003e(a) Comparison of temperature dependent experimental transfer characteristics with simulated curves for varying SBH values. (b) Simulated SS variation with temperature for a uniform D\u003csub\u003eit\u003c/sub\u003e distribution throughout the MoS\u003csub\u003e2\u003c/sub\u003e bandgap. (c) Simulated SS variation with temperature for a calibrated D\u003csub\u003eit\u003c/sub\u003e distribution of Figure 3(c). The D\u003csub\u003eit\u003c/sub\u003e distribution is scaled by a constant factor (DitFact), such that D\u003csub\u003eit\u003c/sub\u003e=Ditfact * (D\u003csub\u003eit\u003c/sub\u003e profile in Figure 3d). SS is extracted in the I\u003csub\u003e\u003cem\u003eDS\u003c/em\u003e\u003c/sub\u003e\u003cem\u003e \u003c/em\u003erange of 1e-4 -1e-3 \u003cem\u003eµ\u003c/em\u003eA/\u003cem\u003eµ\u003c/em\u003em. Indicated are also the experimental values corresponding to Figure \u003ca href=\"#_bookmark1\"\u003e2\u003c/a\u003ec.\u003c/p\u003e","description":"","filename":"floatimage4.png","url":"https://assets-eu.researchsquare.com/files/rs-5897670/v1/68a17f7b77f5fc15dad4438b.png"},{"id":86179219,"identity":"250379da-21c2-453c-b5ad-521226016ca3","added_by":"auto","created_at":"2025-07-07 16:17:23","extension":"pdf","order_by":0,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":983032,"visible":true,"origin":"","legend":"","description":"","filename":"manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-5897670/v1/686c9ef1-f4fc-4c40-808d-bc86fc4c9132.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"\u003cp\u003eInterface trap states induced underestimation of Schottky barrier height in Metal-MX\u003csub\u003e2\u003c/sub\u003e Junctions\u003c/p\u003e","fulltext":[{"header":"1. Introduction","content":"\u003cp\u003eFrequently, field-effect transistors based on novel semiconducting channel materials are built without mimicking the n/p/n or p/n/p doping profile of a conventional silicon-based metal oxide semiconductor field-effect transistor (MOSFET). In fact, the most common way of building prototype FETs is to employ metal source/drain contacts in conjunction with a gating scheme that controls the entire semiconducting channel. In most instances, a Si/SiO\u003csub\u003e2\u003c/sub\u003e substrate with a thick dielectric layer is used as a global back gate, allowing for quick access to some basic device characteristics. For devices of this type, the contact resistance is dominated by the Schottky barrier at the source/drain-to-channel interfaces. In 2004 [\u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e], we discussed a novel approach to extract information, in particular the Schottky barrier height (SBH), using carbon nanotubes as an example. The idea was that the ultra-thin body of the channel material impacts, i.e. reduces the Schottky barrier thickness (SBT) in the gated channel region. This change in turn allows for substantial thermal assisted tunneling between the contacts and the channel, impacting the inverse subthreshold slope (SS) of the device in its off-state. In fact, for gate voltages in the device off-state close to threshold, SS cannot reach the thermal limit, e.g. \u0026sim;60 mV/dec at room temperature, irrespective of the chosen gate oxide thickness, since this regime is impacted by the gate voltage response of the Schottky barrier thickness (SBT). Through a careful analysis of the \u0026ldquo;effective barrier height\u0026rdquo; ϕ\u003csub\u003eB\u003c/sub\u003e, the one that can be extracted from an Arrhenius plot of device current versus inverse temperature T for different gate voltages V\u003csub\u003eGS\u003c/sub\u003e, the actual Schottky barrier height can be identified [\u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e]. Our method has since been used frequently, including for ultra-thin body devices from transition metal dichalcogenides (TMDs).\u003c/p\u003e \u003cp\u003eIn a number of instances very small extracted Schottky barrier heights of 12.5 meV, 64 meV, and 16 meV were reported [\u003cspan additionalcitationids=\"CR3\" citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e\u0026ndash;\u003cspan citationid=\"CR4\" class=\"CitationRef\"\u003e4\u003c/span\u003e]. As we discussed in our original paper, there are a couple of signatures that need to be present to ensure that the extracted SBH is indeed the one that actually determines the current transport. For example, (1) SS needs to be proportional to T in the thermal regime \u0026ndash; i.e. in the deep off-state of the device \u0026ndash; for our analysis to be applicable. Another sanity check is (2) the expected correlation between log(I\u003csub\u003eDS\u003c/sub\u003e) vs. V\u003csub\u003eGS\u003c/sub\u003e and ϕ\u003csub\u003eB\u003c/sub\u003e vs. V\u003csub\u003eGS\u003c/sub\u003e in the thermal regime. In fact, for fully depleted devices (C\u003csub\u003eD\u003c/sub\u003e= 0), SS in the thermal regime should be (k\u003csub\u003eB\u003c/sub\u003eT/q) \u0026lowast; ln(10) \u0026lowast; m with m\u0026thinsp;=\u0026thinsp;1\u0026thinsp;+\u0026thinsp;C\u003csub\u003eit\u003c/sub\u003e/C\u003csub\u003eox\u003c/sub\u003e for constant C\u003csub\u003eit\u003c/sub\u003e and C\u003csub\u003eox\u003c/sub\u003e and \u0026minus;(dϕ\u003csub\u003eB\u003c/sub\u003e/dV\u003csub\u003eGS\u003c/sub\u003e)\u003csup\u003e\u0026minus;1\u003c/sup\u003e = m. In case of reference [\u003cspan citationid=\"CR4\" class=\"CitationRef\"\u003e4\u003c/span\u003e] condition (1) does not apply, as apparent from Fig.\u0026nbsp;9b in [\u003cspan citationid=\"CR4\" class=\"CitationRef\"\u003e4\u003c/span\u003e]. Condition (2) is clearly violated in [\u003cspan additionalcitationids=\"CR3\" citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e\u0026ndash;\u003cspan citationid=\"CR4\" class=\"CitationRef\"\u003e4\u003c/span\u003e] as evident from Fig.\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003e if compared to Fig.\u0026nbsp;\u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003eb in reference [\u003cspan citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e], from the absence of any ϕ\u003csub\u003eB\u003c/sub\u003e-dependence in figure S3 in [\u003cspan citationid=\"CR3\" class=\"CitationRef\"\u003e3\u003c/span\u003e], and from Fig.\u0026nbsp;9b, if compared to Fig.\u0026nbsp;9d in reference [\u003cspan citationid=\"CR4\" class=\"CitationRef\"\u003e4\u003c/span\u003e], where \u0026ldquo;m\u0026rdquo; is labeled as \u0026ldquo;γ\u003csup\u003e-1\u003c/sup\u003e\u0026rdquo;, respectively.\u003c/p\u003e \u003cp\u003eIn the following, we will elucidate why above articles presumably vastly underestimated the actual SBH by comparing our own data with those previously published. In particular, we will identify a strong temperature dependence of C\u003csub\u003eit\u003c/sub\u003e as the culprit for why our previously proposed SBH extraction method [\u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e] cannot be applied. To do that, we fabricated monolayer MoS\u003csub\u003e2\u003c/sub\u003e transistors and electrically characterized the devices at different temperatures to extract the SBH and to understand the effect of the interface traps on the transfer characteristics, especially in the subthreshold regime. Additionally, TCAD simulations are employed to model the distribution of interface traps which explain the change in subthreshold slope with temperature and underestimation of extracted SBH.\u003c/p\u003e"},{"header":"2. Results","content":"\u003cdiv id=\"Sec3\" class=\"Section2\"\u003e \u003ch2\u003e2.1 Device fabrication and electrical characteristics\u003c/h2\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eFigure \u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003ea shows the schematic of the as-fabricated MoS\u003csub\u003e2\u003c/sub\u003e transistor. The local bottom gates (LBGs) were first fabricated on a Si/SiO\u003csub\u003e2\u003c/sub\u003e substrate by lithography and metallization, followed by the deposition of 5.5 nm ALD HfO\u003csub\u003e2\u003c/sub\u003e and 3.6 nm amorphous Boron Nitride (aBN), serving as the bottom gate dielectric. Next, a monolayer MoS\u003csub\u003e2\u003c/sub\u003e film was wet transferred onto the LBG substrate and etched by reactive ion etching with Cl\u003csub\u003e2\u003c/sub\u003e/O\u003csub\u003e2\u003c/sub\u003e at a power of 40 W for 15 seconds. Finally, Ni source/drain (S/D) contacts were patterned using e-beam lithography and e-beam evaporation. Figure\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003eb and \u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003ec show the transfer and output characteristics of an exemplary MoS\u003csub\u003e2\u003c/sub\u003e transistor with a channel length of 200 nm. The device shows good off-state behavior, such as negligible drain-induced barrier lowering (DIBL) and low inverse subthreshold slope (SS \u0026sim; 100 mV/decade, extracted between 1e-3 to 1e-4 \u003cem\u003e\u0026micro;\u003c/em\u003eA/\u003cem\u003e\u0026micro;\u003c/em\u003em), and a high on-state current of \u0026sim; 180 \u003cem\u003e\u0026micro;\u003c/em\u003eA/\u003cem\u003e\u0026micro;\u003c/em\u003em at V\u003csub\u003e\u003cem\u003eDS\u003c/em\u003e\u003c/sub\u003e = 1 V.\u003c/p\u003e \u003cp\u003eTo study the impact of the interface trap density on the SBH extraction, we measured the transfer characteristics of ML MoS\u003csub\u003e2\u003c/sub\u003e transistors at different temperatures for V\u003csub\u003e\u003cem\u003eD\u003c/em\u003e\u003c/sub\u003e = 0.1 V as shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003ed. At gate biases below flatband voltage (\u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003eGS\u003c/em\u003e\u003c/sub\u003e \u0026le; \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003eFB\u003c/em\u003e\u003c/sub\u003e, here at current values of around 1e-3 \u003cem\u003e\u0026micro;\u003c/em\u003eA/\u003cem\u003e\u0026micro;\u003c/em\u003em) the thermionic current determines the current through the device, with \u003cem\u003eI\u003c/em\u003e\u003csub\u003e\u003cem\u003eDS\u003c/em\u003e\u003c/sub\u003e given by [\u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e]:\u003cdiv id=\"Equ1\" class=\"Equation\"\u003e\u003cdiv format=\"TEX\" class=\"mathdisplay\" id=\"FileID_Equ1\" name=\"EquationSource\"\u003e\n$$\\:{I}_{DS}A{T}^{2}{e}^{\\frac{-q{\\varPhi\\:}_{B}}{{k}_{B}T}}$$\u003c/div\u003e\u003cdiv class=\"EquationNumber\"\u003e1\u003c/div\u003e\u003c/div\u003e\u003c/p\u003e \u003cp\u003ewhere A is the Richardson\u0026rsquo;s constant, \u003cem\u003eϕ\u003c/em\u003e\u003csub\u003e\u003cem\u003eB\u003c/em\u003e\u003c/sub\u003e is the effective barrier height, \u003cem\u003ek\u003c/em\u003e\u003csub\u003e\u003cem\u003eB\u003c/em\u003e\u003c/sub\u003e is the Boltzmann constant, q is the electronic charge, and T is the temperature. In order to extract the actual SBH (\u003cem\u003eϕ\u003c/em\u003e\u003csub\u003e\u003cem\u003eSB\u003c/em\u003e\u003c/sub\u003e), the temperature dependent current values (shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003ed) are used to generate an Arrhenius plot (log(\u003cem\u003eI\u003c/em\u003e\u003csub\u003e\u003cem\u003eDS\u003c/em\u003e\u003c/sub\u003e\u003cem\u003e/T\u003c/em\u003e \u003csup\u003e2\u003c/sup\u003e) vs. 1000/T), and the slope of the Arrhenius plot results in a \u003cem\u003eϕ\u003c/em\u003e\u003csub\u003e\u003cem\u003eB\u003c/em\u003e\u003c/sub\u003e vs. \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003eGS\u003c/em\u003e\u003c/sub\u003e plot, as shown in 1e. Note that using this technique over the entire gate voltage range means that \u003cem\u003eϕ\u003c/em\u003e\u003csub\u003e\u003cem\u003eB\u003c/em\u003e\u003c/sub\u003e is only capturing the \u0026ldquo;actual\u0026rdquo; barrier height for \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003eGS\u003c/em\u003e\u003c/sub\u003e \u0026le; \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003eFB\u003c/em\u003e\u003c/sub\u003e which allows to identify the Schottky barrier height \u003cem\u003eϕ\u003c/em\u003e\u003csub\u003e\u003cem\u003eSB\u003c/em\u003e\u003c/sub\u003e, given that for gate biases lower than V\u003csub\u003e\u003cem\u003eFB\u003c/em\u003e\u003c/sub\u003e the effective barrier height \u003cem\u003eϕ\u003c/em\u003e\u003csub\u003e\u003cem\u003eB\u003c/em\u003e\u003c/sub\u003e varies linearly with \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003eGS\u003c/em\u003e\u003c/sub\u003e in the thermionic transport regime. This leads to the extraction of a Schottky barrier height, SBH \u0026sim; 90\u0026thinsp;\u0026plusmn;\u0026thinsp;10 meV. It is important to note that (1) this value of SBH extracted from the transfer characteristics is significantly lower than the SBH obtained from TCAD simulations by fitting our experimental data, which will be discussed later in this paper and (2) the calculations have not been corrected for threshold voltage shifts in transfer characteristics at different temperatures, which is a common practice found in the literature [\u003cspan citationid=\"CR4\" class=\"CitationRef\"\u003e4\u003c/span\u003e, \u003cspan citationid=\"CR5\" class=\"CitationRef\"\u003e5\u003c/span\u003e]. Hence, to understand the effect of threshold voltage (V\u003csub\u003eT\u003c/sub\u003e) correction on the SBH extraction and the underlying reason behind the V\u003csub\u003eT\u003c/sub\u003e shift, the transfer characteristics are adjusted, as shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e2\u003c/span\u003ea. Using these corrected current values, the Arrhenius plot (log(\u003cem\u003eI\u003c/em\u003e\u003csub\u003e\u003cem\u003eDS\u003c/em\u003e\u003c/sub\u003e\u003cem\u003e/T\u003c/em\u003e \u003csup\u003e2\u003c/sup\u003e) vs. 1000/T) is again generated. This time the slopes (-q\u003cem\u003eϕ\u003c/em\u003e\u003csub\u003e\u003cem\u003eB\u003c/em\u003e\u003c/sub\u003e/k\u003csub\u003eB\u003c/sub\u003e) are positive as shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e2\u003c/span\u003eb, resulting in a negative SBH extraction, which is also not consistent with our TCAD simulations. This erroneous SBH value extracted post V\u003csub\u003eT\u003c/sub\u003e correction is a result of the fact that in reality, the V\u003csub\u003eT\u003c/sub\u003e shifts with temperature in this device originate from a varying interface trap density profile, which we will demonstrate from our TCAD simulations in the next section.\u003c/p\u003e \u003cp\u003eNoticing that the small extracted Schottky barrier height (without any V\u003csub\u003eT\u003c/sub\u003e correction) is a result of the very small temperature dependence of the subthreshold currents, we next extracted the inverse subthreshold slope (SS) in the deep off state for currents between 1e-3 to 1e-4 \u003cem\u003e\u0026micro;\u003c/em\u003eA/\u003cem\u003e\u0026micro;\u003c/em\u003em that correspond to the thermionic emission regime. Under these conditions SS is expected to exhibit the following temperature dependence:\u003cdiv id=\"Equ2\" class=\"Equation\"\u003e\u003cdiv format=\"TEX\" class=\"mathdisplay\" id=\"FileID_Equ2\" name=\"EquationSource\"\u003e\n$$\\:SS=\\:\\frac{{k}_{B}T}{q}(1+\\frac{{C}_{D}+{C}_{it}}{{C}_{ox}})$$\u003c/div\u003e\u003cdiv class=\"EquationNumber\"\u003e2\u003c/div\u003e\u003c/div\u003e\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003ewhere C\u003csub\u003e\u003cem\u003eD\u003c/em\u003e\u003c/sub\u003e is the depletion capacitance, C\u003csub\u003e\u003cem\u003eit\u003c/em\u003e\u003c/sub\u003e is the capacitance due to a finite interface trap density (D\u003csub\u003e\u003cem\u003eit\u003c/em\u003e\u003c/sub\u003e), given by C\u003csub\u003e\u003cem\u003eit\u003c/em\u003e\u003c/sub\u003e = \u003cem\u003eq\u003c/em\u003e\u003csup\u003e2\u003c/sup\u003e \u0026lowast; D\u003csub\u003e\u003cem\u003eit\u003c/em\u003e\u003c/sub\u003e and C\u003csub\u003e\u003cem\u003eox\u003c/em\u003e\u003c/sub\u003e is the gate oxide capacitance. Given the absence of any variation of depletion charge in the MoS\u003csub\u003e2\u003c/sub\u003e channel to the applied gate bias, C\u003csub\u003e\u003cem\u003eD\u003c/em\u003e\u003c/sub\u003e is zero in our fully depleted devices. Assuming no dependence of D\u003csub\u003e\u003cem\u003eit\u003c/em\u003e\u003c/sub\u003e on temperature, the subthreshold slope should linearly increase as the temperature rises, as represented by the black dots in Fig.\u0026nbsp;\u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e2\u003c/span\u003ec, assuming that at 300 K the actual D\u003csub\u003e\u003cem\u003eit\u003c/em\u003e\u003c/sub\u003e value had been extracted. However, the extracted SS-values from the subthreshold characteristics at different temperatures as shown by red dots in Fig.\u0026nbsp;\u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e2\u003c/span\u003ec are almost temperature independent. To explain the apparent absence of the expected temperature dependent trend from Eq.\u0026nbsp;(\u003cspan refid=\"Equ2\" class=\"InternalRef\"\u003e2\u003c/span\u003e), one has to conclude that C\u003csub\u003e\u003cem\u003eit\u003c/em\u003e\u003c/sub\u003e is a function of T. The resulting D\u003csub\u003e\u003cem\u003eit\u003c/em\u003e\u003c/sub\u003e(T) is plotted in Fig.\u0026nbsp;\u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e2\u003c/span\u003ed. Interestingly, D\u003csub\u003e\u003cem\u003eit\u003c/em\u003e\u003c/sub\u003e increases with decreasing temperature, reaching a maximum value of 3*10\u003csup\u003e13\u003c/sup\u003e eV\u003csup\u003e-1\u003c/sup\u003ecm\u003csup\u003e-2\u003c/sup\u003e at 80 K. This finding is consistent with previous results by the IMEC group [\u003cspan citationid=\"CR6\" class=\"CitationRef\"\u003e6\u003c/span\u003e] which show higher trap densities at lower temperatures from detailed capacitance measurements on TMDs as a function of T. The study combines the static model in the small signal regime with the distributed R-C network of the semiconductor to understand the dynamic nature of the MOS capacitor, focusing on segregating the effects of channel resistance from interface traps. The interface traps in such a way extracted for a 4 nm HfO\u003csub\u003e2\u003c/sub\u003e/3\u0026ndash;5 ML MoS\u003csub\u003e2\u003c/sub\u003e stack show an exponentially increasing amount of defect states originating from the conduction band of MoS\u003csub\u003e2\u003c/sub\u003e. In short, despite using different methodologies (temperature dependent transfer characteristics in this study and C-V characteristics used in IMEC study [\u003cspan citationid=\"CR6\" class=\"CitationRef\"\u003e6\u003c/span\u003e]), both studies obtain an interface trap density distribution that increases approximately exponentially towards the MoS\u003csub\u003e2\u003c/sub\u003e conduction band edge at the MoS\u003csub\u003e2\u003c/sub\u003e-dielectric interface. Hence, the expected decrease of SS with decreasing T is compensated for by an increase of D\u003csub\u003e\u003cem\u003eit\u003c/em\u003e\u003c/sub\u003e(T) for decreasing temperature. This implies that similar to references [\u003cspan citationid=\"CR3\" class=\"CitationRef\"\u003e3\u003c/span\u003e] and [\u003cspan citationid=\"CR4\" class=\"CitationRef\"\u003e4\u003c/span\u003e] our own MoS\u003csub\u003e2\u003c/sub\u003e data cannot be used to extract the Schottky barrier height at the source/drain metal to TMD channel interface employing the methodology proposed in reference [\u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e]. Also, similar to references [\u003cspan additionalcitationids=\"CR3\" citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e\u0026ndash;\u003cspan citationid=\"CR4\" class=\"CitationRef\"\u003e4\u003c/span\u003e], when using the extraction methodology nonetheless, a vastly underestimated \u003cem\u003eϕ\u003c/em\u003e\u003csub\u003e\u003cem\u003eSB\u003c/em\u003e\u003c/sub\u003e-value is extracted.\u003c/p\u003e \u003cp\u003eOne may ask the question whether the strong dependence of our D\u003csub\u003e\u003cem\u003eit\u003c/em\u003e\u003c/sub\u003e on temperature is a unique result of the TMD-to-gate stack interface. The answer is \u0026ldquo;no\u0026rdquo;. In fact, the observed temperature dependence can be translated into a D\u003csub\u003e\u003cem\u003eit\u003c/em\u003e\u003c/sub\u003e profile inside the TMD bandgap as a function of the energetic position relative to the band edges as discussed in the next section and that is qualitatively consistent with what has been previously reported for other semiconducting channels, e.g. III-V [\u003cspan citationid=\"CR7\" class=\"CitationRef\"\u003e7\u003c/span\u003e, \u003cspan citationid=\"CR8\" class=\"CitationRef\"\u003e8\u003c/span\u003e] and silicon [\u003cspan additionalcitationids=\"CR10\" citationid=\"CR9\" class=\"CitationRef\"\u003e9\u003c/span\u003e\u0026ndash;\u003cspan citationid=\"CR11\" class=\"CitationRef\"\u003e11\u003c/span\u003e]. The difference, however, lies in the magnitude of D\u003csub\u003e\u003cem\u003eit\u003c/em\u003e\u003c/sub\u003e. While silicon technology has achieved D\u003csub\u003e\u003cem\u003eit\u003c/em\u003e\u003c/sub\u003e-values in the 10\u003csup\u003e10\u003c/sup\u003e eV\u003csup\u003e-1\u003c/sup\u003ecm\u003csup\u003e-2\u003c/sup\u003e to 10\u003csup\u003e11\u003c/sup\u003e eV\u003csup\u003e-1\u003c/sup\u003ecm\u003csup\u003e-2\u003c/sup\u003e range, our extracted D\u003csub\u003e\u003cem\u003eit\u003c/em\u003e\u003c/sub\u003e-values at room temperature are substantially higher. This is also the reason why the methodology in reference [\u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e] can readily be applied to other transistor materials for Schottky barrier extraction as long as C\u003csub\u003e\u003cem\u003eit\u003c/em\u003e\u003c/sub\u003e is sufficiently smaller than C\u003csub\u003e\u003cem\u003eox\u003c/em\u003e\u003c/sub\u003e. To further understand the exact distribution of trap densities in MoS\u003csub\u003e2\u003c/sub\u003e devices, TCAD simulations are employed.\u003c/p\u003e \u003c/div\u003e \u003cdiv id=\"Sec4\" class=\"Section2\"\u003e \u003ch2\u003e2.2 Dit distribution extraction with TCAD\u003c/h2\u003e \u003cp\u003eUsing TCAD simulations, we have extracted a D\u003csub\u003e\u003cem\u003eit\u003c/em\u003e\u003c/sub\u003e(E) distribution that is consistent with the experimental temperature dependence of SS. The simulations are carried out with Synopsys Sentaurus Device (SDevice), in which the 2-D material channel is represented as a bulk semiconductor with a 2-D density of states [\u003cspan citationid=\"CR12\" class=\"CitationRef\"\u003e12\u003c/span\u003e]. Figure\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003ea shows the simulated structure, which mimics the experimental device. The source and drain contacts are modeled with a non-local Schottky barrier tunneling model [\u003cspan citationid=\"CR13\" class=\"CitationRef\"\u003e13\u003c/span\u003e]. An energy dependent D\u003csub\u003eit\u003c/sub\u003e distribution is assumed at the MoS\u003csub\u003e2\u003c/sub\u003e-aBN interface and specified in SDevice, using an energy dependent-D\u003csub\u003eit\u003c/sub\u003e lookup table with an overall resolution of 50 meV and a 15 meV refinement for the first point. To capture in particular the on-state performance of our devices, a temperature dependent mobility, \u0026micro; has been used as obtained from our earlier extraction on the same gate stack [\u003cspan citationid=\"CR14\" class=\"CitationRef\"\u003e14\u003c/span\u003e] (see Fig.\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003eb). Other material parameters for MoS\u003csub\u003e2\u003c/sub\u003e are obtained from [\u003cspan citationid=\"CR15\" class=\"CitationRef\"\u003e15\u003c/span\u003e]. The remaining calibration parameters are the values of the D\u003csub\u003e\u003cem\u003eit\u003c/em\u003e\u003c/sub\u003e distribution at each energy inside the TMD bandgap (independent of temperature) and the contact Schottky barrier height. While the deep\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eoff-state in the thermionic transport regime is used to determine D\u003csub\u003e\u003cem\u003eit\u003c/em\u003e\u003c/sub\u003e(E) from the various temperature dependent measurements, the actual on-state performance is captured by the Schottky barrier height. Note that D\u003csub\u003e\u003cem\u003eit\u003c/em\u003e\u003c/sub\u003e(T) in Fig.\u0026nbsp;\u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e2\u003c/span\u003ed is the result of the integrated impact of D\u003csub\u003e\u003cem\u003eit\u003c/em\u003e\u003c/sub\u003e(E) for a particular temperature.\u003c/p\u003e \u003cp\u003eFigure \u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003ec shows that the temperature dependence of the transfer characteristics can be well captured with a SBH of 180 meV and a D\u003csub\u003e\u003cem\u003eit\u003c/em\u003e\u003c/sub\u003e distribution that peaks towards the conduction band edge (E\u003csub\u003e\u003cem\u003eC\u003c/em\u003e\u003c/sub\u003e) as shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003ed. It should be noted that the simulations also show a V\u003csub\u003eT\u003c/sub\u003e-variation with temperature, even though no additional parameter had been varied with temperature, indicating that the shift between the 200 K and the 300 K curves arises from the interface trap density profile. The calibrated SBH of 180 meV is substantially larger than that obtained from the extraction methodology in the previous section, and Fig.\u0026nbsp;\u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003ea shows that the previously extracted value of 90 meV (calculated without threshold voltage correction of transfer characteristics) would result in a significant overestimation of the device currents, in particular for lower temperatures. For completeness, we also include the case of a higher SBH of 270 meV, showing the uniqueness of the calibrated value of 180 meV mentioned before.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eWe further demonstrate that the experimental temperature dependence of the SS cannot be captured using a uniform D\u003csub\u003e\u003cem\u003eit\u003c/em\u003e\u003c/sub\u003e energy distribution. Figure\u0026nbsp;\u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003eb shows that for any given value of the uniform D\u003csub\u003e\u003cem\u003eit\u003c/em\u003e\u003c/sub\u003e, the simulated SS increases with temperature as discussed above in the context of Eq.\u0026nbsp;(\u003cspan refid=\"Equ2\" class=\"InternalRef\"\u003e2\u003c/span\u003e), in contrast to the relatively constant experimental SS values of Fig.\u0026nbsp;\u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e2\u003c/span\u003ea. On the other hand, Fig.\u0026nbsp;\u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003ec shows that with a temperature independent peaked D\u003csub\u003e\u003cem\u003eit\u003c/em\u003e\u003c/sub\u003e(E) distribution, the temperature-induced SS increase is compensated as the Fermi-level shifts away from E\u003csub\u003e\u003cem\u003eC\u003c/em\u003e\u003c/sub\u003e and toward lower values of D\u003csub\u003e\u003cem\u003eit\u003c/em\u003e\u003c/sub\u003e. For the calibrated D\u003csub\u003e\u003cem\u003eit\u003c/em\u003e\u003c/sub\u003e distribution, the SS is nearly constant within the considered temperature range, which corresponds to the experimentally observed trend.\u003c/p\u003e \u003c/div\u003e"},{"header":"3. Conclusions","content":"\u003cp\u003eIn this study, the effect of interface traps on the extraction of Schottky barrier height is investigated. The SBH extracted from temperature dependent transfer characteristics of MoS\u003csub\u003e2\u003c/sub\u003e transistors is significantly lower than the value extracted from TCAD simulations. TCAD simulations reveal that the calibrated SBH is two times higher than the experimentally extracted SBH using the approach described in [\u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e]. This is due to the high interface trap densities at the 2D material/dielectric (MoS\u003csub\u003e2\u003c/sub\u003e/a-BN/HfO\u003csub\u003e2\u003c/sub\u003e) interface which results in underestimation of the SBH. The interface trap density is not only high, of the order of 10\u003csup\u003e14\u003c/sup\u003ecm\u003csup\u003e\u003cem\u003e\u0026minus;\u003c/em\u003e2\u003c/sup\u003eeV\u003csup\u003e\u003cem\u003e\u0026minus;\u003c/em\u003e\u0026thinsp;1\u003c/sup\u003e at the band edge, but also changes over an appreciable energy range inside the bandgap of MoS\u003csub\u003e2\u003c/sub\u003e.\u003c/p\u003e"},{"header":"Declarations","content":"\u003ch2\u003eAuthor Contribution\u003c/h2\u003e\u003cp\u003eH.J. and D.V. contributed equally. H.J. analyzed the experimental data and results. D.V., S.S., C.J.L.R., and G.S.K. discussed SBH extraction method using TCAD and D.V. performed the TCAD simulations. Z.S. fabricated the device and conducted the electrical characterization. H.J., D.V., Z.S., and J.A. wrote the manuscript. All authors reviewed the manuscript.\u003c/p\u003e"},{"header":"References","content":"\u003col\u003e\u003cli\u003e\u003cspan\u003eAppenzeller, J., Radosavljevi\u0026acute;c, M., Knoch, J., Avouris, P.: Tunneling versus thermionic emission in one-dimensional semiconductors. Physical review letters 92(4), 048301 (2004)\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eZheng, X., Cal`o, A., Albisetti, E., Liu, X., Alharbi, A.S.M., Arefe, G., Liu, X., Spieser, M., Yoo, W.J., Taniguchi, T., et al.: Patterning metal contacts on monolayer MoS\u003csub\u003e2\u003c/sub\u003e with vanishing Schottky barriers using thermal nanolithography. Nature Electronics 2(1), 17\u0026ndash;25 (2019)\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eKwon, J., Lee, J.-Y., Yu, Y.-J., Lee, C.-H., Cui, X., Hone, J., Lee, G.-H.: Thickness-dependent Schottky barrier height of MoS\u003csub\u003e2\u003c/sub\u003e field-effect transistors. Nanoscale 9(18), 6151\u0026ndash;6157 (2017)\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eMitta, S.B., Choi, M.S., Nipane, A., Ali, F., Kim, C., Teherani, J.T., Hone, J., Yoo, W.J.: Electrical characterization of 2D materials-based field-effect transistors. 2D Materials 8(1), 012002 (2020)\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eKaushik, N., Nipane, A., Basheer, F., Dubey, S., Grover, S., Deshmukh, M.M., Lodha, S.: Schottky barrier heights for Au and Pd contacts to MoS\u003csub\u003e2\u003c/sub\u003e. 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IEEE\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eLaturia, A., Put, M.L., Vandenberghe, W.G.: Dielectric properties of hexagonal boron nitride and transition metal dichalcogenides: from monolayer to bulk. Npj 2D Materials and Applications 2(1), 6 (2018). Publisher: Springer US ISBN:4169901800\u003c/span\u003e\u003c/li\u003e\u003c/ol\u003e"}],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":true,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":false,"highlight":"","institution":"","isAcceptedByJournal":true,"isAuthorSuppliedPdf":false,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":false,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"npj-2d-materials-and-applications","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":false,"externalIdentity":"npj2dmaterials","sideBox":"Learn more about [npj 2D Materials and Applications](http://www.nature.com/npj2dmaterials/)","snPcode":"41699","submissionUrl":"https://submission.springernature.com/new-submission/41699/3","title":"npj 2D Materials and Applications","twitterHandle":"","acdcEnabled":true,"dfaEnabled":true,"editorialSystem":"stoa","reportingPortfolio":"NPJ","inReviewEnabled":true,"inReviewRevisionsEnabled":true},"keywords":"ML MoS2, field-effect transistors, interface trap density, subthreshold slope, Schottky barrier height, TCAD","lastPublishedDoi":"10.21203/rs.3.rs-5897670/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-5897670/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eUnderstanding the interfaces between a contact metal and a two-dimensional (2D) semiconductor as well as the dielectric gate stack and the same 2D material in transition metal dichalcogenide (TMD) based transistors is a crucial step towards the introduction of TMD materials into advanced logic nodes. In particular, for the contact metal/2D interface, one of the key parameters is the Schottky barrier height (SBH), which is frequently extracted based on temperature-dependent subthreshold characteristics of TMD field-effect transistors (FETs). However, recently, using this methodology has resulted in rather low extracted SBH values for TMD based transistors, which seems inconsistent with the low on-current levels in said devices. Here, we therefore connect measured device characteristics on monolayer (ML) MoS\u003csub\u003e2\u003c/sub\u003e transistors with technology computer-aided design (TCAD) simulations. In particular, our analysis shows that low SBHs can incorrectly be extracted when the interface trap density D\u003csub\u003eit\u003c/sub\u003e is substantial and exhibits at the same time a significant temperature dependence as is the case for TMDs. In fact, TCAD simulations and comparison with the obtained electrical data reveals that the actual SBH is substantially larger than what is extracted when ignoring the above mentioned details of D\u003csub\u003eit\u003c/sub\u003e.\u003c/p\u003e","manuscriptTitle":"Interface trap states induced underestimation of Schottky barrier height in Metal-MX2 Junctions","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2025-02-04 09:03:18","doi":"10.21203/rs.3.rs-5897670/v1","editorialEvents":[{"type":"communityComments","content":0},{"type":"decision","content":"Revision requested","date":"2025-04-02T08:53:30+00:00","index":"","fulltext":""},{"type":"editorInvitedReview","content":"","date":"2025-03-16T13:24:55+00:00","index":"hide","fulltext":""},{"type":"editorInvitedReview","content":"","date":"2025-03-13T03:22:36+00:00","index":"hide","fulltext":""},{"type":"reviewerAgreed","content":"322633619720905834234113707057093954805","date":"2025-02-24T20:09:48+00:00","index":"hide","fulltext":""},{"type":"reviewerAgreed","content":"284241726854224067430212505968736256741","date":"2025-02-20T19:20:17+00:00","index":"hide","fulltext":""},{"type":"reviewerAgreed","content":"6726689300860535832504141825235730425","date":"2025-02-18T18:02:19+00:00","index":"hide","fulltext":""},{"type":"reviewersInvited","content":"","date":"2025-02-18T17:07:36+00:00","index":"","fulltext":""},{"type":"editorAssigned","content":"","date":"2025-02-18T15:04:55+00:00","index":"","fulltext":""},{"type":"checksComplete","content":"","date":"2025-01-31T12:49:50+00:00","index":"","fulltext":""},{"type":"submitted","content":"npj 2D Materials and Applications","date":"2025-01-24T18:05:34+00:00","index":"","fulltext":""}],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"npj-2d-materials-and-applications","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":false,"externalIdentity":"npj2dmaterials","sideBox":"Learn more about [npj 2D Materials and Applications](http://www.nature.com/npj2dmaterials/)","snPcode":"41699","submissionUrl":"https://submission.springernature.com/new-submission/41699/3","title":"npj 2D Materials and Applications","twitterHandle":"","acdcEnabled":true,"dfaEnabled":true,"editorialSystem":"stoa","reportingPortfolio":"NPJ","inReviewEnabled":true,"inReviewRevisionsEnabled":true}}],"origin":"","ownerIdentity":"dbc7bb59-6190-405d-be9d-a03c43dc2c32","owner":[],"postedDate":"February 4th, 2025","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"published-in-journal","subjectAreas":[{"id":43781768,"name":"Physical sciences/Nanoscience and technology/Nanoscale devices"},{"id":43781769,"name":"Physical sciences/Nanoscience and technology/Nanoscale materials"},{"id":43781770,"name":"Physical sciences/Physics/Electronics photonics and device physics"}],"tags":[],"updatedAt":"2025-07-07T16:08:01+00:00","versionOfRecord":{"articleIdentity":"rs-5897670","link":"https://doi.org/10.1038/s41699-025-00576-y","journal":{"identity":"npj-2d-materials-and-applications","isVorOnly":false,"title":"npj 2D Materials and Applications"},"publishedOn":"2025-07-01 15:58:34","publishedOnDateReadable":"July 1st, 2025"},"versionCreatedAt":"2025-02-04 09:03:18","video":"","vorDoi":"10.1038/s41699-025-00576-y","vorDoiUrl":"https://doi.org/10.1038/s41699-025-00576-y","workflowStages":[]},"version":"v1","identity":"rs-5897670","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-5897670","identity":"rs-5897670","version":["v1"]},"buildId":"8U1c8b4HqxoKbykW_rLl7","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}