Design Method for Unbalanced Ternary Logic Family Based on Binary Memristors

Design Method for Unbalanced Ternary Logic Family Based on Binary Memristors | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Design Method for Unbalanced Ternary Logic Family Based on Binary Memristors Xiaoyuan Wang, Yingfei Sun, Jiawei Zhou, Xinhui Chen, Sung Mo Kang, and 1 more This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-3593161/v1 This work is licensed under a CC BY 4.0 License Status: Published Journal Publication published 14 Mar, 2024 Read the published version in Nonlinear Dynamics → Version 1 posted 5 You are reading this latest preprint version Abstract This paper proposes a design method for unbalanced ternary logic family based on hybrid design of binary memristors and CMOS transistors, building on the foundational positive ternary logic circuits. By using the symmetry of negative and positive ternary logics, negative ternary TAND, TOR, TI, 1-3 decoder and 2-9 decoder are derived from the previously designed positive ternary basic logic gate circuits. Furthermore, negative ternary XOR, XNOR, 3-1 encoder, and 9-2 encoder are design-improved. For the first time, unbalanced ternary priority encoders is proposed, including a 3-1 priority encoder and a 9-2 priority encoder，of which the former is implemented with only 7 memristors. The functionalities of these circuits are demonstrated through LTSpice simulations. Finally, hardware experiments were performed on a stable 20×20 ZnO-based resistive switch array. Subsequent design of more complex digital logic circuits can benefit from this work. Memristor Binary memristor Decoder Priority encoder Multi-valued logic Ternary logic Full Text Cite Share Download PDF Status: Published Journal Publication published 14 Mar, 2024 Read the published version in Nonlinear Dynamics → Version 1 posted Editorial decision: Minor revisions 21 Dec, 2023 Reviewers agreed at journal 17 Nov, 2023 Reviewers invited by journal 16 Nov, 2023 Editor assigned by journal 09 Nov, 2023 First submitted to journal 08 Nov, 2023 You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. 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Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-3593161","acceptedTermsAndConditions":true,"allowDirectSubmit":false,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":250318379,"identity":"20022b16-e58b-45c4-9f5b-eca3583b5897","order_by":0,"name":"Xiaoyuan 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