Robust and Compact Reversible Logic Gate for Low-Power and High-Performance Computing

Robust and Compact Reversible Logic Gate for Low-Power and High-Performance Computing | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Robust and Compact Reversible Logic Gate for Low-Power and High-Performance Computing Anju Rajput, Renu Kumawat, Avireni Srinivasulu, Jyoti Sharma This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-7090231/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract Reversible logic is a design paradigm suitable to energy-efficient digital systems and has lately received recognition as a viable option for designing sophisticated digital applications. It possesses the capacity to revolutionize progress in quantum and low-power computing. This research presents an innovative reversible gate designed with merely 10 transistors. The suggested gate includes capabilities for several logic operations such as XOR, XNOR, NOT, NAND, NOR, and half-adder. This proposed design can attain a minimal quantum cost, which is strongly advocated in quantum computing. We have verified the design's resilience using Monte Carlo and process corner analysis after modeling it with Cadence Virtuoso at 45 nm technology and 1 V supply voltage. This confirms the robustness of the design amidst variation. In contrast to current reversible gates, the proposed structure achieves a 18% reduction in delay and a 12% reduction in power delay product, rendering it an appealing option for high-speed and low-energy circuit design. To illustrate its adaptability in alternative designs, we have utilized it to the construction of a 4-bit binary-to-Gray code converter circuit. Reversible logic quantum cost optimization energy efficient computing robust quantum compatible logic delay optimization Full Text Additional Declarations No competing interests reported. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-7090231","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":488671888,"identity":"1ff6760a-6558-4a77-ad14-66383193a968","order_by":0,"name":"Anju Rajput","email":"","orcid":"","institution":"Manipal University Jaipur","correspondingAuthor":false,"prefix":"","firstName":"Anju","middleName":"","lastName":"Rajput","suffix":""},{"id":488671889,"identity":"c64bbcc4-93e3-4379-959e-af02ecd8d0f6","order_by":1,"name":"Renu Kumawat","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAABOUlEQVRIie3RsUrDQBjA8S8GmuWTrjcEfIUUoWmp2AdxSQkky93QpYuCJ4G6ROe46CvUN2g5aJcQ10AFWwp16RAXqYNiatNCTairw/2XfBz5kbscgEz2b+tnzwQBN2vpoHKA0l6iXAW7RPmbeLi7XEzM65shgVCclQP7dXain+omYZOD+OJZN7UBh6QjfhM9jBwCsWBB7FQ8ijbWA9dQ6XCOdb/FlSDKEUJolUAiGB9bK6KiETug0pJAo9/i6mE3T44Wa/Iwdt+8Gl5m5CslT1OufhYQgtWfjfXGtOIBijVh3dWQfkUpIEiPa1bosseXRfvOx1F6hDkIdivSQ035wI/cHNHCSpwMG+w+HPWSD/+8aWqOMqPvommW7cFk2Wnk/vIqa3sRPoAB2T1th/0t12/ChshkMpks7RvGdXSURafhawAAAABJRU5ErkJggg==","orcid":"","institution":"Manipal University Jaipur","correspondingAuthor":true,"prefix":"","firstName":"Renu","middleName":"","lastName":"Kumawat","suffix":""},{"id":488671890,"identity":"f09d6ea0-1939-414d-a32b-6b9e5098a8a2","order_by":2,"name":"Avireni Srinivasulu","email":"","orcid":"","institution":"Mohan Babu University","correspondingAuthor":false,"prefix":"","firstName":"Avireni","middleName":"","lastName":"Srinivasulu","suffix":""},{"id":488671891,"identity":"bf6ec287-d461-4235-9b3e-5fa4045cd6e1","order_by":3,"name":"Jyoti Sharma","email":"","orcid":"","institution":"Birla Institute of Technology Mesra, Off Campus Jaipur","correspondingAuthor":false,"prefix":"","firstName":"Jyoti","middleName":"","lastName":"Sharma","suffix":""}],"badges":[],"createdAt":"2025-07-10 07:38:30","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-7090231/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-7090231/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":91821667,"identity":"88bd1c9e-5148-45a6-988e-d3a814e5dad5","added_by":"auto","created_at":"2025-09-22 07:31:16","extension":"pdf","order_by":1,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":674743,"visible":true,"origin":"","legend":"","description":"","filename":"ReversibleCircuits2.pdf","url":"https://assets-eu.researchsquare.com/files/rs-7090231/v1_covered_0399575d-5bb7-417a-8b6d-7a49999f25a6.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"Robust and Compact Reversible Logic Gate for Low-Power and High-Performance Computing","fulltext":[],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":false,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":true,"highlight":"","institution":"","isAcceptedByJournal":false,"isAuthorSuppliedPdf":true,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":true,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"Reversible logic, quantum cost optimization, energy efficient computing, robust, quantum compatible logic, delay optimization","lastPublishedDoi":"10.21203/rs.3.rs-7090231/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-7090231/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"Reversible logic is a design paradigm suitable to energy-efficient digital systems and has lately received recognition as a viable option for designing sophisticated digital applications. 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