Enhancing Computational Speed and Accuracy in Circuit Design Calculations using ANN
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This paper presents an ANN-based method for modeling and optimizing 65nm D-Latch design, achieving over 100x speed improvement and optimized performance metrics compared to traditional methods.
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This preprint studied how to model, design, and optimize a 65 nm D-Latch positive-edge-triggered latch for performance metrics affecting digital circuit power and timing, using transistor-level simulation data to train artificial neural networks (ANNs). The authors report that ANN-based models generated from the training data enable calculation and optimization that are more than 100 times faster than traditional methods, and they use the models to optimize setup time and propagation delay (data to output). A major stated limitation is that the approach’s speed and accuracy depend on transistor-level training data and model generation, rather than any explicit analytical derivations, though it is positioned as adaptable even without analytical formulas. This paper does not explicitly discuss endometriosis or adenomyosis; it was included in the corpus via a keyword match in the upstream search index.
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Abstract
Abstract The efficiency of Latch design and optimization plays a crucial role in shaping the overall performance of digital circuits, impacting power consumption and timing within emerging system-on-chip (SOC) archi-tectures. This paper introduces a methodology for modeling, designing, and optimizing 65nm D-Latch positive-edge-triggered Latch. Leveraging an Arti-ficial neural network (ANN)-based optimization ap-proach, an accurate model is first generated for vari-ous performance metrics using training data acquired from transistor-level models, which surpass tradi-tional methods by over 100 times in speed. Sub-sequently, these precise ANN-based models are em-ployed to optimize design objectives such as setup time, and propagation delay (Data to Output). The utilization of these swift and precise models markedly expedites the design process and yields significantly optimized outcomes. Furthermore, given the ANN’s capacity as a universal approximator capable of cap-turing any nonlinear input-output relationship, the proposed method is adaptable to optimizing circuits for diverse performance metrics, even in the absence of analytical formulas. Additionally, the automation of circuit design through the proposed method sim-plifies the tasks of circuit designers.
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Enhancing Computational Speed and Accuracy in Circuit Design Calculations using ANN | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Enhancing Computational Speed and Accuracy in Circuit Design Calculations using ANN Keshav Mohan, Lokesh Gautam, Aryan Chaudhary, Ansh Jindal This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-4425104/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract The efficiency of Latch design and optimization plays a crucial role in shaping the overall performance of digital circuits, impacting power consumption and timing within emerging system-on-chip (SOC) archi-tectures. This paper introduces a methodology for modeling, designing, and optimizing 65nm D-Latch positive-edge-triggered Latch. Leveraging an Arti-ficial neural network (ANN)-based optimization ap-proach, an accurate model is first generated for vari-ous performance metrics using training data acquired from transistor-level models, which surpass tradi-tional methods by over 100 times in speed. Sub-sequently, these precise ANN-based models are em-ployed to optimize design objectives such as setup time, and propagation delay (Data to Output). The utilization of these swift and precise models markedly expedites the design process and yields significantly optimized outcomes. Furthermore, given the ANN’s capacity as a universal approximator capable of cap-turing any nonlinear input-output relationship, the proposed method is adaptable to optimizing circuits for diverse performance metrics, even in the absence of analytical formulas. Additionally, the automation of circuit design through the proposed method sim-plifies the tasks of circuit designers. Artificial Intelligence and Machine Learning Latch Design Efficiency Optimization Methodology Artificial Neural Network (ANN) Architecture Performance Metric Modeling Full Text Additional Declarations The authors declare no competing interests. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. 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