Power Efficient and Improved Noise Margin of Sram Cell for System on Chip Applications

Noise margin analysis of SRAM cell is became more crucial for on chip applications. Currently the technology is migrating towards less than 10nm node and hence it is necessary to measure the noise margin of SRAM cell very effectively, since memory is one of the major part of system on chips (SOCs) and Network on chips (NOCs) devices. If the margin is not calculated efficiently then it may leads to bad chip product and the whole device which contains this chip may not work as per the expectation. This further leads to low yield which increases the number of defective chips compared to good one. In this paper the noise margin analysis of SRAM cell is performed using 7nm process technology node using HSPICE simulator.