A Wide Tuning Range High Performance PLL Based on Capacitor Arrays

A Wide Tuning Range High Performance PLL Based on Capacitor Arrays | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Article A Wide Tuning Range High Performance PLL Based on Capacitor Arrays Jun Liu, Qian Ma, Ning Ning, Chao Li, Shibi Ma, Linqing Huang, and 1 more This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-4715413/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract The paper presents a wide tuning range high performance PLL, which is mainly used for high speed wideband clock signal generation to reduce the difficulty of providing high-speed input clocks externally. The circuit mainly consists of PFD, CP, VCO, DIVIDER and other units. It improves the phase noise of the VCO by reducing the VCO tuning gain, and uses a capacitor array to extend the output frequency range. The circuit is designed in a 28nm process and the output signals can work from 8GHz to 12GHz. The PLL is used as a sampling clock for the DAC. When the DAC outputs a 1.8GHz sine wave, the measured phase noise can reach -110dBc/Hz@100kHz offset. Physical sciences/Engineering/Electrical and electronic engineering Physical sciences/Engineering/Mechanical engineering PLL wide tuning range capacitor arrays Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 I. INTRODUCTION In electronic systems, especially in communication systems, electronic measurement, instrumentation and other fields, the quality of the clock directly affects the performance of the whole system. PLL can realize clock frequency doubling, phase tracking, clock recovery and other functions, and is a commonly used circuit for clock generation. Wide tuning range PLL can accurately lock and track the phase and frequency of the input signal over a wide frequency range, thus realizing more flexible and efficient frequency synthesis and control [1–7]. II. DESIGN OF THE WHOLE PLL STRUCTURE This wide tuning range PLL circuit is designed in a 28nm process and can output 8GHz ~ 12GHz signal. It mainly contains: PFD, CP, off-chip LPF, LC VCO, feedback frequency divider and other units, in which the VCO is designed with a band-selective Auto Frequency Calibration (AFC) algorithm to improve the performance of the phase-locked loop. The general block diagram of the circuit is shown in Fig. 1 . In Fig. 1 , the PFD outputs a pulse signal proportional to the phase difference between Fin and the feedback divider output signal Fdiv by comparing the phase difference of Fin and the feedback divider output signal Fdiv, and then this pulse signal serves as the control signal of the CP, which decides the CP to charge or discharge the LPF in the back stage. At the same time, the LPF converts the high-frequency current pulse signal into a low-frequency voltage signal FILT_FINE after filtering, and then this voltage signal controls the output frequency of the VCO, and finally, the output signal of the VCO is divided by the frequency divider of the feedback loop for 8*N frequency division, and then outputs the signal fdiv and serves as one of the input signals of the PFD, and finally, under the effect of the negative phase feedback in the loop, the PLL reaches a stabilized state and locked at the frequency: 8N*F in /M. III. DESIGN OF THE MAIN UNITS A. Phase Frequency Detector The Phase Frequency Detector(PFD) is used to detect the difference in phase and frequency between the reference signal and the frequency-divided feedback signal.The outputs of the PFD are UP and DOWN pulses, and the difference between the pulse widths of these two pulses is directly proportional to the difference in phase between REFCLK and FBCLK. It mainly consists of D flip-flops, NAND gate and programmable delay line as shown in Fig. 2. When the frequency of REFCLK is higher than FBCLK or the phase is ahead, the pulse width of UP signal will be larger than that of DOWN signal; when the frequency of REFCLK is lower than FBCLK or the phase is lagged, the pulse width of UP signal will be smaller than that of DOWN; when REFCLK and FBCLK are in the same frequency and the same phase, the pulse width of UP signal is equal to that of DOWN. The UP and DOWN waveforms in different cases are shown in Fig. 3. The purpose of the delay unit in the RESET signal path is to ensure the complete establishment of the UP and DOWN pulse waveforms when the phase difference is small, so that the charge/discharge switch of the CP unit does not turn on completely, thus avoiding the dead zone. The delay time should be considered as a compromise, if the delay time is too small, then the CP switch can not be fully opened; if the delay time is too large, then the CP conduction time is long, contributing to the current noise. B. Charge Pump The Charge Pump (CP) unit takes the UP and DOWN pulses generated by the PFD and converts them into current signals. The current switching and inflow/outflow are controlled by the UP and DOWN pulses.The CP unit mainly consists of a bias circuit, a current source, and a switch and an auxiliary op-amp, and the basic structure is shown in Fig. 4. The AMP1 and M1 circuits enable the M1 branch to generate bias currents related to the Ibias, where the Rcp resistance value is variable, thus realizing the adjustability of the charge pump current. The auxiliary op-amp AMP2 makes the V1 and V2 node voltages equal to avoid the channel length modulation effect that causes current bias. Rpmis and Rnmis resistance value is variable, in the calibration mode, the charge pump operating mode is shown in Fig. 5, at this time V1 = VDD/2, if you find that FILT_FINE is not equal to V1, then it means that there is a mismatch between the charge pump PMOS branch and the NMOS branch currents, and by adjusting the resistance value of Rpmis or Rnmis can be adjusted to the charge pump mismatch current. C. Voltage Controlled Oscillator The Voltage Controlled Oscillator(VCO) utilizes a standard LC resonant cavity, which consists of two differential inductors, two variable capacitor arrays, a switched capacitor array, and complementary NMOS and PMOS negative resistors. The variable capacitor array is controlled by the charge pump output voltage, which can make the frequency change continuously to realize the frequency fine tuning; the switched capacitor array is controlled by the AFC algorithm, which can carry out the frequency selection to realize the coarse tuning. The negative resistance can be used to offset the parasitic resistance in the LC oscillator to ensure the stability of the resonance. The circuit structure is shown in Fig. 6. The variable capacitor array is shown in Fig. 7, which is controlled by two control signals, SW1 and SW0 . When the control signal is 0, the MOS capacitors C1 and C2 are connected to VDD; when the control signal is 1, the MOS capacitor C1 is connected to the voltage FILT_FINE, and the finely tuned branch is on, and the MOS capacitor C2 is connected to the voltage FILT_COARSE, and the coarsely tuned branch is on. Among them, the size of coarse tuning branch MOS capacitor C2 is 8 times of fine tuning branch MOS capacitor C1. D. Feedback Frequency Divider The VCO output signal is divided and fed to the PFD, but since the VCO output signal frequency is very high, the frequency divider used in this paper is accomplished in two stages. The first stage is a high-speed prescaler circuit, as shown in Fig. 8, which is first divided into 2 by a D flip-flop, and then divided into 4 by two D flip-flops, thus constituting an 8-division circuit, and in order to meet the high-speed requirements, the D flip-flop is realized by a TSPC circuit. The second stage is a conventional integer frequency divider. Therefore, the frequency divider circuit in this paper is an 8*N times frequency divider. E. Digital Automatic Frequency Calibration In order to meet the wide tuning range, the VCO uses a capacitor array to realize multiple frequency tuning sub-bands to extend the output frequency coverage, so the PLL needs to quickly and accurately select the appropriate VCO frequency tuning sub-bands through the Auto Frequency Calibration (AFC) circuit. The analog loop then controls the tuning voltage of the VCO through its own negative phase feedback until the loop locks. The block diagram of AFC is shown in Fig. 9. The AFC algorithm uses the frequency comparison method to realize calibration by comparing the frequency of the output divider signal Fdiv and the reference signal Fin. Before digital calibration, it is necessary to disconnect the analog calibration loop, and at the same time, the tuning voltage of the VCO is set to a fixed value of Vref, the counter counts the frequency of Fdiv for a certain period of time, and then compares the counted value and the target counted value, and the control logic adjusts the VCO capacitance array control word according to the counting result to regulate the frequency of the VCO. F. Analog Calibration After the digital calibration finds the sub-band it also needs to be locked by analog calibration, the analog calibration loop is shown in Fig. 10. The PFD compares the phase information of Fin and Fdiv to control the CP charging and discharging, and the CP charging and discharging currents are converted to the fine-tuned voltage FILT_FINE through the LPF to regulate the frequency of the VCO until the phase alignment of the Fin and Fdiv frequencies are equal, then the PLL completes the locking, and the fine-tuned voltage FILT_FINE is kept unchanged. In addition, the inclusion of a coarse tuning loop consisting of a Gm-C integrator allows the fine tuning voltage FILT_FINE to be controlled at Vref during lock. For example, if FILT_FINE is greater than Vref, FILT_COARSE increases, the variable capacitor capacitance becomes smaller, Fdiv increases, the CP discharges, and FILT_FINE decreases until it decreases to Vref, and FILT_COARSE stabilizes. IV. SUMMARY This wide tuning range PLL circuit is designed in a 28nm process and the layout is shown in Fig. 11 . This wide tuning range PLL circuit is applied in a high-speed DAC for generating an internal sampling clock. The DAC works at 12 GSPS and outputs a 1.8 GHz sine wave, the measured phase noise can reach − 110dBc/Hz@100kHz offset. The results of the test phase noise are shown in Fig. 12 . Declarations Author Contribution Jun Liu wrote the main manuscript text, and all authors reviewed the manuscript. Acknowledgement The authors would like to acknowledge the contributions of Yi Ding, Jiandong Zang, Gang Li, Yidan Dai, and Lingrui Zhang. Data Availability The datasets used and/or analysed during the current study available from the corresponding author on reasonable request.• All data generated or analysed during this study are included in this published article. References Mark Ferriss et al., “An Integral Path Self-Calibration Scheme for a Dual-Loop PLL,” IEEE Journal of Solid-State Circuits, vol. 48, no.4, pp. 996-1008, April. 2013. Vamshi Manthena et al., “A 1.2V 2.4 GHz low spur CMOS PLL synthesizer with a gain boosted charge pump for a batteryless transceiver,” IEEE Symposium on Radio Frequency Integrated Technology (RFIT), Nov. 2012. A. Loke et al., “A versatile 90-nm CMOS charge-pump PLL for SerDes transmitter clocking,” IEEE Journal of Solid-State Circuits, vol. 41, no.8, pp. 1894-1907, Aug. 1998. Juan Xie et al., “A low power low phase noise dual-band multiphase VCO,” Journal of Microelectronics, vol. 43, no. 12, pp. 1016-1022, Dec. 2012. Sung-Geun Kim, Jinsoo Rhim, Dae-Hyun Kwon, Min-Hyeong Kim, “A Low-Voltage PLL With a Supply-Noise Compensated Feedforward Ring VCO,” IEEE Journals & Magazines, vol. 63, no. 6, pp. 548-552, 2016. Kwang-Chun Choi, Sung-Geun Kim, Seung-Woo Lee, Bhum-Cheol Lee, and Woo-Young Choi, “A 990uW 1.6-GHz PLL Based on a Novel Supply-Regulated Active Loop Filter VCO,” Journal of latex class files, vol. 6, no. 1, pp. 1-5, Jan 2007. M. Hufford, et al., “An improved wideband PLL with adaptive frequency response that tracks the reference,” IEEE Custom Integrated Circuits Conf., pp. 549–552, Sep. 2005. Additional Declarations No competing interests reported. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-4715413","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Article","associatedPublications":[],"authors":[{"id":334839623,"identity":"91bdeeab-a34f-43d9-97e8-e11d3f29671f","order_by":0,"name":"Jun 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DOWN\u003c/p\u003e","description":"","filename":"3.png","url":"https://assets-eu.researchsquare.com/files/rs-4715413/v1/11ef6c3a99728af46a6ec15b.png"},{"id":61867876,"identity":"503328d9-e73a-4495-b31f-202436e8dcf2","added_by":"auto","created_at":"2024-08-06 12:30:17","extension":"png","order_by":4,"title":"Figure 4","display":"","copyAsset":false,"role":"figure","size":24524,"visible":true,"origin":"","legend":"\u003cp\u003eSchematic of charge pump circuit\u003c/p\u003e","description":"","filename":"4.png","url":"https://assets-eu.researchsquare.com/files/rs-4715413/v1/331fdcf5ee6b5256d6db0526.png"},{"id":61867121,"identity":"b92a9762-047a-47d6-8552-40266484c52d","added_by":"auto","created_at":"2024-08-06 12:22:18","extension":"png","order_by":5,"title":"Figure 5","display":"","copyAsset":false,"role":"figure","size":20306,"visible":true,"origin":"","legend":"\u003cp\u003eCharge Pump Circuit Diagram in Calibration Mode\u003c/p\u003e","description":"","filename":"5.png","url":"https://assets-eu.researchsquare.com/files/rs-4715413/v1/c79b8f1e14abc1b6381f3a00.png"},{"id":61867115,"identity":"458ccbc7-0a2a-41d8-95ee-aee0a6f5f0a8","added_by":"auto","created_at":"2024-08-06 12:22:17","extension":"png","order_by":6,"title":"Figure 6","display":"","copyAsset":false,"role":"figure","size":25408,"visible":true,"origin":"","legend":"\u003cp\u003eLC VCO Circuit Diagram\u003c/p\u003e","description":"","filename":"6.png","url":"https://assets-eu.researchsquare.com/files/rs-4715413/v1/0a978aed67e434cac50ee0ef.png"},{"id":61867117,"identity":"f296d3c4-a0a3-469a-9389-f812d3fb89b9","added_by":"auto","created_at":"2024-08-06 12:22:17","extension":"png","order_by":7,"title":"Figure 7","display":"","copyAsset":false,"role":"figure","size":22079,"visible":true,"origin":"","legend":"\u003cp\u003eVariable Capacitor Array Circuit Diagram\u003c/p\u003e","description":"","filename":"7.png","url":"https://assets-eu.researchsquare.com/files/rs-4715413/v1/97a0f9511786852e49210d15.png"},{"id":61867112,"identity":"d4d740e2-67e1-47ab-ba38-c05a28bbc5d3","added_by":"auto","created_at":"2024-08-06 12:22:17","extension":"png","order_by":8,"title":"Figure 8","display":"","copyAsset":false,"role":"figure","size":13480,"visible":true,"origin":"","legend":"\u003cp\u003eHigh Speed Pre-Divided Circuit Diagram\u003c/p\u003e","description":"","filename":"8.png","url":"https://assets-eu.researchsquare.com/files/rs-4715413/v1/1212b3d53ac96044182cd67b.png"},{"id":61867116,"identity":"7dc13534-5087-4dbd-bae5-7cb5b0338749","added_by":"auto","created_at":"2024-08-06 12:22:17","extension":"png","order_by":9,"title":"Figure 9","display":"","copyAsset":false,"role":"figure","size":14999,"visible":true,"origin":"","legend":"\u003cp\u003eBlock diagram of AFC\u003c/p\u003e","description":"","filename":"9.png","url":"https://assets-eu.researchsquare.com/files/rs-4715413/v1/f2c6631dc46a48b5f450e194.png"},{"id":61867113,"identity":"5b1016ba-433b-4115-b2bf-360c48865bfa","added_by":"auto","created_at":"2024-08-06 12:22:17","extension":"png","order_by":10,"title":"Figure 10","display":"","copyAsset":false,"role":"figure","size":15341,"visible":true,"origin":"","legend":"\u003cp\u003eCircuit diagram of analog calibration loop\u003c/p\u003e","description":"","filename":"10.png","url":"https://assets-eu.researchsquare.com/files/rs-4715413/v1/aab1f771e1779f2ada743150.png"},{"id":61867118,"identity":"fed5baba-a877-4a59-8333-6da39d01dd57","added_by":"auto","created_at":"2024-08-06 12:22:17","extension":"png","order_by":11,"title":"Figure 11","display":"","copyAsset":false,"role":"figure","size":205388,"visible":true,"origin":"","legend":"\u003cp\u003eThe layout of the circuit\u003c/p\u003e","description":"","filename":"11.png","url":"https://assets-eu.researchsquare.com/files/rs-4715413/v1/fc584ec8c79beba1f9f5f7ea.png"},{"id":61867122,"identity":"fc7b7f3d-15c2-4872-93bc-22e2361f6c6e","added_by":"auto","created_at":"2024-08-06 12:22:20","extension":"png","order_by":12,"title":"Figure 12","display":"","copyAsset":false,"role":"figure","size":102796,"visible":true,"origin":"","legend":"\u003cp\u003eThe phase noise of the output waveform\u003c/p\u003e","description":"","filename":"12.png","url":"https://assets-eu.researchsquare.com/files/rs-4715413/v1/f5d41dc4f7f681afa702b394.png"},{"id":64214859,"identity":"67e0a19f-3335-46ee-b47c-e7ec915cbb81","added_by":"auto","created_at":"2024-09-10 09:05:53","extension":"pdf","order_by":0,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":609521,"visible":true,"origin":"","legend":"","description":"","filename":"manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-4715413/v1/002551dd-4946-4191-a661-212fc071fec6.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"A Wide Tuning Range High Performance PLL Based on Capacitor Arrays","fulltext":[{"header":"I.\tINTRODUCTION ","content":"\u003cp\u003eIn electronic systems, especially in communication systems, electronic measurement, instrumentation and other fields, the quality of the clock directly affects the performance of the whole system. PLL can realize clock frequency doubling, phase tracking, clock recovery and other functions, and is a commonly used circuit for clock generation. Wide tuning range PLL can accurately lock and track the phase and frequency of the input signal over a wide frequency range, thus realizing more flexible and efficient frequency synthesis and control [1\u0026ndash;7].\u003c/p\u003e"},{"header":"II.\tDESIGN OF THE WHOLE PLL STRUCTURE","content":"\u003cp\u003eThis wide tuning range PLL circuit is designed in a 28nm process and can output 8GHz\u0026thinsp;~\u0026thinsp;12GHz signal. It mainly contains: PFD, CP, off-chip LPF, LC VCO, feedback frequency divider and other units, in which the VCO is designed with a band-selective Auto Frequency Calibration (AFC) algorithm to improve the performance of the phase-locked loop. The general block diagram of the circuit is shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003e.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eIn Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003e, the PFD outputs a pulse signal proportional to the phase difference between Fin and the feedback divider output signal Fdiv by comparing the phase difference of Fin and the feedback divider output signal Fdiv, and then this pulse signal serves as the control signal of the CP, which decides the CP to charge or discharge the LPF in the back stage. At the same time, the LPF converts the high-frequency current pulse signal into a low-frequency voltage signal FILT_FINE after filtering, and then this voltage signal controls the output frequency of the VCO, and finally, the output signal of the VCO is divided by the frequency divider of the feedback loop for 8*N frequency division, and then outputs the signal fdiv and serves as one of the input signals of the PFD, and finally, under the effect of the negative phase feedback in the loop, the PLL reaches a stabilized state and locked at the frequency: 8N*F\u003csub\u003ein\u003c/sub\u003e/M.\u003c/p\u003e"},{"header":"III. DESIGN OF THE MAIN UNITS","content":"\u003cp\u003eA. \u003cem\u003ePhase Frequency Detector\u003c/em\u003e\u003c/p\u003e\n\u003cp\u003eThe Phase Frequency Detector(PFD) is used to detect the difference in phase and frequency between the reference signal and the frequency-divided feedback signal.The outputs of the PFD are UP and DOWN pulses, and the difference between the pulse widths of these two pulses is directly proportional to the difference in phase between REFCLK and FBCLK. It mainly consists of D flip-flops, NAND gate and programmable delay line as shown in Fig.\u0026nbsp;2.\u003c/p\u003e\n\u003cp\u003eWhen the frequency of REFCLK is higher than FBCLK or the phase is ahead, the pulse width of UP signal will be larger than that of DOWN signal; when the frequency of REFCLK is lower than FBCLK or the phase is lagged, the pulse width of UP signal will be smaller than that of DOWN; when REFCLK and FBCLK are in the same frequency and the same phase, the pulse width of UP signal is equal to that of DOWN. The UP and DOWN waveforms in different cases are shown in Fig.\u0026nbsp;3.\u003c/p\u003e\n\u003cp\u003eThe purpose of the delay unit in the RESET signal path is to ensure the complete establishment of the UP and DOWN pulse waveforms when the phase difference is small, so that the charge/discharge switch of the CP unit does not turn on completely, thus avoiding the dead zone. The delay time should be considered as a compromise, if the delay time is too small, then the CP switch can not be fully opened; if the delay time is too large, then the CP conduction time is long, contributing to the current noise.\u003c/p\u003e\n\u003cp\u003eB. \u003cem\u003eCharge Pump\u003c/em\u003e\u003c/p\u003e\n\u003cp\u003eThe Charge Pump (CP) unit takes the UP and DOWN pulses generated by the PFD and converts them into current signals. The current switching and inflow/outflow are controlled by the UP and DOWN pulses.The CP unit mainly consists of a bias circuit, a current source, and a switch and an auxiliary op-amp, and the basic structure is shown in Fig.\u0026nbsp;4.\u003c/p\u003e\n\u003cp\u003eThe AMP1 and M1 circuits enable the M1 branch to generate bias currents related to the Ibias, where the Rcp resistance value is variable, thus realizing the adjustability of the charge pump current. The auxiliary op-amp AMP2 makes the V1 and V2 node voltages equal to avoid the channel length modulation effect that causes current bias.\u003c/p\u003e\n\u003cp\u003eRpmis and Rnmis resistance value is variable, in the calibration mode, the charge pump operating mode is shown in Fig.\u0026nbsp;5, at this time V1 = VDD/2, if you find that FILT_FINE is not equal to V1, then it means that there is a mismatch between the charge pump PMOS branch and the NMOS branch currents, and by adjusting the resistance value of Rpmis or Rnmis can be adjusted to the charge pump mismatch current.\u003c/p\u003e\n\u003cp\u003eC. \u003cem\u003eVoltage Controlled Oscillator\u003c/em\u003e\u003c/p\u003e\n\u003cp\u003eThe Voltage Controlled Oscillator(VCO) utilizes a standard LC resonant cavity, which consists of two differential inductors, two variable capacitor arrays, a switched capacitor array, and complementary NMOS and PMOS negative resistors. The variable capacitor array is controlled by the charge pump output voltage, which can make the frequency change continuously to realize the frequency fine tuning; the switched capacitor array is controlled by the AFC algorithm, which can carry out the frequency selection to realize the coarse tuning. The negative resistance can be used to offset the parasitic resistance in the LC oscillator to ensure the stability of the resonance. The circuit structure is shown in Fig.\u0026nbsp;6.\u003c/p\u003e\n\u003cp\u003eThe variable capacitor array is shown in Fig.\u0026nbsp;7, which is controlled by two control signals, SW1 \u0026lt; 3:0 \u0026gt; and SW0 \u0026lt; 3:0\u0026gt;. When the control signal is 0, the MOS capacitors C1 and C2 are connected to VDD; when the control signal is 1, the MOS capacitor C1 is connected to the voltage FILT_FINE, and the finely tuned branch is on, and the MOS capacitor C2 is connected to the voltage FILT_COARSE, and the coarsely tuned branch is on. Among them, the size of coarse tuning branch MOS capacitor C2 is 8 times of fine tuning branch MOS capacitor C1.\u003c/p\u003e\n\u003cp\u003eD. \u003cem\u003eFeedback Frequency Divider\u003c/em\u003e\u003c/p\u003e\n\u003cp\u003eThe VCO output signal is divided and fed to the PFD, but since the VCO output signal frequency is very high, the frequency divider used in this paper is accomplished in two stages. The first stage is a high-speed prescaler circuit, as shown in Fig.\u0026nbsp;8, which is first divided into 2 by a D flip-flop, and then divided into 4 by two D flip-flops, thus constituting an 8-division circuit, and in order to meet the high-speed requirements, the D flip-flop is realized by a TSPC circuit. The second stage is a conventional integer frequency divider. Therefore, the frequency divider circuit in this paper is an 8*N times frequency divider.\u003c/p\u003e\n\u003cp\u003eE. \u003cem\u003eDigital Automatic Frequency Calibration\u003c/em\u003e\u003c/p\u003e\n\u003cp\u003eIn order to meet the wide tuning range, the VCO uses a capacitor array to realize multiple frequency tuning sub-bands to extend the output frequency coverage, so the PLL needs to quickly and accurately select the appropriate VCO frequency tuning sub-bands through the Auto Frequency Calibration (AFC) circuit. The analog loop then controls the tuning voltage of the VCO through its own negative phase feedback until the loop locks. The block diagram of AFC is shown in Fig.\u0026nbsp;9.\u003c/p\u003e\n\u003cp\u003eThe AFC algorithm uses the frequency comparison method to realize calibration by comparing the frequency of the output divider signal Fdiv and the reference signal Fin. Before digital calibration, it is necessary to disconnect the analog calibration loop, and at the same time, the tuning voltage of the VCO is set to a fixed value of Vref, the counter counts the frequency of Fdiv for a certain period of time, and then compares the counted value and the target counted value, and the control logic adjusts the VCO capacitance array control word according to the counting result to regulate the frequency of the VCO.\u003c/p\u003e\n\u003cp\u003eF. \u003cem\u003eAnalog Calibration\u003c/em\u003e\u003c/p\u003e\n\u003cp\u003eAfter the digital calibration finds the sub-band it also needs to be locked by analog calibration, the analog calibration loop is shown in Fig.\u0026nbsp;10.\u003c/p\u003e\n\u003cp\u003eThe PFD compares the phase information of Fin and Fdiv to control the CP charging and discharging, and the CP charging and discharging currents are converted to the fine-tuned voltage FILT_FINE through the LPF to regulate the frequency of the VCO until the phase alignment of the Fin and Fdiv frequencies are equal, then the PLL completes the locking, and the fine-tuned voltage FILT_FINE is kept unchanged. In addition, the inclusion of a coarse tuning loop consisting of a Gm-C integrator allows the fine tuning voltage FILT_FINE to be controlled at Vref during lock. For example, if FILT_FINE is greater than Vref, FILT_COARSE increases, the variable capacitor capacitance becomes smaller, Fdiv increases, the CP discharges, and FILT_FINE decreases until it decreases to Vref, and FILT_COARSE stabilizes.\u003c/p\u003e"},{"header":"IV. SUMMARY","content":"\u003cp\u003eThis wide tuning range PLL circuit is designed in a 28nm process and the layout is shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig11\" class=\"InternalRef\"\u003e11\u003c/span\u003e.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eThis wide tuning range PLL circuit is applied in a high-speed DAC for generating an internal sampling clock. The DAC works at 12 GSPS and outputs a 1.8 GHz sine wave, the measured phase noise can reach \u0026minus;\u0026thinsp;110dBc/Hz@100kHz offset. The results of the test phase noise are shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig12\" class=\"InternalRef\"\u003e12\u003c/span\u003e.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e"},{"header":"Declarations","content":"\u003ch2\u003eAuthor Contribution\u003c/h2\u003e\u003cp\u003eJun Liu wrote the main manuscript text, and all authors reviewed the manuscript.\u003c/p\u003e\u003ch2\u003eAcknowledgement\u003c/h2\u003e\u003cp\u003eThe authors would like to acknowledge the contributions of Yi Ding, Jiandong Zang, Gang Li, Yidan Dai, and Lingrui Zhang.\u003c/p\u003e\u003ch2\u003eData Availability\u003c/h2\u003e\u003cp\u003eThe datasets used and/or analysed during the current study available from the corresponding author on reasonable request.\u0026bull; All data generated or analysed during this study are included in this published article.\u003c/p\u003e"},{"header":"References","content":"\u003col\u003e\n \u003cli\u003eMark Ferriss et al., \u0026ldquo;An Integral Path Self-Calibration Scheme for a Dual-Loop PLL,\u0026rdquo; IEEE Journal of Solid-State Circuits, vol. 48, no.4, pp. 996-1008, April. 2013.\u003c/li\u003e\n \u003cli\u003eVamshi Manthena et al., \u0026ldquo;A 1.2V 2.4 GHz low spur CMOS PLL synthesizer with a gain boosted charge pump for a batteryless transceiver,\u0026rdquo; IEEE Symposium on Radio Frequency Integrated Technology (RFIT), Nov. 2012.\u003c/li\u003e\n \u003cli\u003eA. Loke et al., \u0026ldquo;A versatile 90-nm CMOS charge-pump PLL for SerDes transmitter clocking,\u0026rdquo; IEEE Journal of Solid-State Circuits, vol. 41, no.8, pp. 1894-1907, Aug. 1998.\u003c/li\u003e\n \u003cli\u003eJuan Xie et al., \u0026ldquo;A low power low phase noise dual-band multiphase VCO,\u0026rdquo; Journal of Microelectronics, vol. 43, no. 12, pp. 1016-1022, Dec. 2012.\u003c/li\u003e\n \u003cli\u003eSung-Geun Kim, Jinsoo Rhim, Dae-Hyun Kwon, Min-Hyeong Kim, \u0026ldquo;A Low-Voltage PLL With a Supply-Noise Compensated Feedforward Ring VCO,\u0026rdquo; IEEE Journals \u0026amp; Magazines, vol. 63, no. 6, pp. 548-552, 2016.\u003c/li\u003e\n \u003cli\u003eKwang-Chun Choi, Sung-Geun Kim, Seung-Woo Lee, Bhum-Cheol Lee, and Woo-Young Choi, \u0026ldquo;A 990uW 1.6-GHz PLL Based on a Novel Supply-Regulated Active Loop Filter VCO,\u0026rdquo; Journal of latex class files, vol. 6, no. 1, pp. 1-5, Jan 2007.\u003c/li\u003e\n \u003cli\u003eM. Hufford, et al., \u0026ldquo;An improved wideband PLL with adaptive frequency response that tracks the reference,\u0026rdquo; IEEE Custom Integrated Circuits Conf., pp. 549\u0026ndash;552, Sep. 2005.\u003cstrong\u003e\u003cbr\u003e\u0026nbsp;\u003c/strong\u003e\u003c/li\u003e\n\u003c/ol\u003e"}],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":true,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":true,"highlight":"","institution":"","isAcceptedByJournal":false,"isAuthorSuppliedPdf":false,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":false,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"PLL, wide tuning range, capacitor arrays","lastPublishedDoi":"10.21203/rs.3.rs-4715413/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-4715413/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eThe paper presents a wide tuning range high performance PLL, which is mainly used for high speed wideband clock signal generation to reduce the difficulty of providing high-speed input clocks externally. The circuit mainly consists of PFD, CP, VCO, DIVIDER and other units. It improves the phase noise of the VCO by reducing the VCO tuning gain, and uses a capacitor array to extend the output frequency range. The circuit is designed in a 28nm process and the output signals can work from 8GHz to 12GHz. The PLL is used as a sampling clock for the DAC. When the DAC outputs a 1.8GHz sine wave, the measured phase noise can reach -110dBc/Hz@100kHz offset.\u003c/p\u003e","manuscriptTitle":"A Wide Tuning Range High Performance PLL Based on Capacitor Arrays","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2024-08-06 12:22:12","doi":"10.21203/rs.3.rs-4715413/v1","editorialEvents":[{"type":"communityComments","content":0}],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true}}],"origin":"","ownerIdentity":"3c327553-7a4a-446f-995a-6be681e89fee","owner":[],"postedDate":"August 6th, 2024","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"posted","subjectAreas":[{"id":35460785,"name":"Physical sciences/Engineering/Electrical and electronic engineering"},{"id":35460786,"name":"Physical sciences/Engineering/Mechanical engineering"}],"tags":[],"updatedAt":"2024-09-10T08:57:46+00:00","versionOfRecord":[],"versionCreatedAt":"2024-08-06 12:22:12","video":"","vorDoi":"","vorDoiUrl":"","workflowStages":[]},"version":"v1","identity":"rs-4715413","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-4715413","identity":"rs-4715413","version":["v1"]},"buildId":"qtupq5eGEP_6zYnWcrvyt","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}