Implementation Of Two Cross Two Switch To Implement Bitonic Sorting Circuit

Reversible logic synthesis is becoming a significant research component for post-CMOS computing devices, particularly quantum computing. In this work we connect the reversible logic synthesis problem to sorting algorithms. Reversible logic has emerged as a promising technology in recent years, with applications in low power CMOS, quantum computing, nanotechnology, and optical computing. The classical gates AND, OR, and XOR are not reversible. This paper employs the control swap gate to implement a 2x2 switch. In multiprocessor system different computing operations are performed concurrently to get higher throughput. Sorting network can be used to tie up different parts of a large complex system efficiently with least amount of hardware to perform concurrent operations. A sorting network can be built using a multiple input and multiple output switching network. Following the implementation of the 2x2 switch, a bitonic sorting circuit is designed. The goal of developing a reversible sorting circuit is to reduce power consumption while maintaining reliable communication. The bitonic sorting circuit was successfully implemented, and the output was simulated in IBM qiskit. This presents efficient sorting circuit that can sort binary numbers in ascending/descending order.