Reliability and Power Analysis of FinFET Based SRAM

Reliability and Power Analysis of FinFET Based SRAM | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Reliability and Power Analysis of FinFET Based SRAM Alluri Navaneetha, K. Bikshalu This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-759064/v1 This work is licensed under a CC BY 4.0 License Status: Under Review Version 1 posted 4 You are reading this latest preprint version Abstract Demand for accommodating more and new functionalities within a single chip such as SOC needs a novel devices and architecture such as FinFET device instead of MOSFET. FinFET is emerged as non-planar, multigate device to overcome short channel effects such as subthreshold swing deterioration, drain induced barrier lowering, threshold voltage roll off which degrade circuit performance. As the need of device technology is mounting in electronic gadgets the important parameters are taken into consideration such as low leakage, high reliability, low power dissipation, and high operating speed. Reliability is one of key considerations in converting a proof of concept into reality. In this work Reliability of FinFET device is studied experimentally according to ITRS (international technology roadmap for semiconductor) roadmap using several standard test protocols such as multiple current stressing, harsher environment conditions, and effect of electromigration. Furthermore, power analysis of FinFET based SRAM is done by using 7nm bsimcmg PTM files in mentor graphics tool. The FinFET based SRAM shown low leakage, power dissipation, delay compared to existing conventional MOSFET based SRAM. Electronic Materials and Devices Magnetics Materials and Devices MOSFET FinFET SRAM SOI SCE Reliability ITRS. Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 1. Introduction Electronic devices are in high demand in the electronics sector and are utilized in a variety of applications including automobiles, computing, communications, entertainment, artificial intelligence, neural networks, computer vision, big data, and many others [ 1 ], in which advanced nanodevice FinFET is used as a transistor instead of MOSFET to achieve high performance, low power dissipation, low area at reduced technology. Channel electrostatics is controlled by single gate MOSFET whereas control of channel in 3 directions to reduce short channel effects is achieved by 3 gate FinFET [ 2 , 3 ] For digital circuit, Mixed signal circuit, Analog/RF circuit, FinFET is emerged as superior device to get low power dissipation, high speed, low area at deep submicron range. FinFET can be fabricated in 2 ways one is SOI (silicon on insulator) and alternatively as BULK. Due to the presence of an insulating layer beneath oxide, SOI FinFETs with lower parasitic capacitance increases switching speed and reduces power consumption [ 4 ]. RF characteristics, Linearity, is achieved by spacer dielectric optimization. For nanoscale applications reduction of leakage is required which in turn reduces and improves system performance [ 4 ]. FinFET has well established structure and fabrication due to this TSMC and Intel manufacturing Industries made used from 2011 to till date at sub 22nm technology nodes [ 5 ]. SOI FinFET shows reduced device cross talk, lower junction leakage, fully dielectric isolation, lower junction leakage, reduced capacitance, nearly ideal subthreshold slope [ 6 – 8 ]. FinFET reduces short channel effects by wrapping gate over channel from four sides. Due to continuous scaling FinFET faces several challenges in terms of cost effective, patterning, layout, device performance [ 9 – 12 ]. Due to several advantages FinFET can be used in variety of application such as terrestrial systems, infrared detectors, space, satellite communication, nuclear reactor, military [ 12 – 13 ]. 2. Reliability Study of FinFET One of the most important factors to consider when turning a proof of concept into reality is reliability. It is critical to investigate the dependability of these surface passivation methods in more depth. The specific contact resistance is the most important factor in determining reliability. Under any adversity, the resistance values should not change dramatically. The ITRS (International Technology Roadmap for Semiconductors) developed a number of typical test techniques to ensure reliability. Multiple current stressing is a test that involves repeatedly passing a variable current of quite high amplitude through a test structure. There will be no major performance decrease in a trustworthy framework. Temperature cycling is another more rigorous reliability test that is performed on a regular basis. Repeating the numerous current stressing measurements at different temperatures is part of the experiment. -55°C to + 125°C is the standard temperature range. In order to ensure reliability, the test structure should be able to withstand these circumstances without degrading. Last but not least, the test structure should be exposed to a harsher environment to account for variability caused by differing storage circumstances. Over a lengthy period of time, the test structure is normally maintained in a high relative humidity environment (usually RH > 60%) and at a high temperature (> 100°C) (typically a week or more). To ensure trustworthiness, the repeat measurements should resemble those of the original measurements. Preparation of the substrate, Fin etch, oxide deposition, planarization, recess etch, gate oxide deposition, and ultimately gate deposition was used in the fabrication of the FinFET device. Figure 1 shows the TEM cross section of the fabricated FinFET device at 22nm CMOS technology node, whereas Fig. 2 shows the corresponding 3D FinFET device structure in Sentaurus Tcad simulation domain. Prior to go for reliability studies, fabricated FinFET device bonded with feeder lines (M1, M2) at low temperature (160 ºC) and low pressure (2.5 mbar) for Kelvin structure design [ 18 ], process flow is explained below. Figure 3 shows the cross-sectional TEM of bonded region of the feeder lines. Figure 4 shows the complete experimental process flow of reliability study of FinFET device. 2.1. Reliability assessment of the Fabricated FinFET using Multiple Current Stressing test For applications such as high-speed super-fast multi-core processor design, the electrical performance of the FinFET device is critical, especially when numerous operations are performed. As a result, the constructed Kelvin structure along with FinFET device (with M1,M2 feeders) was treated to 1000 cycles of current stress with magnitudes ranging from − 0.1 A to + 0.1 A. At room temperature, all measurements were made with a Keithley source measuring unit. Each 100 cycles, the specific resistance was measured. 2.2. Reliability assessment of the fabricated FinFET device using Temperature Cycling Test The thermal stability test, as per the JESD22-A104B standard, involves subjecting the FinFET device through feeder to 1000 cycles of current sweeping from − 0.1 A to + 0.1 A at various temperatures ranging from − 55 ⁰C to + 125 ⁰C. The resistance behavior of a FinFET device specimen pre and post temperature cycles is shown in Fig. 6 . It can be inferred from the figure that even at very high and very low temperature the fabricated FinFET device is reliable and there is no deprivation of the specific resistance. As a result, FinFET devices may be viable and efficient at both high and low temperatures. 2.3. Reliability assessment of the Fabricated FinFET structure under harsher environment conditions The specimens were maintained under harsher environment circumstances for 96 hours, with a high relative humidity (RH) of 65 percent and a high temperature of 130°C, in order to investigate the effect of tougher environmental condition on the produced FinFET. The data taken after this storage correlate extremely well to the ones taken before this retention, as shown in Fig. 7 . After such a lengthy period of exposure to harsher environmental results, it is clear that the unique resistance of both CMOS technology situations has not degraded. This shows that FinFET devices produced utilizing both CMOS and CMOS technology is more resistant to dampness and high temperatures. 2.4. Electromigration Assessment of the FinFET device post bonding During an EM test, four-point sensing is used to evaluate electrical resistance. As shown in Fig. 8 , resistance measurements taken during EM testing demonstrate a latency period during which the resistance remains unchanged, followed by a gradual and then rapid increase. 3. Static Random Access Memory (SRAM) Cache memory which is made of SRAM cell [9-11] occupies 50% of area in processor the leakage power due to cache memory in processor is the major source of power dissipation [12]. Now a days SRAM is operating in nanometer range in electronic gadgets so, the power dissipation in SRAM should be as low as possible in which leakage currents has to be less and speed should be more. Low power dissipation and more speed in SRAM is obtained by using advanced devices such as FinFET instead of MOSFET. To meet technology scaling new structure challenges have been proposed such as FinFET and Nanowire [13]. FinFET device attracted many SRAM designer’s as FinFET has superior short channel effects, reduced dopant fluctuations, independent gating, better subthreshold slope [13,14]. From device level to architecture level many FinFET based SRAM cells have been proposed [15-17]. The trend of SRAM along with CMOS technology scaling in different processors and SOC products has fuelled the need of innovation in the area of SRAM design. Simulation results are carried out for 7nm FinFET based SRAM to analyze the parameters for leakage power, delay and power dissipation which is compared with existing MOSFET device. 7nm FinFET based SRAM shown less leakage, low power, high speed compared to the existing MOSFET based SRAM device as shown in comparison table (Table-1). Schematic diagram of simulated FinFET based SRAM and simulation result shown in Fig. 9 and Fig. 10 respectively. Table 1. Comparison of parameters of 7nm FinFET based SRAM along with conventional MOSFET based SRAM. Parameter MOSFET FinFET Mode Write Read Write Read Technology 180nm 180nm 7nm 7nm Delay 143ps 974ps 96ps 603ps Leakage power 286nW 793nW 1.6nW 1.98nW Power Dissipation 1.50nW 618pW 787pW 397pW Conclusion Reliability assessment of the experimental FinFET device under 7nm and 22nm is demonstrated under various tests such as temperature cycling test, harsher environment condition, multiple current stress, the results shown that the device structure above to withstand under any circumstances without degrading to ensure reliability. The most important component to decrease or increase performance of system is SRAM memory which is used as cache memory in multiprocessor chip, requires low power dissipation, low leakages, high speed for the future IOT devices which connects nearly $50 billion devices in future. Analysis of leakage and power of SRAM is done using 7nm bsimcmg FinFET file in Mentor Graphic tool which show low power dissipation and high speed compared to the existing MOSFET at high technology node. Declarations Acknowledgements :- The authors are thankful to the Kakatiya University and Mahatma Gandhi Institute of technology for their co-operation and support during this research work. Author Contributions :-A.Navaneetha : Data Collection, Formal analysis,Simulation,original draft preparation,Dr.K.Bikshalu : Supervision,Conceptualization,methodology. Funding: No funding received Data Availability : Not applicable. Consent to Participate :Yes Consent for Publication :Yes Financial Interests : The authors declare they have no Financial interests. Conflict of Interest :The author has no conflicts of interest to declare that are relevant to the content of this article. Compliance with Ethical Standards : The contents of this manuscript are not now under consideration for publication elsewhere. The content of this manuscript have not been copyrighted or published previously. The contents of this manuscript will not be copyrighted, submitted or published elsewhere while acceptance by the journal is under consideration References 1.Sahay S,Kumar MJ(2019) Junctionless Field-effect transistors:design,modeling and simulation,Wiley,Hoboken. 2.Narendar V,Tripathi S,Naik RBS(2018) A two dimensional(2D) analytical modeling and improved short channel performance of Graded-Channel gate-stack(GCGS) dual-material double-gate(DMDG) MOSFET,Silicon 10(6):2399-2407 3.Nowak EJ,Aller I,Ludwig T,Keunwoo Kim,Joshi RV,Ching-te Chaung,Berstein K,Puri R(2004) Turning silicon on its edge double gate CMOS/FinFET technology,IEEE Circ Devices Mag20(1):20-31. 4.Sachid AB,Chen M, HuC(2017) Bulk FinFET with low-k spacers for continued scaling,IEEE Trans Electron Devices 64(4):1861-1864 5.Bharath Sreenivasulu,Narender Vadthiya Design and deep insights into sub 10nm spacer engineering Junctionless FinFET for Nanoscale applications,ECS journal of solid state science and technology 2021 10 013008. 6.E.Yu,K.Heo ,and S.Cho “Characterization and optimization of inverted-T FinFET under nanoscale dimensions”,IEEE Trans Electron Devices,65,3521(2018). 7.Nelapati RP,Sivasankaran S. Impact of self heating effect on the performance of hybrid FinFET, microelectron J 2018;76:63-8. 8.Moparthi S,Adarsh KP,Tiwari PK,Saramekala GK,Analog and RF performance evaluation of negative capacitance SOI junctionless transistor,AEU- Int J Electron Commun 2020;122:153243.https://doi.org//10.106/j.aeue.2020.153243. 9.Narendar V, etal.Investigation of short channel Effects(SCEs) and Analog/RF Figure of merits(FOMs) of dual Material bottom – Spacer Ground -Plane(DMBSGP].FinFET 2019;12:2283-91. 10.Tamersit k.Sub – 10nm junctionless carbon nanotube field – effect transistors with improved performance.AEU – Int J Electron Commun 2020;124:153354. https://dio.org/10.1016/j.aeue.2020.153354. 11.J.P.Colinge etal.,Junctionless transistors: Physics and properities.Semiconductor-on-Insulator Materials for Nanoelectronics Applications, Engineering Materials, New York,NY,USA :Springer -Verlag,2011,pp.187-200. 12.Colinge J-P,Lee C-W,Afzalian A,Akhavan ND,Yan R,Ferain I,et al .Nanowire Transistors without Junctions.Nat Nanotechnol 2010;5(3):225-9. 13.Vadthiya N,Narware P,Bheemudu V,Sunitha B.A novel bottom-spacer ground – plane(BSGP) FinFET for improved logic and analog/RF performance.AEU – Int J Electro Commun 2020;127:153459.https://doi.org/10.1016/j.aeue.2020.153459. 14.Dhanumjayal,M.Sudha,Dr.M.N.GiriPrasad,Dr.K.Padmaraju “Cell stability analysis of conventional 6T dynamic 8T SRAM cell in 45nm technology”, international journal of VLSI design and communication systems(VLSICs) Vol.3,No.2,April 2012. 15.J.Sallese,N.Chevillon,C.Lallement,B.Iniguez, and F.Pregaldiny,”Charge based modelling of Junctionless double gate Field Effect Trasnsistors”,IEEE Trans Electronic devices,58,2628(2011). 16.A.Carlson,Z.Guo,S.Balasubramanian,R.Zlatanovici,T.K.Liu,B.Nikolic,SRAM Read/Write margin enhancements using FinFETs,IEEE Trans Very Large Scale Integr,Syst.18(6) (June,2010) 887-900. 17.L.Baghriye,S.Toofan,R.Saeidi,F.Moradi,offset-Compensated high Speed Sense Amplifier for STT – MRAMs,IEEE Trans Very Large Scale Integr,June(2018),1051-1058. 18. A.K. Panigrahi, S. Bonam, T. Ghosh, S.G. Singh, and S.R.K. Vanjari, 2016. Ultra-thin Ti passivation mediated breakthrough in high quality Cu-Cu bonding at low temperature and pressure. Materials Letters, 169, pp.269-272. Cite Share Download PDF Status: Under Review Version 1 posted Reviews received at journal 29 Jul, 2021 Reviewers invited by journal 29 Jul, 2021 Editor assigned by journal 28 Jul, 2021 First submitted to journal 27 Jul, 2021 You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. 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Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-759064","acceptedTermsAndConditions":true,"allowDirectSubmit":false,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":42742872,"identity":"89c4c964-c549-4ce7-b22c-90b2eccf3070","order_by":0,"name":"Alluri Navaneetha","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAAA60lEQVRIiWNgGAWjYJACZiCW4QMSBz4ACTZ2wjoYm4EEDxuQODgDpIWZFC3MPDBL8QFz9ubjjwtq7HjYJHIfHrb5tU2ej5mB8cPHHNxaLHuOJTbPOJYM1JJucDi377ZhGzMDs+TMbbi1GNzIMWzmYWMGakljOJzbc5sRqIWNmReflvvvPzbz/KuHaLHsuW1PWMsNHsZm3rbDEC0MP24nEtZyJs1wNm/fcR42nmcMB3sbbie3MTM24/fL8cMPPvN8q5bjZ09j/vDjz23b+e3NBz98xKMFFTC2gckGYtWDwB9SFI+CUTAKRsFIAQCI/Es3abIBRgAAAABJRU5ErkJggg==","orcid":"","institution":"Mahatma Gandhi Institute of Technology","correspondingAuthor":true,"prefix":"","firstName":"Alluri","middleName":"","lastName":"Navaneetha","suffix":""},{"id":42742873,"identity":"f1f81888-20a8-40d6-b186-3db0c6b16c3c","order_by":1,"name":"K. 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decrease of contact resistance was found as shown in Fig. 5, indicating that the constructed FinFET device is trustworthy.","description":"","filename":"floatimage5.png","url":"https://assets-eu.researchsquare.com/files/rs-759064/v1/694fb726e82ac1fadf25f283.png"},{"id":12080948,"identity":"29cfc022-61cc-4cc3-9b5f-392fa8a9a02e","added_by":"auto","created_at":"2021-08-03 19:54:28","extension":"png","order_by":6,"title":"Figure 6","display":"","copyAsset":false,"role":"figure","size":102362,"visible":true,"origin":"","legend":"Electrical performance of Fabricated FinFET structure under temperature cycling test.","description":"","filename":"floatimage6.png","url":"https://assets-eu.researchsquare.com/files/rs-759064/v1/c16af0c3db613901f0371121.png"},{"id":12080944,"identity":"d4c5e3e6-d979-4c84-81cb-933c85369ad1","added_by":"auto","created_at":"2021-08-03 19:54:28","extension":"png","order_by":7,"title":"Figure 7","display":"","copyAsset":false,"role":"figure","size":103145,"visible":true,"origin":"","legend":"Electrical performance evaluation of the fabricated FinFET device at harsher environment condition.","description":"","filename":"floatimage7.png","url":"https://assets-eu.researchsquare.com/files/rs-759064/v1/5886102a864213bd42d50bff.png"},{"id":12081156,"identity":"50d790d1-3abe-4d89-8f76-0b7d9c206c13","added_by":"auto","created_at":"2021-08-03 19:57:28","extension":"png","order_by":8,"title":"Figure 8","display":"","copyAsset":false,"role":"figure","size":104372,"visible":true,"origin":"","legend":"Relative degradation plot of FinFET device under EM test.","description":"","filename":"floatimage8.png","url":"https://assets-eu.researchsquare.com/files/rs-759064/v1/e514f46d8706f8d045373081.png"},{"id":12081280,"identity":"885ae50f-a2e7-41e3-a7cf-467b0ff91b13","added_by":"auto","created_at":"2021-08-03 20:00:28","extension":"png","order_by":9,"title":"Figure 9","display":"","copyAsset":false,"role":"figure","size":14038,"visible":true,"origin":"","legend":"Schematic of FinFET based SRAM","description":"","filename":"floatimage9.png","url":"https://assets-eu.researchsquare.com/files/rs-759064/v1/75c768fb5255bcc7731e933e.png"},{"id":12080946,"identity":"7c0a0d27-ece6-481e-8988-c539c1f296d1","added_by":"auto","created_at":"2021-08-03 19:54:28","extension":"png","order_by":10,"title":"Figure 10","display":"","copyAsset":false,"role":"figure","size":22529,"visible":true,"origin":"","legend":"Simulation results of FinFET based SRAM","description":"","filename":"floatimage10.png","url":"https://assets-eu.researchsquare.com/files/rs-759064/v1/7f4a7663965d9d184cd9cb64.png"},{"id":13707223,"identity":"703e652f-ac15-4f59-9f67-1128fca5441e","added_by":"auto","created_at":"2021-09-17 14:01:44","extension":"pdf","order_by":0,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":1564043,"visible":true,"origin":"","legend":"","description":"","filename":"manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-759064/v1/a78616e9-bd58-48c2-a8d9-8fa32a4b88aa.pdf"}],"financialInterests":"","formattedTitle":"\u003cp\u003eReliability and Power Analysis of FinFET Based SRAM\u003c/p\u003e","fulltext":[{"header":"1. Introduction","content":"\u003cp\u003eElectronic devices are in high demand in the electronics sector and are utilized in a variety of applications including automobiles, computing, communications, entertainment, artificial intelligence, neural networks, computer vision, big data, and many others [\u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e], in which advanced nanodevice FinFET is used as a transistor instead of MOSFET to achieve high performance, low power dissipation, low area at reduced technology. Channel electrostatics is controlled by single gate MOSFET whereas control of channel in 3 directions to reduce short channel effects is achieved by 3 gate FinFET [\u003cspan citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e, \u003cspan citationid=\"CR3\" class=\"CitationRef\"\u003e3\u003c/span\u003e] For digital circuit, Mixed signal circuit, Analog/RF circuit, FinFET is emerged as superior device to get low power dissipation, high speed, low area at deep submicron range. FinFET can be fabricated in 2 ways one is SOI (silicon on insulator) and alternatively as BULK. Due to the presence of an insulating layer beneath oxide, SOI FinFETs with lower parasitic capacitance increases switching speed and reduces power consumption [\u003cspan citationid=\"CR4\" class=\"CitationRef\"\u003e4\u003c/span\u003e]. RF characteristics, Linearity, is achieved by spacer dielectric optimization.\u003c/p\u003e \u003cp\u003eFor nanoscale applications reduction of leakage is required which in turn reduces and improves system performance [\u003cspan citationid=\"CR4\" class=\"CitationRef\"\u003e4\u003c/span\u003e]. FinFET has well established structure and fabrication due to this TSMC and Intel manufacturing Industries made used from 2011 to till date at sub 22nm technology nodes [\u003cspan citationid=\"CR5\" class=\"CitationRef\"\u003e5\u003c/span\u003e]. SOI FinFET shows reduced device cross talk, lower junction leakage, fully dielectric isolation, lower junction leakage, reduced capacitance, nearly ideal subthreshold slope [\u003cspan additionalcitationids=\"CR7\" citationid=\"CR6\" class=\"CitationRef\"\u003e6\u003c/span\u003e\u0026ndash;\u003cspan citationid=\"CR8\" class=\"CitationRef\"\u003e8\u003c/span\u003e]. FinFET reduces short channel effects by wrapping gate over channel from four sides. Due to continuous scaling FinFET faces several challenges in terms of cost effective, patterning, layout, device performance [\u003cspan additionalcitationids=\"CR10 CR11\" citationid=\"CR9\" class=\"CitationRef\"\u003e9\u003c/span\u003e\u0026ndash;\u003cspan citationid=\"CR12\" class=\"CitationRef\"\u003e12\u003c/span\u003e]. Due to several advantages FinFET can be used in variety of application such as terrestrial systems, infrared detectors, space, satellite communication, nuclear reactor, military [\u003cspan citationid=\"CR12\" class=\"CitationRef\"\u003e12\u003c/span\u003e\u0026ndash;\u003cspan citationid=\"CR13\" class=\"CitationRef\"\u003e13\u003c/span\u003e].\u003c/p\u003e"},{"header":"2.\tReliability Study of FinFET","content":"\u003cp\u003eOne of the most important factors to consider when turning a proof of concept into reality is reliability. It is critical to investigate the dependability of these surface passivation methods in more depth. The specific contact resistance is the most important factor in determining reliability. Under any adversity, the resistance values should not change dramatically. The ITRS (International Technology Roadmap for Semiconductors) developed a number of typical test techniques to ensure reliability. Multiple current stressing is a test that involves repeatedly passing a variable current of quite high amplitude through a test structure. There will be no major performance decrease in a trustworthy framework. Temperature cycling is another more rigorous reliability test that is performed on a regular basis. Repeating the numerous current stressing measurements at different temperatures is part of the experiment. -55\u0026deg;C to +\u0026thinsp;125\u0026deg;C is the standard temperature range. In order to ensure reliability, the test structure should be able to withstand these circumstances without degrading. Last but not least, the test structure should be exposed to a harsher environment to account for variability caused by differing storage circumstances. Over a lengthy period of time, the test structure is normally maintained in a high relative humidity environment (usually RH\u0026thinsp;\u0026gt;\u0026thinsp;60%) and at a high temperature (\u0026gt;\u0026thinsp;100\u0026deg;C) (typically a week or more). To ensure trustworthiness, the repeat measurements should resemble those of the original measurements.\u003c/p\u003e\n\u003cp\u003ePreparation of the substrate, Fin etch, oxide deposition, planarization, recess etch, gate oxide deposition, and ultimately gate deposition was used in the fabrication of the FinFET device. Figure \u003cspan class=\"InternalRef\"\u003e1\u003c/span\u003e shows the TEM cross section of the fabricated FinFET device at 22nm CMOS technology node, whereas Fig. \u003cspan class=\"InternalRef\"\u003e2\u003c/span\u003e shows the corresponding 3D FinFET device structure in Sentaurus Tcad simulation domain.\u003c/p\u003e\n\u003cp\u003ePrior to go for reliability studies, fabricated FinFET device bonded with feeder lines (M1, M2) at low temperature (160 \u0026ordm;C) and low pressure (2.5 mbar) for Kelvin structure design [\u003cspan class=\"CitationRef\"\u003e18\u003c/span\u003e], process flow is explained below. Figure \u003cspan class=\"InternalRef\"\u003e3\u003c/span\u003e shows the cross-sectional TEM of bonded region of the feeder lines. Figure \u003cspan class=\"InternalRef\"\u003e4\u003c/span\u003e shows the complete experimental process flow of reliability study of FinFET device.\u003c/p\u003e\n\u003cdiv class=\"Section2\" id=\"Sec3\"\u003e\n \u003ch2\u003e2.1. Reliability assessment of the Fabricated FinFET using Multiple Current Stressing test\u003c/h2\u003e\n \u003cp\u003eFor applications such as high-speed super-fast multi-core processor design, the electrical performance of the FinFET device is critical, especially when numerous operations are performed. As a result, the constructed Kelvin structure along with FinFET device (with M1,M2 feeders) was treated to 1000 cycles of current stress with magnitudes ranging from \u0026minus;\u0026thinsp;0.1 A to +\u0026thinsp;0.1 A. At room temperature, all measurements were made with a Keithley source measuring unit. Each 100 cycles, the specific resistance was measured.\u003c/p\u003e\n\u003c/div\u003e\n\u003cdiv class=\"Section2\" id=\"Sec4\"\u003e\n \u003ch2\u003e2.2. Reliability assessment of the fabricated FinFET device using Temperature Cycling Test\u003c/h2\u003e\n \u003cp\u003eThe thermal stability test, as per the JESD22-A104B standard, involves subjecting the FinFET device through feeder to 1000 cycles of current sweeping from \u0026minus;\u0026thinsp;0.1 A to +\u0026thinsp;0.1 A at various temperatures ranging from \u0026minus;\u0026thinsp;55 ⁰C to +\u0026thinsp;125 ⁰C. The resistance behavior of a FinFET device specimen pre and post temperature cycles is shown in Fig. \u003cspan class=\"InternalRef\"\u003e6\u003c/span\u003e. It can be inferred from the figure that even at very high and very low temperature the fabricated FinFET device is reliable and there is no deprivation of the specific resistance. As a result, FinFET devices may be viable and efficient at both high and low temperatures.\u003c/p\u003e\n\u003c/div\u003e\n\u003cdiv class=\"Section2\" id=\"Sec5\"\u003e\n \u003ch2\u003e2.3. Reliability assessment of the Fabricated FinFET structure under harsher environment conditions\u003c/h2\u003e\n \u003cp\u003eThe specimens were maintained under harsher environment circumstances for 96 hours, with a high relative humidity (RH) of 65 percent and a high temperature of 130\u0026deg;C, in order to investigate the effect of tougher environmental condition on the produced FinFET. The data taken after this storage correlate extremely well to the ones taken before this retention, as shown in Fig. \u003cspan class=\"InternalRef\"\u003e7\u003c/span\u003e. After such a lengthy period of exposure to harsher environmental results, it is clear that the unique resistance of both CMOS technology situations has not degraded. This shows that FinFET devices produced utilizing both CMOS and CMOS technology is more resistant to dampness and high temperatures.\u003c/p\u003e\n\u003c/div\u003e\n\u003cdiv class=\"Section2\" id=\"Sec6\"\u003e\n \u003ch2\u003e2.4. Electromigration Assessment of the FinFET device post bonding\u003c/h2\u003e\n \u003cp\u003eDuring an EM test, four-point sensing is used to evaluate electrical resistance. As shown in Fig. \u003cspan class=\"InternalRef\"\u003e8\u003c/span\u003e, resistance measurements taken during EM testing demonstrate a latency period during which the resistance remains unchanged, followed by a gradual and then rapid increase.\u003c/p\u003e\n\u003c/div\u003e"},{"header":"3.\tStatic Random Access Memory (SRAM)","content":"\u003cp\u003eCache memory which is made of SRAM cell [9-11] occupies 50% of area in processor the leakage power due to cache memory in processor is the major source of power dissipation [12]. Now a days SRAM is operating in nanometer range in electronic gadgets so, the power dissipation in SRAM should be as low as possible in which leakage currents has to be less and speed should be more. Low power dissipation and more speed in SRAM is obtained by using advanced devices such as FinFET instead of MOSFET. To meet technology scaling new structure challenges have been proposed such as FinFET and Nanowire [13]. FinFET device attracted many SRAM designer\u0026rsquo;s as FinFET has superior short channel effects, reduced dopant fluctuations, independent gating, better subthreshold slope [13,14]. From device level to architecture level many FinFET based SRAM cells have been proposed [15-17]. The trend of SRAM along with CMOS technology scaling in different processors and SOC products has fuelled the need of innovation in the area of SRAM design. Simulation results are carried out for 7nm FinFET based SRAM to analyze the parameters for leakage power, delay and power dissipation which is compared with existing MOSFET device. 7nm FinFET based SRAM shown less leakage, low power, high speed compared to the existing MOSFET based SRAM device as shown in comparison table (Table-1). Schematic diagram of simulated FinFET based SRAM and simulation result shown in Fig. 9 and Fig. 10 respectively.\u003c/p\u003e\n\u003cp\u003eTable 1. Comparison of parameters of 7nm FinFET based SRAM along with conventional MOSFET based SRAM.\u003c/p\u003e\n\u003ctable border=\"1\" cellpadding=\"0\" cellspacing=\"0\"\u003e\n \u003ctbody\u003e\n \u003ctr\u003e\n \u003ctd valign=\"top\" width=\"33.333333333333336%\"\u003e\n \u003cp\u003e\u003cstrong\u003eParameter\u003c/strong\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd valign=\"top\" width=\"33.333333333333336%\"\u003e\n \u003cp\u003e\u003cstrong\u003eMOSFET\u003c/strong\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd valign=\"top\" width=\"33.333333333333336%\"\u003e\n \u003cp\u003e\u003cstrong\u003eFinFET\u003c/strong\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd valign=\"top\" width=\"33.333333333333336%\"\u003e\n \u003cp\u003e\u003cstrong\u003eMode\u003c/strong\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd valign=\"top\" width=\"33.333333333333336%\"\u003e\n \u003cp\u003eWrite \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; Read\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd valign=\"top\" width=\"33.333333333333336%\"\u003e\n \u003cp\u003eWrite \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; Read\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd valign=\"top\" width=\"33.333333333333336%\"\u003e\n \u003cp\u003e\u003cstrong\u003eTechnology\u003c/strong\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd valign=\"top\" width=\"33.333333333333336%\"\u003e\n \u003cp\u003e180nm \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp;180nm\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd valign=\"top\" width=\"33.333333333333336%\"\u003e\n \u003cp\u003e7nm \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; 7nm\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd valign=\"top\" width=\"33.333333333333336%\"\u003e\n \u003cp\u003e\u003cstrong\u003eDelay\u003c/strong\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd valign=\"top\" width=\"33.333333333333336%\"\u003e\n \u003cp\u003e143ps \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp;974ps\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd valign=\"top\" width=\"33.333333333333336%\"\u003e\n \u003cp\u003e96ps \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; 603ps\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd valign=\"top\" width=\"33.333333333333336%\"\u003e\n \u003cp\u003e\u003cstrong\u003eLeakage power\u003c/strong\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd valign=\"top\" width=\"33.333333333333336%\"\u003e\n \u003cp\u003e286nW \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp;793nW\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd valign=\"top\" width=\"33.333333333333336%\"\u003e\n \u003cp\u003e1.6nW \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp;1.98nW\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd valign=\"top\" width=\"33.333333333333336%\"\u003e\n \u003cp\u003e\u003cstrong\u003ePower Dissipation\u003c/strong\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd valign=\"top\" width=\"33.333333333333336%\"\u003e\n \u003cp\u003e1.50nW \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; 618pW\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd valign=\"top\" width=\"33.333333333333336%\"\u003e\n \u003cp\u003e787pW \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; 397pW\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003c/tbody\u003e\n\u003c/table\u003e\n\u003cdiv class=\"Section2\" id=\"Sec6\"\u003e\u003cbr\u003e\u003c/div\u003e"},{"header":"Conclusion","content":"\u003cp\u003eReliability assessment of the experimental FinFET device under 7nm and 22nm is demonstrated under various tests such as temperature cycling test, harsher environment condition, multiple current stress, the results shown that the device structure above to withstand under any circumstances without degrading to ensure reliability. The most important component to decrease or increase performance of system is SRAM memory which is used as cache memory in multiprocessor chip, requires low power dissipation, low leakages, high speed for the future IOT devices which connects nearly $50 billion devices in future. Analysis of leakage and power of SRAM is done using 7nm bsimcmg FinFET file in Mentor Graphic tool which show low power dissipation and high speed compared to the existing MOSFET at high technology node.\u003c/p\u003e"},{"header":"Declarations","content":"\u003cp\u003e\u003cstrong\u003eAcknowledgements\u003c/strong\u003e:- The authors are thankful to the Kakatiya University and Mahatma Gandhi Institute of technology for their co-operation and support during this research work.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eAuthor Contributions\u003c/strong\u003e:-A.Navaneetha : Data Collection, Formal analysis,Simulation,original draft preparation,Dr.K.Bikshalu : Supervision,Conceptualization,methodology.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eFunding:\u003c/strong\u003e No funding received\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eData Availability\u003c/strong\u003e: Not applicable.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eConsent to Participate\u003c/strong\u003e :Yes\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eConsent for Publication\u003c/strong\u003e :Yes\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eFinancial Interests\u003c/strong\u003e : The authors declare they have no Financial interests.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eConflict of Interest\u003c/strong\u003e :The author has no conflicts of interest to declare that are relevant to the content of this article.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eCompliance with Ethical Standards\u003c/strong\u003e: The contents of this manuscript are not now under consideration for publication elsewhere.\u003c/p\u003e\n\u003cp\u003eThe content of this manuscript have not been copyrighted or published previously.\u003c/p\u003e\n\u003cp\u003eThe contents of this manuscript will not be copyrighted, submitted or published elsewhere while acceptance by the journal is under consideration\u003c/p\u003e"},{"header":"References","content":"\u003cp\u003e1.Sahay S,Kumar MJ(2019) Junctionless Field-effect transistors:design,modeling and simulation,Wiley,Hoboken.\u003c/p\u003e\n\u003cp\u003e2.Narendar V,Tripathi S,Naik RBS(2018) \u0026nbsp;A two dimensional(2D) analytical modeling and improved short channel performance of Graded-Channel gate-stack(GCGS) dual-material double-gate(DMDG) MOSFET,Silicon 10(6):2399-2407\u003c/p\u003e\n\u003cp\u003e3.Nowak EJ,Aller I,Ludwig T,Keunwoo Kim,Joshi RV,Ching-te Chaung,Berstein K,Puri R(2004) Turning silicon on its edge double gate CMOS/FinFET technology,IEEE Circ Devices Mag20(1):20-31.\u003c/p\u003e\n\u003cp\u003e4.Sachid AB,Chen M, HuC(2017) Bulk FinFET with low-k spacers for continued scaling,IEEE Trans Electron Devices 64(4):1861-1864\u003c/p\u003e\n\u003cp\u003e5.Bharath Sreenivasulu,Narender Vadthiya Design and deep insights into sub 10nm spacer engineering Junctionless FinFET for Nanoscale applications,ECS journal of solid state science and technology 2021 10 013008.\u003c/p\u003e\n\u003cp\u003e6.E.Yu,K.Heo ,and S.Cho \u0026ldquo;Characterization and optimization of inverted-T FinFET under nanoscale dimensions\u0026rdquo;,IEEE Trans Electron Devices,65,3521(2018).\u003c/p\u003e\n\u003cp\u003e7.Nelapati RP,Sivasankaran S. Impact of self heating effect on the performance of hybrid FinFET, microelectron \u0026nbsp;J 2018;76:63-8.\u003c/p\u003e\n\u003cp\u003e8.Moparthi S,Adarsh KP,Tiwari PK,Saramekala GK,Analog and RF performance evaluation of negative capacitance SOI junctionless transistor,AEU- Int J Electron Commun 2020;122:153243.https://doi.org//10.106/j.aeue.2020.153243.\u003c/p\u003e\n\u003cp\u003e9.Narendar V, etal.Investigation of short channel Effects(SCEs) and Analog/RF Figure of merits(FOMs) of dual Material bottom \u0026ndash; Spacer Ground -Plane(DMBSGP].FinFET 2019;12:2283-91.\u003c/p\u003e\n\u003cp\u003e10.Tamersit k.Sub \u0026ndash; 10nm junctionless carbon nanotube field \u0026ndash; effect transistors with improved performance.AEU \u0026ndash; Int J Electron Commun 2020;124:153354.\u0026nbsp;https://dio.org/10.1016/j.aeue.2020.153354.\u003c/p\u003e\n\u003cp\u003e11.J.P.Colinge etal.,Junctionless transistors: Physics and properities.Semiconductor-on-Insulator Materials for Nanoelectronics Applications, Engineering Materials, New York,NY,USA :Springer -Verlag,2011,pp.187-200.\u003c/p\u003e\n\u003cp\u003e12.Colinge \u0026nbsp;J-P,Lee C-W,Afzalian A,Akhavan ND,Yan R,Ferain I,et al .Nanowire Transistors without Junctions.Nat Nanotechnol 2010;5(3):225-9.\u003c/p\u003e\n\u003cp\u003e13.Vadthiya N,Narware P,Bheemudu V,Sunitha B.A novel bottom-spacer ground \u0026ndash; plane(BSGP) \u0026nbsp; FinFET for improved logic and analog/RF performance.AEU \u0026ndash; Int J Electro Commun 2020;127:153459.https://doi.org/10.1016/j.aeue.2020.153459.\u003c/p\u003e\n\u003cp\u003e14.Dhanumjayal,M.Sudha,Dr.M.N.GiriPrasad,Dr.K.Padmaraju \u0026ldquo;Cell stability analysis of conventional 6T dynamic 8T SRAM cell in 45nm technology\u0026rdquo;, international journal of VLSI design and communication systems(VLSICs) Vol.3,No.2,April 2012.\u003c/p\u003e\n\u003cp\u003e15.J.Sallese,N.Chevillon,C.Lallement,B.Iniguez, and F.Pregaldiny,\u0026rdquo;Charge based modelling of Junctionless double gate Field Effect Trasnsistors\u0026rdquo;,IEEE Trans Electronic devices,58,2628(2011).\u003c/p\u003e\n\u003cp\u003e16.A.Carlson,Z.Guo,S.Balasubramanian,R.Zlatanovici,T.K.Liu,B.Nikolic,SRAM Read/Write margin enhancements using FinFETs,IEEE Trans Very Large Scale Integr,Syst.18(6) (June,2010) 887-900.\u003c/p\u003e\n\u003cp\u003e17.L.Baghriye,S.Toofan,R.Saeidi,F.Moradi,offset-Compensated high Speed Sense Amplifier for \u0026nbsp;STT \u0026ndash; MRAMs,IEEE Trans Very Large Scale Integr,June(2018),1051-1058.\u003c/p\u003e\n\u003cp\u003e18. A.K. Panigrahi, S. Bonam, T. Ghosh, S.G. Singh, and S.R.K. Vanjari, 2016. Ultra-thin Ti passivation mediated breakthrough in high quality Cu-Cu bonding at low temperature and pressure. Materials Letters, 169, pp.269-272.\u003c/p\u003e"}],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":true,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":false,"highlight":"","institution":"","isAcceptedByJournal":true,"isAuthorSuppliedPdf":false,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":true,"isPdf":false,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"silicon","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":false,"externalIdentity":"scon","sideBox":"Learn more about [Silicon](https://www.springer.com/journal/12633)","snPcode":"12633","submissionUrl":"https://submission.nature.com/new-submission/12633/3","title":"Silicon","twitterHandle":"","acdcEnabled":true,"dfaEnabled":true,"editorialSystem":"em","reportingPortfolio":"Springer Hybrid","inReviewEnabled":true,"inReviewRevisionsEnabled":false},"keywords":"MOSFET, FinFET, SRAM, SOI, SCE, Reliability, ITRS.","lastPublishedDoi":"10.21203/rs.3.rs-759064/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-759064/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eDemand for accommodating more and new functionalities within a single chip such as SOC needs a novel devices and architecture such as FinFET device instead of MOSFET. FinFET is emerged as non-planar, multigate device to overcome short channel effects such as subthreshold swing deterioration, drain induced barrier lowering, threshold voltage roll off which degrade circuit performance. As the need of device technology is mounting in electronic gadgets the important parameters are taken into consideration such as low leakage, high reliability, low power dissipation, and high operating speed. Reliability is one of key considerations in converting a proof of concept into reality. In this work Reliability of FinFET device is studied experimentally according to ITRS (international technology roadmap for semiconductor) roadmap using several standard test protocols such as multiple current stressing, harsher environment conditions, and effect of electromigration. Furthermore, power analysis of FinFET based SRAM is done by using 7nm bsimcmg PTM files in mentor graphics tool. The FinFET based SRAM shown low leakage, power dissipation, delay compared to existing conventional MOSFET based SRAM.\u003c/p\u003e","manuscriptTitle":"Reliability and Power Analysis of FinFET Based SRAM","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2021-08-03 19:54:26","doi":"10.21203/rs.3.rs-759064/v1","editorialEvents":[{"type":"communityComments","content":0},{"type":"editorInvitedReview","content":"","date":"2021-07-29T10:31:44+00:00","index":0,"fulltext":""},{"type":"reviewersInvited","content":"","date":"2021-07-29T10:16:38+00:00","index":"","fulltext":""},{"type":"editorAssigned","content":"","date":"2021-07-28T22:32:36+00:00","index":"","fulltext":""},{"type":"submitted","content":"Silicon","date":"2021-07-28T02:24:09+00:00","index":"","fulltext":""}],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"silicon","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":false,"externalIdentity":"scon","sideBox":"Learn more about [Silicon](https://www.springer.com/journal/12633)","snPcode":"12633","submissionUrl":"https://submission.nature.com/new-submission/12633/3","title":"Silicon","twitterHandle":"","acdcEnabled":true,"dfaEnabled":true,"editorialSystem":"em","reportingPortfolio":"Springer Hybrid","inReviewEnabled":true,"inReviewRevisionsEnabled":false}}],"origin":"","ownerIdentity":"938121dc-5d2c-44b7-bb28-8b70380e042e","owner":[],"postedDate":"August 3rd, 2021","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"under-review","subjectAreas":[{"id":6167524,"name":"Electronic Materials and Devices"},{"id":6167525,"name":"Magnetics Materials and Devices"}],"tags":[],"updatedAt":"2021-08-20T10:32:42+00:00","versionOfRecord":[],"versionCreatedAt":"2021-08-03 19:54:26","video":"","vorDoi":"","vorDoiUrl":"","workflowStages":[]},"version":"v1","identity":"rs-759064","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-759064","identity":"rs-759064","version":["v1"]},"buildId":"_2-kVJe1T_tPrBINL-cwx","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}